E-tile Hard IP User Guide E-tile Hard IP for Ethernet and E-Tile CPRI PHY Intel FPGA IPs Updated for Intel® Quartus® Prime Design Suite: 19.1 Subscribe UG-20160 | 2019.05.17 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. About E-tile Hard IP User Guide...................................................................................... 4 2. About the E-tile Hard IP for Ethernet Intel FPGA IP Core................................................ 5 2.1. E-tile Hard IP for Ethernet Intel FPGA IP Supported Features....................................... 7 2.2. E-tile Hard IP for Ethernet Intel FPGA IP Overview....................................................10 2.3. IP Core Device Family and Speed Grade Support......................................................15 2.3.1. E-tile Hard IP for Ethernet Intel FPGA IP Device Family Support......................15 2.3.2. E-tile Hard IP for Ethernet Intel FPGA IP Device Speed Grade Support.............16 2.4. IP Core Verification.............................................................................................. 16 2.4.1. Simulation Environment............................................................................16 2.4.2. Compilation Checking............................................................................... 16 2.4.3. Hardware Testing..................................................................................... 16 2.5. Resource Utilization..............................................................................................17 2.6. Release Information............................................................................................. 18 2.7. Getting Started....................................................................................................18 2.7.1. Installing and Licensing Intel FPGA IP Cores................................................ 19 2.7.2. Specifying the IP Core Parameters and Options............................................ 22 2.7.3. Generated File Structure........................................................................... 22 2.7.4. Integrating Your IP Core in Your Design...................................................... 24 2.7.5. IP Core Testbenches................................................................................. 35 2.7.6. Compiling the Full Design..........................................................................35 2.8. E-tile Hard IP for Ethernet Intel FPGA IP Parameters.................................................35 2.8.1. Parameter Editor Parameters..................................................................... 35 2.8.2. RTL Parameters....................................................................................... 47 2.9. Functional Description.......................................................................................... 48 2.9.1. E-tile Hard IP for Ethernet Intel FPGA IP MAC ............................................. 51 2.9.2. PCS, OTN, FlexE, and Custom PCS Modes....................................................70 2.9.3. Auto-Negotiation and Link Training............................................................. 74 2.9.4. TX and RX RS-FEC................................................................................... 74 2.9.5. PMA Direct Mode......................................................................................75 2.9.6. Dynamic Reconfiguration.......................................................................... 75 2.10. Reset................................................................................................................76 2.10.1. Reset Sequence..................................................................................... 79 2.11. Interfaces and Signals........................................................................................ 79 2.11.1. TX MAC Interface to User Logic................................................................ 80 2.11.2. RX MAC Interface to User Logic................................................................ 85 2.11.3. TX PCS Interface to User Logic.................................................................88 2.11.4. RX PCS Interface to User Logic.................................................................91 2.11.5. FlexE and OTN Mode TX Interface.............................................................94 2.11.6. FlexE and OTN Mode RX Interface............................................................ 96 2.11.7. TX Custom PCS Interface to User Logic..................................................... 98 2.11.8. RX Custom PCS Interface to User Logic................................................... 101 2.11.9. PMA Direct Interface............................................................................. 103 2.11.10. Custom Rate Interface.........................................................................103 2.11.11. Deterministic Latency Interface............................................................ 104 2.11.12. 1588 PTP Interface............................................................................. 105 2.11.13. Ethernet Link and Transceiver Signals....................................................109 E-tile Hard IP User Guide: E-tile Hard IP for Ethernet and E-Tile CPRI PHY Send Feedback Intel FPGA IPs 2 Contents 2.11.14. Reconfiguration Interfaces and Signals.................................................. 110 2.11.15. Miscellaneous Status and Debug Signals................................................ 114 2.11.16. Reset Signals..................................................................................... 115 2.11.17. Clocks...............................................................................................116 2.12. Reconfiguration and Status Register Descriptions..................................................128 2.12.1. Auto Negotiation and Link Training Registers............................................ 129 2.12.2. PHY Registers...................................................................................... 143 2.12.3. TX MAC Registers................................................................................. 166 2.12.4. RX MAC Registers................................................................................. 170 2.12.5. Pause and Priority- Based Flow Control Registers...................................... 172 2.12.6. TX Statistics Counter Registers...............................................................193 2.12.7. RX Statistics Counter Registers...............................................................198 2.12.8. 1588 PTP Registers...............................................................................202 2.12.9. RS-FEC Registers..................................................................................204 2.12.10. PMA Registers.................................................................................... 205 3. About the E-Tile CPRI PHY.......................................................................................... 206 3.1. Supported Features............................................................................................ 206 3.2. E-Tile CPRI PHY Intel FPGA IP Overview................................................................ 206 3.3. E-Tile CPRI PHY Device Family Support..................................................................208 3.4. Resource Utilization............................................................................................209 3.5. Release Information........................................................................................... 209 3.6. E-Tile CPRI PHY Intel FPGA IP Core Device Speed Grade Support.............................. 209 3.7. Getting Started..................................................................................................209 3.7.1. Installing and Licensing Intel FPGA IP Cores...............................................209 3.7.2. Specifying the IP Core Parameters and Options.......................................... 212 3.7.3. Generated File Structure......................................................................... 213 3.7.4. E-Tile CPRI PHY Intel FPGA IP Channel Placement....................................... 215 3.7.5. IP Core Testbenches............................................................................... 215 3.7.6. Compiling the Full Design........................................................................ 216 3.8. Parameter Settings.............................................................................................216 3.9. Functional Description.........................................................................................217 3.9.1. CPRI PHY Functional Blocks..................................................................... 217 3.10. E-Tile CPRI PHY Intel FPGA IP Interface Signals.................................................... 221 3.10.1. Clock Signals....................................................................................... 221 3.10.2. TX MII Interface...................................................................................223 3.10.3. RX MII Interface...................................................................................224 3.10.4. Status Interface for 64B/66B Line Rate....................................................225 3.10.5. Serial I/O Pins......................................................................................225 3.10.6. Reconfiguration Interfaces (Avalon-MM)...................................................225