LC2MOS a Complete 14-Bit DAC AD7840 FEATURES FUNCTIONAL BLOCK DIAGRAM Complete 14-Bit Voltage Output DAC Parallel and Serial Interface Capability 80 dB Signal-to-Noise Ratio Interfaces to High Speed DSP Processors e.g., ADSP-2100, TMS32010, TMS32020 45 ns min WR Pulse Width Low Power – 70 mW typ. Operates from 65 V Supplies GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7840 is a fast, complete 14-bit voltage output D/A con- 1. Complete 14-Bit D/A Function verter. It consists of a 14-bit DAC, 3 V buried Zener reference, The AD7840 provides the complete function for creating ac DAC output amplifier and high speed control logic. signals and dc voltages to 14-bit accuracy. The part features The part features double-buffered interface logic with a 14-bit an on-chip reference, an output buffer amplifier and 14-bit input latch and 14-bit DAC latch. Data is loaded to the input D/A converter. latch in either of two modes, parallel or serial. This data is then 2. Dynamic Specifications for DSP Users transferred to the DAC latch under control of an asynchronous In addition to traditional dc specifications, the AD7840 is LDAC signal. A fast data setup time of 21 ns allows direct specified for ac parameters including signal-to-noise ratio and parallel interfacing to digital signal processors and high speed harmonic distortion. These parameters along with important 16-bit microprocessors. In the serial mode, the maximum serial timing parameters are tested on every device. data clock rate can be as high as 6 MHz. 3. Fast, Versatile Microprocessor Interface The analog output from the AD7840 provides a bipolar output The AD7840 is capable of 14-bit parallel and serial interfac- range of ±3 V. The AD7840 is fully specified for dynamic per- ing. In the parallel mode, data setup times of 21 ns and write formance parameters such as signal-to-noise ratio and harmonic pulse widths of 45 ns make the AD7840 compatible with distortion as well as for traditional dc specifications. Full power modern 16-bit microprocessors and digital signal processors. output signals up to 20 kHz can be created. In the serial mode, the part features a high data transfer rate The AD7840 is fabricated in linear compatible CMOS of 6 MHz. (LC2MOS), an advanced, mixed technology process that com- bines precision bipolar circuits with low power CMOS logic. The part is available in a 24-pin plastic and hermetic dual-in-line package (DIP) and is also packaged in a 28-termi- nal plastic leaded chip carrier (PLCC). REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703 (VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = O V, REF IN = +3 V, RL = 2 kV, AD7840–SPECIFICATIONS CL = 100 pF. All specifications TMIN to TMAX unless othewise noted.) Parameter J, A1 K, B1 S1 Units Test Conditions/Comments DYNAMIC PERFORMANCE2 3 Signal to Noise Ratio (SNR) 76 78 76 dB min VOUT = 1 kHz Sine Wave, fSAMPLE = 100 kHz 4 Typically 82 dB at +25°C for 0 < VOUT < 20 kHz Total Harmonic Distortion (THD) –78 –80 –78 dB max VOUT = 1 kHz Sine Wave, fSAMPLE = 100 kHz 4 Typically –84 dB at +25°C for 0 < VOUT < 20 kHz Peak Harmonic or Spurious Noise –78 –80 –78 dB max VOUT = 1 kHz Sine Wave, fSAMPLE = 100 kHz 4 Typically –84 dB at +25°C for 0 < VOUT < 20 kHz DC ACCURACY Resolution 14 14 14 Bits Integral Nonlinearity ±2 ±1 ±2 LSB max Differential Nonlinearity ±0.9 ±0.9 ±0.9 LSB max Guaranteed Monotonic Bipolar Zero Error ±10 ±10 ±10 LSB max Positive Full Scale Error5 ±10 ±10 ±10 LSB max Negative Full Scale Error5 ±10 ±10 ±10 LSB max REFERENCE OUTPUT6 REF OUT @ +25°C 2.99 2.99 2.99 V min 3.01 3.01 3.01 V max REF OUT TC ±60 ±60 ±60 ppm/°C max Reference Load Change (∆REF OUT vs. ∆I) –1 –1 –1 mV max Reference Load Current Change (0–500 µA) REFERENCE INPUT Reference Input Range 2.85 2.85 2.85 V min 3 V ± 5% 3.15 3.15 3.15 V max Input Current 50 50 50 µA max LOGIC INPUTS Input High Voltage, VINH 2.4 2.4 2.4 V min VDD = 5 V ± 5% Input Low Voltage, VINL 0.8 0.8 0.8 V max VDD = 5 V ± 5% Input Current, IIN ±10 ±10 ±10 µA max VIN = 0 V to VDD Input Current (CS Input Only) ±10 ±10 ±10 µA max VIN =VSS to VDD 7 Input Capacitance, CIN 10 10 10 pF max ANALOG OUTPUT Output Voltage Range ±3 ±3 ±3 V nom DC Output Impedance 0.1 0.1 0.1 Ω typ Short-Circuit Current 20 20 20 mA typ AC CHARACTERISTICS7 Voltage Output Settling Time Settling Time to within ±1/2 LSB of Final Value Positive Full-Scale Change 4 4 4 µs max Typically 2 µs Negative Full-Scale Change 4 4 4 µs max Typically 2.5 µs Digital-to-Analog Glitch Impulse 10 10 10 nV secs typ Digital Feedthrough 2 2 2 nV secs typ POWER REQUIREMENTS VDD +5 +5 +5 V nom ±5% for Specified Performance VSS –5 –5 –5 V nom ±5% for Specified Performance IDD 14 14 15 mA max Output Unloaded, SCLK = +5 V. Typically 10 mA ISS 6 6 7 mA max Output Unloaded, SCLK = +5 V. Typically 4 mA Power Dissipation 100 100 110 mW max Typically 70 mW NOTES 1Temperature ranges are as follows: J, K Versions, 0°C to +70°C; A, B Versions, –25°C to +85°C; S Version, –55°C to +125°C. 2 VOUT (pk-pk) = ±3 V 3SNR calculation includes distortion and noise components. 4Using external sample-and-hold (see Testing the AD7840). 5Measured with respect to REF IN and includes bipolar offset error. 6For capacitive loads greater than 50 pF, a series resistor is required (see Internal Reference section). 7Sample tested @ +25°C to ensure compliance. Specifications subject to change without notice. –2– REV. B AD7840 1, 2 TIMING CHARACTERISTICS (VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = 0 V.) Limit at TMIN, TMAX Limit at TMIN, TMAX Parameter (J, K, A, B Versions) (S Version) Units Conditions/Comments t1 0 0 ns min CS to WR Setup Time t2 0 0 ns min CS to WR Hold Time t3 45 50 ns min WR Pulse Width t4 21 28 ns min Data Valid to WR Setup Time t5 10 15 ns min Data Valid to WR Hold Time t6 40 40 ns min LDAC Pulse Width t7 50 50 ns min SYNC to SCLK Falling Edge 3 t8 150 200 ns min SCLK Cycle Time t9 30 40 ns min Data Valid to SCLK Setup Time t10 75 100 ns min Data Valid to SCLK Hold Time t11 75 100 ns min SYNC to SCLK Hold Time NOTES 1Timing specifications in bold print are 100% production tested. All other times are sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2See Figures 6 and 8. 3SCLK mark/space ratio is 40/60 to 60/40. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE V to AGND . –0.3 V to +7 V DD Integral VSS to AGND . +0.3 V to –7 V Temperature SNR Nonlinearity Package AGND to DGND . –0.3 V to VDD + 0.3 V Model1 Range (dB) (LSB) Option2 VOUT to AGND . VSS to VDD ° ° ± REF OUT to AGND . 0 V to VDD AD7840JN 0 C to +70 C 78 min 2 max N-24 ° ° ± REF IN to AGND . –0.3 V to VDD + 0.3 V AD7840KN 0 C to +70 C 80 min 1 max N-24 ° ° ± Digital Inputs to DGND . –0.3 V to VDD + 0.3 V AD7840JP 0 C to +70 C 78 min 2 max P-28A Operating Temperature Range AD7840KP 0°C to +70°C 80 min ±1 max P-28A Commercial (J, K Versions) . 0°C to +70°C AD7840AQ –25°C to +85°C 78 min ±2 max Q-24 Industrial (A, B Versions) . –25°C to +85°C AD7840ARS –25°C to +85°C 78 min ±2 max RS-24 ° ° ± Extended (S Version) . –55°C to +125°C AD7840BQ –25 C to +85 C 80 min 1 max Q-24 3 ° ° ± Storage Temperature Range . –65°C to +150°C AD7840SQ –55 C to +125 C 78 min 2 max Q-24 Lead Temperature (Soldering, 10 sec) . +300°C NOTES Power Dissipation (Any Package) to +75°C . 450 mW 1To order MIL-STD-883, Class B processed parts, add /883B to part number. Derates above +75°C by . 10 mW/°C Contact your local sales office for military data sheet and availability. 2N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip. *Stresses above those listed under “Absolute Maximum Ratings” may cause 3This grade will be available to /883B processing only.