Vivado Design Suite User Guide High-Level Synthesis UG902 (v2018.3) December 20, 2018 Revision History Revision History The following table shows the revision history for this document. Section Revision Summary 12/20/2018 Version 2018.3 Schedule Viewer Updated information on the schedule viewer. Optimizing the Design Clarified information on dataflow and loops throughout section. C++ Arbitrary Precision Fixed-Point Types: Reference Added note on using header files. Information HLS Math Library Updated information on how hls_math.h is used. The HLS Math Library, Fixed-Point Math Functions Updated functions. HLS Video Library, HLS Video Functions Library Moved the HLS video library to the Xilinx GitHub (https:// github.com/Xilinx/xfopencv) HLS SQL Library, HLS SQL Library Functions Updated hls::db to hls::alg functions. System Calls Added information on using the __SYNTHESIS__ macro. Arrays Added information on array sizing behavior. Command Reference Updated commands. config_dataflow, config_rtl Added the option -disable_start_propagation Class Methods, Operators, and Data Members Added guidance on specifying data width. UG902 (v2018.3) December 20, 2018Send Feedback www.xilinx.com High-Level Synthesis 2 Table of Contents Revision History...............................................................................................................2 Chapter 1: High-Level Synthesis............................................................................ 5 High-Level Synthesis Benefits....................................................................................................5 High-Level Synthesis Basics....................................................................................................... 6 Understanding Vivado HLS...................................................................................................... 12 Using Vivado HLS...................................................................................................................... 19 Data Types for Efficient Hardware.......................................................................................... 71 Managing Interfaces.................................................................................................................77 Optimizing the Design............................................................................................................119 Verifying the RTL..................................................................................................................... 176 Exporting the RTL Design.......................................................................................................189 Chapter 2: High-Level Synthesis C Libraries................................................196 Arbitrary Precision Data Types Library.................................................................................196 HLS Stream Library................................................................................................................. 211 HLS Math Library.....................................................................................................................220 HLS Video Library.................................................................................................................... 231 HLS IP Libraries........................................................................................................................231 HLS Linear Algebra Library.................................................................................................... 254 HLS DSP Library....................................................................................................................... 265 HLS SQL Library....................................................................................................................... 267 Chapter 3: High-Level Synthesis Coding Styles..........................................269 Unsupported C Constructs.....................................................................................................269 C Test Bench.............................................................................................................................273 Functions.................................................................................................................................. 280 Loops........................................................................................................................................ 282 Arrays........................................................................................................................................289 Data Types................................................................................................................................299 C Builtin Functions.................................................................................................................. 324 Hardware Efficient C Code..................................................................................................... 325 UG902 (v2018.3) December 20, 2018Send Feedback www.xilinx.com High-Level Synthesis 3 C++ Classes and Templates....................................................................................................343 Assertions.................................................................................................................................351 SystemC Synthesis.................................................................................................................. 354 Chapter 4: High-Level Synthesis Reference Guide...................................373 Command Reference.............................................................................................................. 373 GUI Reference..........................................................................................................................447 Interface Synthesis Reference............................................................................................... 451 AXI4-Lite Slave C Driver Reference........................................................................................469 HLS Video Functions Library.................................................................................................. 482 HLS Linear Algebra Library Functions.................................................................................. 482 HLS DSP Library Functions..................................................................................................... 491 HLS SQL Library Functions..................................................................................................... 504 C Arbitrary Precision Types.................................................................................................... 507 C++ Arbitrary Precision Types................................................................................................ 521 C++ Arbitrary Precision Fixed-Point Types........................................................................... 541 Comparison of SystemC and Vivado HLS Types..................................................................564 Appendix A: Additional Resources and Legal Notices........................... 571 Xilinx Resources.......................................................................................................................571 Documentation Navigator and Design Hubs...................................................................... 571 References................................................................................................................................572 Please Read: Important Legal Notices................................................................................. 572 UG902 (v2018.3) December 20, 2018Send Feedback www.xilinx.com High-Level Synthesis 4 Chapter 1 High-Level Synthesis The Xilinx® Vivado® High-Level Synthesis (HLS) tool transforms a C specification into a register transfer level (RTL) implementation that you can synthesize into a Xilinx field programmable gate array (FPGA). You can write C specifications in C, C++, or SystemC, and the FPGA provides a massively parallel architecture with benefits in performance, cost, and power over traditional processors. This chapter provides an overview of high-level synthesis. Note: For more information on FPGA architectures and Vivado HLS basic concepts, see the Introduction to FPGA Design Using High-Level Synthesis (UG998). High-Level Synthesis Benefits High-level synthesis bridges hardware and software domains, providing the following primary benefits: • Improved productivity for hardware designers Hardware designers can work at a higher level of abstraction while creating high-performance hardware. • Improved system performance for software designers Software developers can accelerate the computationally intensive parts of their algorithms on a new compilation target, the FPGA. Using a high-level synthesis design methodology allows you to: • Develop algorithms at the C-level Work at a level that is abstract from the implementation details, which consume development time. • Verify at the C-level Validate the functional correctness of the design more quickly than with traditional hardware description languages. • Control the C synthesis process through optimization directives Create specific high-performance hardware implementations. • Create multiple implementations from the C source code using optimization directives UG902 (v2018.3) December 20, 2018Send Feedback www.xilinx.com High-Level Synthesis 5 Chapter