See all versions of this document MicroBlaze Processor Reference Guide UG984 (v2020.1) June 3, 2020 Revision History The following table shows the revision history for this document. Date Version Revision 06/03/2020 2020.1 Updated for Vivado 2020.1 release • Added ELF format description. • Describe Memory Protection feature in more detail. • Clarified Peripheral Data AXI write behavior. • Define FINT and DLONG instruction rounding behavior. 10/30/2019 2019.2 Updated for Vivado 2019.2 release: • Updated description of 64-bit immediate instructions with added opcodes. • Clarified reset behavior. •Replaced SDK with Vitis. • Added Block-RAM count to resource utilization tables. 24/04/2019 2019.1 Updated for Vivado 2019.1 release: • Added information about cache reset behavior. • Included calling convention for variable argument functions. • Corrected WDC pseudo code. • Provided link to MicroBlaze pages on the Xilinx Wiki. 11/14/2018 2018.3 Updated for Vivado 2018.3 release: • Added description of MicroBlaze 64-bit implementation, new in version 11.0. 04/04/2018 2018.1 Updated for Vivado 2018.1 release: • Included information about instruction pipeline hazards and forwarding. • Clarified that software break does not set the BIP bit in MSR. • Explained memory scrubbing behavior. • Added more detailed description of sleep and pause usage. • Clarified use of parallel debug clock and reset. 10/04/2017 2017.3 Updated for Vivado 2017.3 release: • Added automotive UltraScale+ Zynq and Spartan-7 devices. • Updated description of debug trace, to add event trace, new in version 10.0. • Added 4PB extended address size. • Clarified description of cache trace signals. 04/05/2017 2017.1 Updated for Vivado 2017.1 release: • Added description of MMU Physical Address Extension (PAE), new in version 10.0. • Extended privileged instruction list, and updated instruction descriptions. • Updated information on debug program trace. • Added reference to the Triple Modular Redundancy (TMR) subsystem. • Corrected description of BSIFI instruction. • Updated MFSE instruction description with PAE information. • Added MTSE instruction used with PAE, new in version 10.0. • Updated WDC instruction for external cache invalidate and flush. MicroBlaze Processor Reference Guide Send Feedback 2 UG984 (v2020.1) June 3, 2020 www.xilinx.com Date Version Revision 10/05/2016 2016.3 Updated for Vivado 2016.3 release: • Added description of frequency optimized 8-stage pipeline, new in version 10.0. • Describe bit field instructions, new in version 10.0. • Include information on parallel debug interface, new in version 10.0. • Added version 10.0 to MicroBlaze release version code in PVR. • Included Spartan-7 target architecture in PVR. • Updated description of MSR reset value. • Updated Xilinx 04/06/2016 2016.1 Updated for Vivado 2016.1 release: • Included description of address extension, new in version 9.6. • Included description of pipeline pause functionality, new in version 9.6 • Included description of non-secure AXI access support, new in version 9.6. • Included description of hibernate and suspend instructions, new in version 9.6. • Added version 9.6 to MicroBlaze release version code in PVR. • Corrected references to Table 2-47 and Table 2-48. • Replaced references to the deprecated Xilinx Microprocessor Debugger (XMD) with Xilinx System Debugger (XSDB). • Removed C code function attributes svc_handler and svc_table_handler. 04/15/2015 2015.1 Updated for Vivado 2015.1 release: • Included description of 16 word cache line length, new in version 9.5. • Added version 9.5 to MicroBlaze release version code in PVR. • Corrected description of supported endianness and parameter C_ENDIANNESS. • Corrected description of outstanding reads for instruction and data cache. • Updated FPGA configuration memory protection document reference [Ref 5]. • Corrected Bus Index Range definitions for Lockstep Comparison in Table 3-14. • Clarified registers altered for IDIV instruction. • Corrected PVR assembler mnemonics for MFS instruction. • Updated performance and resource utilization for 2015.1. • Added references to training resources. 10/01/2014 2014.3 Updated for Vivado 2014.3 release: • Corrected semantic description for PCMPEQ and PCMPNE in Table 2.1. • Added version 9.4 to MicroBlaze release version code in PVR. • Included description of external program trace, new in version 9.4 04/02/2014 2014.1 Updated for Vivado 2014.1 release: • Added v9.3 to MicroBlaze release version code in PVR. • Clarified availability and behavior of stack protection registers. • Corrected description of LMB instruction and data bus exception. • Included description of extended debug features, new in version 9.3: performance monitoring, program trace and non-intrusive profiling. • Included definition of Reset Mode signals, new in version 9.3. • Clarified how the AXI4-Stream TLAST signal is handled. • Added UltraScale and updated performance and resource utilization for 2014.1. 12/18/2013 2013.4 Updated for Vivado 2013.4 release. 10/02/2013 2013.3 Updated for Vivado 2013.3 release. 06/19/2013 2013.2 Updated for Vivado 2013.2 release. 03/20/2013 2013.1 Initial Xilinx release. This User Guide is derived from UG081. MicroBlaze Processor Reference Guide Send Feedback 3 UG984 (v2020.1) June 3, 2020 www.xilinx.com Table of Contents Chapter 1: Introduction Guide Contents. 6 Chapter 2: MicroBlaze Architecture Introduction . 7 Overview . 7 Data Types and Endianness. 11 Instructions. 13 Registers . 28 Pipeline Architecture . 55 Memory Architecture . 61 Privileged Instructions . 62 Virtual-Memory Management . 64 Reset, Interrupts, Exceptions, and Break . 79 Instruction Cache . 89 Data Cache . 93 Floating-Point Unit (FPU). 98 Stream Link Interfaces . 104 Debug and Trace . 105 Fault Tolerance. 128 Lockstep Operation . 136 Coherency. 139 Data and Instruction Address Extension . 142 Chapter 3: MicroBlaze Signal Interface Description Introduction . 144 Overview . 144 MicroBlaze I/O Overview . 145 AXI4 and ACE Interface Description . 158 Local Memory Bus (LMB) Interface Description . 164 Lockstep Interface Description . 173 Debug Interface Description . 178 Trace Interface Description . 180 MicroBlaze Processor Reference Guide Send Feedback 4 UG984 (v2020.1) June 3, 2020 www.xilinx.com MicroBlaze Core Configurability . 183 Chapter 4: MicroBlaze Application Binary Interface Introduction . 195 Data Types . 195 Register Usage Conventions . 196 Stack Convention . 198 Memory Model . 200 Interrupt, Break and Exception Handling. 201 Reset Handling . 203 ELF Format . 204 Chapter 5: MicroBlaze Instruction Set Architecture Introduction . 208 Notation . 208 Formats. 210 MicroBlaze 32-bit Instructions . 210 MicroBlaze 64-bit Instructions . 319 Appendix A: Performance and Resource Utilization Performance. ..