Agenda Introduction: Session 3: SystemVerilog Assertions SystemVerilog Motivation Language Tutorial Vassilios Gerousis, Infineon Technologies Bassam Tabbara, Novas Software Accellera Technical Committee Chair Tecnhology and User Experience Session 1: Alon Flaisher, Intel SystemVerilog for Design Using SystemVerilog Assertions Language Tutorial and Testbench Together Johny Srouji, Intel Jon Michelson, Verification Central User Experience Matt Maidment, Intel Session 4: SystemVerilog APIs Doug Warmke, Model Technology Session 2: Session 5: SystemVerilog Momentum SystemVerilog for Verification Verilog2001 to SystemVerilog Language Tutorial Stuart Sutherland, Sutherland HDL Tom Fitzpatrick, Synopsys User Experience SystemVerilog Industry Support Faisal Haque, Verification Central Vassilios Gerousis, Infineon Lunch: 12:15 – 1:00pm End: 5:00pm 29 DAC2003 Accellera SystemVerilog Workshop SystemVerilog 3.1 Design Subset Johny Srouji Intel Chair – SV-Basic Committee 30 DAC2003 Accellera SystemVerilog Workshop Presentation Outline • Data Types • Structures & Unions • Literals • Enumerated Data Types • Constants & Parameters • Scope & Lifetime • Interfaces 31 DAC2003 Accellera SystemVerilog Workshop Basic SV3.1 Data Types reg r; // 4-state Verilog-2001 single-bit datatype integer i; // 4-state Verilog-2001 >= 32-bit datatype bit b; // single bit 0 or 1 logic w; // 4-valued logic, x 0 1 or z as in Verilog byte b8; // 8 bit signed integer int i; // 2-state, 32-bit signed integer shortint s;// 2-state, 16-bit signed integer longint l; // 2-state, 64-bit signed integer Make your own types using typedef Use typedef to get C compatibility typedef shortint short; typedef longint longlong; typedef real double; typedef shortreal float; 32 DAC2003 Accellera SystemVerilog Workshop 2 State and 4 State Data Types Verilog reg and integer Verilog reg a; integer i; type bits can contain x SystemVerilog and z values Equivalent to these logic a; SystemVerilog logic signed [31:0] i; 4-valued SystemVerilog types bit a; SystemVerilog These SystemVerilog int i; types have two-valued bits (0 and 1) IfIf youyou don'tdon't needneed thethe XX andand ZZ valuesvalues thenthen useuse thethe SystemVerilogSystemVerilog bitbit andand intint typestypes whichwhich MAKEMAKE EXECUTIONEXECUTION FASTERFASTER 33 DAC2003 Accellera SystemVerilog Workshop Packed And Unpacked Arrays unpacked bit a [3:0]; a0 a1 array of unused a2 bits a3 Don’t get them mixed up packed array of bit [3:0] p; p3 p2 p1 p0 bits bit [15:0] memory [1023:0]; 1k 16 bit memory[i] = ~memory[i]; unpacked memory[i] [15:8] = 0; memory Packed indexes can be sliced 1k 16 bit Can operate on packed bit [15:0] [1023:0] Frame; entire memory always @inv Frame = ~Frame; memory 34 DAC2003 Accellera SystemVerilog Workshop Structures struct { bit [7:0] opcode; bit [23:0] addr; } IR; // anonymous structure LikLikee in in C C but but without without thethe optional optional structure structure tagstags before before the the { { typedef struct { bit [7:0] opcode; bit [23:0] addr; } instruction; // named structure type instruction IR; // define variable IR.opcode = 1; // set field in IR 35 DAC2003 Accellera SystemVerilog Workshop Unions typedef union { union int n; real f; provide storage for again,again, like like in in C C } u_type; either int or real u_type u; structs and unions can be initial assigned as a whole begin Can be passed through u.n = 27; int tasks/functions/ports as a $display("n=%d", u.n); whole u.f = 3.1415; real $display("f=%f",u.f); can contain fixed size packed $finish(0); or unpacked arrays end 36 DAC2003 Accellera SystemVerilog Workshop Packed Structures Represents bit or part selects of vectors struct packed { reg [24:0] Entry; bit Valid; `define Valid 24 byte Tag; `define Tag 23:16 bit [15:0] Addr; } Entry; `define Addr 15:0 iTag = Entry.Tag; iTag = Entry[`Tag]; iAddr = Entry.Addr; iAddr = Entry[`Addr]; iValid = Entry.Valid iValid = Entry[`Valid] 32 0 unpacked 2 Valid packedpacked struct struct may may struct 1 Tag containcontain other other packed packed 0 Addr structs or packed arrays structs or packed arrays 24 23 1615 0 Valid Tag Addr packed struct 37 DAC2003 Accellera SystemVerilog Workshop SV 3.1 Literals • SV literal values are extensions of those for Verilog reg [31:0] a,b; reg [15:0] c,d; This works ... like in Verilog a = 32'hf0ab; c = 16'hFFFF Adds the ability to a = '0; This fills the packed specify unsized literal b = '1; array with the same c = 'x; bit value single bit values with d = 'z; a preceding ‘ logic [31:0] a; These are ... a = 32'hffffffff; equivalent a = '1; 38 DAC2003 Accellera SystemVerilog Workshop SV 3.1 Literals This works like in Verilog Adds time literals #10 a <= 1; #5ns b <= !b; #1ps $display("%b", b); You can also specify delays with explicit units Similar to C, but with Adds Array literals the replication operator int n[1:2][1:3] = {{0,1,2},{3{4}}} ({{}}) allowed 39 DAC2003 Accellera SystemVerilog Workshop Enumerated Data Types enum {red, yellow, green} light1, light2; anonymous int type enum {bronze=3, silver, gold} medal; silver=4, gold=5 enum {a=0, b=7, c, d=8} alphabet; Syntax error enum {bronze=4’h3, silver, gold} medal; silver=4’h4, gold=4’h5 typedef enum {red, green, blue, yellow, white, black} Colors; Colors col; integer a, b; a=2*3=6 a = blue * 3; col=3 col = yellow; b=3+1=4 b = col + green; 40 DAC2003 Accellera SystemVerilog Workshop Type Casting int'(2.0 * 3.0) A data type can be changed shortint' {8’hFA, 8’hCE} by using a cast (‘) operation 17 ' (x – 2) • Any aggregate bit-level object can be reshaped ObjectsObjects must must have have – Packed ⇔ Unpacked, Array ⇔ Structure identicidenticalal bit bit size size typedef struct { bit [7:0] f1; f1 A bit [7:0] f2; bit [7:0] f3[0:5]; f2 } Unpacked_s; typedef struct packed { f30 f31 f32 f33 f34 f35 bit [15:0][0:2] f1; bit [15:0] f2; } Packed_s; B Unpacked_s A; Packed_s B; f10 f11 f12 f2 … A = Unpacked_s’(B); B = Packed_s’(A); 41 DAC2003 Accellera SystemVerilog Workshop Constants • Use like defines or parameters • Global constant (const) is resolved at the END of elaboration. • Local constant (localparam) is resolved at the BEGINNING of elaboration. – No order dependency problems when compiling • specparam is used for specify blocks const bit TRUE = 1; global constant const logic option = a.b.c; Can’t be overridden Can contain an expression module top; with any hierarchical path name with localparam int TRUE = -1; defparam localparam bit FALSE = 0; local constant initial $display(“TRUE=%d", TRUE); // -1 endmodule 42 DAC2003 Accellera SystemVerilog Workshop Parameters module top; logic clk; Override parameters by name clockgen #(.start_value(1'b1), .delay(50), .ctype(int)) c (clk); always @clk $display("t=%t clk=%b", $time, clk); initial begin repeat(10) @(posedge clk) ; $finish(0); Parameter used end endmodule before definition module clockgen (output ctype clk); parameter logic start_value=0; parameter type ctype=bit; parameter time delay=100; initial clk <= start_value; Parameters can have always #delay clk <= !clk; explicit type endmodule 43 DAC2003 Accellera SystemVerilog Workshop Variable Types • Static variables • Global variables – Allocated and initialized at – Defined outside of any module time 0 (i.e. in $root) – Exist for the entire – Accessible from any scope simulation – Must be static – Tasks and functions can be • Automatic variables global too – Enable recursive tasks and • Local variables functions – Accessible at the scope where – Reallocated and initialized they are defined and below each time entering a block – Default to static, can made – May not be used to trigger automatic an event – Accessible from outside the scope with a hierarchical pathname 44 DAC2003 Accellera SystemVerilog Workshop Scope and Lifetime top inst; data declared outside of modules is static int max = 10; and global int n; module top; int n; initial begin i is automatic and automatic int i; local to that block n = 1; data declared inside for (i=2; i<=max; i++) of a module is static n *= i; and available to all end tasks and functions in initial begin : myblock that module n = 1; for (int i=2; i<=max; i++) n *= i; global n $root.n = n; local n end endmodule 45 DAC2003 Accellera SystemVerilog Workshop Task and Function Arguments • Default Arguments – Definition: task foo(int j=5, int k=8); – Usage: foo(); foo(5); foo(,8); foo(5,8); • Pass by Name foo(.k(22)); // j uses default • Pass by Reference Optional “read-only” qualifier – Declaration: task tk([const] ref int[1000:1] ar); – Usage: tk(my_array); // note: no ‘&’ Simplifies Task/Function Usage 46 DAC2003 Accellera SystemVerilog Workshop Familiar C Features In SystemVerilog do continue starts begin next loop iteration works with: if ( (n%3) == 0 ) continue; for while if (foo == 22) break; forever end break exits repeat while (foo != 0); the loop do while … Blocking Assignments Extra parentheses if ( (a=b) ) … required to distinguish as expressions while ((a = b || c)) from if(a==b) Auto increment/ x++; decrement operators if (--c > 17) c=0; Assignment Operators a += 3; Semantically equivalent s &= mask; to blocking assignment Wildcard Comparisons f <<= 3; X and Z values act as a =?= b wildcards a !?= b 47 DAC2003 Accellera SystemVerilog Workshop SystemVerilog Interfaces Design On A White Board HDL Design Complex signals SystemVerilog Bus protocol repeated in blocks Interface Bus Hard to add signal through hierarchy Design Signal 1 Signal 2 Read() Communication encapsulated in interface Write() - Reduces errors, easier to modify Bus Bus Assert - Significant code