Logic Families Characterizing Digital ICs Digital ICs characterized several ways Circuit Complexity Gives measure of number of transistors or gates Within single package Four general categories SSI - Small Scale IC < 12 gates or so MSI - Medium Scale IC < 100 gates or so LSI - Large Scale IC < 1000 gates or so VLSI - Small Scale IC > 1000 gates or so Main Characteristics Voltage Levels Input Output Low High Supply Noise Margins Based upon voltage levels Propagation delay Low to High High to Low Setup and hold times Storage devices Fan In and Fan Out Based upon Input sink capability Output drive capability Power dissipation Circuit Technologies and Topologies Describes Process used to implement devices Input and output structure of the device Four general categories - 1 of 20 - TTL Transistor Transistor Logic Bipolar transistors on input and output NPN, PNP, diodes Input Diode Transistor BE junction Output Typically two transistors Configured in totem pole arrangement ECL Emitter Coupled Logic Bipolar Input Configured in non-saturating differential pair Output Emitter follower type of configuration -V Logic done in emitter circuitry rather than collector High speed MOS Metal Oxide Semiconductor Field Effect Transistors MOS transistors on input and output N MOS N Channel transistors Operating in enhancement mode Less common as single technology in new designs Input Gate Output Typically two transistors Configured in totem pole arrangement Upper configured as depletion mode load P MOS P Channel transistors Operating in enhancement mode Rarely used alone in new designs Input Gate - 2 of 20 - Output Typically two transistors Configured in totem pole arrangement Upper configured as depletion mode load C MOS N - P Channel transistor pairs Operating in enhancement mode Input Gate Output Two transistors Configured in totem pole arrangement Upper P channel Lower N channel BICMOS Both CMOS and Bipolar transistors Bipolar mainly on output Used for speed Works well for combining Analog and digital circuitry on same substrate Circuit Topology Output Stages Three different types Normal Active drive logic both high and low states TTL CMOS Open Collector / Drain Active drive logic low state passive pull up to high state Used in applications where - 3 of 20 - Wire OR bus Sink large amounts of current Lamp LED Relay TTL CMOS Tristate Two states Behave as Normal Active drive logic low and high states Third state Both devices turned OFF Output floats Tristate mode Selected by control line Typically Low enables drive High disables Used in applications where Bus configurations Bus usually pulled high passively Size of pullup determined by Logic family CMOS - higher value TTL - lower value Desired bus speed Input Stages TTL Two forms Multiple emitter Diode Multiple Emitter - 4 of 20 - Input transistor behaves in interesting way Q1 When any input low Q1 Q2 Emitters act as emitters Operates in forward direction Turns on to ground Q2 Turns off When all inputs high Q1 Emitters act as collectors Operates in reverse direction Supplies current/voltage to Q2 Q2 Turns on Diode Input Diode inputs work like traditional DTL Both inputs High Q2 turns on Any input low Q2 turns off - 5 of 20 - CMOS Input structure 1 N channel and 1 P channel For each input Circuit above shows "AND" configuration Reverse configuration for "OR" function Logic Families Continually changing as technologies improve Common Bipolar LS Low Power Schottky AS Advanced Schottky ALS Advanced Low Power Schottky 54 / 74 Military / Commercial CMOS HC / HCT High Speed CMOS TTL Compatible 4000 Typical numbering A Look at the Real World Logic gates and circuits always work perfectly on paper Let’s now look at some of the things we encounter When working with real parts Voltage Levels TTL or CMOS we have supply voltage of +5 VDC ECL will use a negative supply -5.2 VDC Denoted Vcc - Bipolar Vdd - MOS Vee - ECL - 6 of 20 - Logic Levels On paper we deal with logical 0 or logical 1 In physical parts Represented by different voltage levels Most typically Logical 0 - 0 volts Logical 1 - +5 volts Newer logics Logical 0 - 0 volts Logical 1 - +1.5 or 3.0 volts We refer to Logic 0 as low Logic 1 as high Problem When dealing with real parts Logic high never exactly 5.0 v Logic low never exactly 0.0v If logic High gets too low Interpreted as logic 0 Low gets too high Interpreted as logic 1 Max and Min Values For TTL family we specify Min logic high voltage 2.0 volts Lower either interpret as logic 0 or Don’t know This can be a problem Max logic low voltage 0.7 volts Higher either interpret as logic 1 or Don’t know This can be a problem Nominal Values We rarely work with parts at max voltages specify Typical Nominal values Must consider when doing worst case design Typical logic high voltage 3.5 volts Typical logic low voltage 0.2 volts - 7 of 20 - Noise immunity Difference between Min (Max) values and nominal values Gives noise immunity Consider if VOH from a gate is 3.5 v VIHmin is 2.0 v VOH - VIHmin = 1.5v What this says is we can have 1.5 v of low going noise spike Before it’s interpreted as a logic 0 Consider if VOL from a gate is 0.2 v VILmax is 0.7 v VOL - VILmin = 0.5v What this says is we can have 0.5 v of high going noise spike Before it’s interpreted as a logic 1 Observe Based upon typical values have 1.5 v of high noise immunity 0.5 v of low noise immunity TTL CMOS Noise Margins Fan 4.5 VOHtyp 5.0 5.0 In Noise Margins and 3.5 VOHtyp Fan Out 2.7 VOHmin 2.4 VOHmin 2.0 VIHmin 2.0 VIHmin 0.5 VOLmax 0.7 VILmax 0.4 VOLmax 0.8 VILmax 0 0 0.2 VOLtyp 0.0 VOLtyp Amount of current a device can source or sink - 8 of 20 - Limited Such limits determine how many other devices Can be driven Fan Out Measure of output drive capability Specifies how current device can Supply to other devices in logic high state Sink from other devices in logic low state Fan In Measure of device input requirements Specifies how current device Supplies to other devices in logic low state Sink from other devices in logic high state Analyzing Let’s specify drive capability for typical gate IOL 8 mA @ VOL = 0.5VDC IOH -400 µA @ VOH = 3.4 VDC IIL -400 µA @ VIL = 0.4VDC IIH 20 µA @ VIH = 2.7 VDC For such analysis Ohm’s law must hold If high drive required to supply additional current Voltage must drop If low drive required to sink additional current Voltage must increase For this device Logic 0 State When output at logic 0 Can sink 8mA When input at logic 0 Sources -400 µA Thus Can sink current from 20 devices Logic 1 State When output at logic 1 Can supply -400 µA When input at logic 1 Requires 20 µA Thus Can source current to 20 devices Thus fan out for device is 20 - 9 of 20 - Can connect up to 20 devices Can support up to 20 unit loads Observe on input Device typically requires 20 µA for logic 1 -400 µA for logic 0 Call this a unit load State fan in is 1 unit load If values double State fan in is 2 unit loads Increasing Drive Capability Are occasions when require more drive capability Handle several ways Buffers / Drivers Such devices designed for purpose of driving Often open collector configuration High sink - intended to drive low Such devices tend to be slower Parallel Devices Another common technique Connect several standard devices in parallel Assumption If one device will sink/source x mA Then n devices will sink/source nx mA Is belief valid? Let's consider following circuit configuration A B Let's put a step input into the circuit input device A device B tpd1 tpd2 - 10 of 20 - From the diagram we see Propagation delay through two devices is different If device A faster that device B When A tries to go high B still (partially) off Tries to hold signal low Two devices fighting Conflict in two logic states can potentially damage part May not occur immediately More often will appear as premature failure Problem In any random sample of parts Have no guarantee of device speed Hand selecting parts not solution Possible solution If paralleled devices in same package Thus on same small portion of die Prop delays much closer than on arbitrary parts Still real world parts and will be different Unused Inputs Gate inputs should always be defined Never let them float Problem with TTL Larger problem with CMOS Floating input Has parasitic capacitors connected To ground Surrounding circuitry Such capacitors Charge up to threshold voltage of device Cause device to change state Uncontrolled or unknown ways Defining Inputs Direct connection to VDD, VCC, VSS permitted Both CMOS and LS TTL Direct connection to VDD, VCC, prohibited Standard TTL - 11 of 20 - Must be done through pullup Preferred method Connect to VCC or VDD Through pullup resistor CMOS 10 - 100K Since input current negligible size insignificant LS TTL Remember IIH and IIL Must calculate current to ensure voltage drop not too large With such scheme Can connect to ground for test Only works if several inputs not connected to same pullup Unused Gates Similarly must define inputs to unused devices Goal to place device in low power state Devices left undefined Can enter state in which all internal devices conducting to ground Basic Logic Devices Classified according to function Will include SSI - Small Scale Integrated circuits MSI - Medium Scale Integrated Circuits Combinational Logic SSI Devices Basic Logic Gates Comprises basic logic gates AND / NAND OR / NOR Invertor Exclusive OR / NOR Bus Drivers and Transceivers Serve two main purposes Provide high current drive Perform multiplexing function Output configuration Open collector Tristate Inverting / Noninverting - 12 of 20 - If tristate