Nanoelectronics Miniaturisation in Electronics: Scaling Challenges With slides from: Prog. Aidan Quinn (Nanotechnology Group, Tyndall) Prof. Jean -Pierre Colinge (formerly head of MNE Centre, Ty ndall) Dr Lida Ansari (Electronics Theory Group, Tyndall) Dr Vladimir Djara (ex - Silicon Research Group & CFF, Tyndall) Dr Barry O’Sullivan (ex – SRG, Tyndall) 1 CMOS Scaling • Microprocessor performance: 2011 vs 1971 • Semiconductor Industry Overview (ITRS) • Internat iona l Tec hno logy Roa dmap for Sem icon ductors (2011 Edit ion ) http://www.itrs.net/Links/2011ITRS/Home2011.htm (pub. Feb. 2012) Executive Summary, Litho gra ph y, Emer gin g Research Devices , Emer gin g Research Materials sections • Moore’s Law ((g)Scaling). • Silicon Process Scaling Challenges. – Lithography – Transistor – Gate Dielectric – Interconnects – Power Dissipation 2 First Transistor (1947) Transistor “Transforming resistor” At Bell laboratories in 1947 3 Discrete Electronic Circuits Electronic elements wired or soldered together onto circuit boards. Large space Expensive 4 Early Integrated Circuits Robret Noyce: First Nobel Prize, 2000 monolitic integrated circuit Jack Kilby: Inventor of the first integrated circuit – at Texas Instruments in 1959 5 Only 4 transistors! Intel Quad‐Core (2,000,000,000 transistors), 2008 One centimetre The first transistor 1947 High speed of microprocessors Higher numbers of Low cost transistors on a chip 4000 transistors of 22 nm Low power consumption gate length fit across the width of a human hair! 6 Past & Present: Silicon Microppgrocessors at the 20 nm length scale (a human hair is about 50,000 nm in diameter) 1971: 2011: Intel 4004. First commercially 8 x 128 Gbit die available microprocessor: 5 kilobits of data (~ a text message) 1 Tera bit o f da ta (~ 50, 000 p ho tos ~600 kHz clock frequency from a 3 Megapixel camera) ~3 GHz clock freqqyuency 7 Source: Intel (6/12/11) Near Future: 3D Nanotransistors L g Drain Gate W Source Tsi 200 nm A-A’ BOX Nanoscale Tri-gate Transistors Fabricated at Tyndall using Electron-Beam Lithography (Prof. J.P. Colinge). Electron microscopy images from Intel Ireland (2014). 8 Classical CMOS Field-effect Transistor Gate Oxide gate source SiO2 VG drain VS VD n+ n+ L p-type silicon • First MOSFET IC’s produced in 1963 •SiO2 was the gate dielectric of choice until 2008 • Channel / ggpate oxide interface critical to device performance and long-term stability • L is the channel (gate) length 9 Source: Barry O’Sullivan Introduction What is a MOSFET ? MOSFET: Metal Oxide Semiconductor Field Effect Transistor CMOS Inverter Vin Vout 45-nm node (INTEL) 10 10 MOSFETs are Everywhere MOSFET: Metal Oxide Semiconductor Field Effect Transistor Data centres 11 11 Transistor is a switch! Julius Edgar Lilienfeld , 1925 Dawon Kahng, 1959 Gate Source Drain 12 MOS Gate Stack → Ideal Case M SourceO Drain S 13 13 Introduction MOS Gate Stack → Ideal Case M O S CdtiBdConduction Band Fermi Level Source DiDrain Valence Band Energy Distance 14 14 Introduction MOS Gate Stack → Ideal Case V < VT M SourceO Drain S OFF state 15 15 Introduction MOS Gate Stack → Ideal Case V < VT M SourceO Drain S OFF state 16 16 Introduction MOS Gate Stack → Ideal Case V < VT M SourceO Drain S OFF state 17 17 Introduction MOS Gate Stack → Ideal Case V < VT M SourceO Drain S OFF state 18 18 Introduction MOS Gate Stack → Ideal Case V = VTh M SourceO Drain S Threshold Threshold 19 19 Introduction MOS Gate Stack → Ideal Case V > VTh Qinv = Cox . (V ‐ VTh) M SourceO Drain S ON state 20 20 Introduction MOS Gate Stack → Non‐ideal Case V > VTh Qinv + Qtrap = Cox . (V + ΔV ‐VTh) M SourceO Drain S Qtrap 21 21 Introduction MOS Gate Stack → Non‐ideal Case V > VT Qinv + Qtrap = Cox . (V + ΔV ‐VT) M SourceO Drain S Qtrap 22 ΔV yields degradation of SS 22 Motivation Number of transistors in ICs had doubled every year from the invention of the IC in 1958 until 1965 and predicted that the trend would continue “for at least ten years” Gordon Moore Tradllditional scaling increasingly challenging new materials & novel devices Source ITRS 23 Moore’s Law: Number of transistors per unit area doubles everyyy 2 years Source: Intel (Oct. 2009) 24 Top-down MOS transistors 25 Typical feature size for a given ITRS node/year Definitions of typical feature size for a given ITRS node/year NB Some features are even smaller, e. g. gate length Source ITRS 2011 26 Gate Pitch (Intel) Source: Intel (Oct. 2009) 27 Static Random Access Memory (SRAM) Cell Size Source: Intel (Oct. 2009) 28 Scaling Nodes (term gradually being replaced by “Year of First Production” due to differences in scaling rates) Why: 500 nm, 350 nm, 250 nm, 180 nm, 130 nm, 90 nm, 65 nm, 45 nm, 32 nm ? Ln Ln+1 Ln Area of 1 transistor: An+1 = An / 2 An+2 = An+1 / 2 A = L 2 2 = A / 4 n n = Ln+1 n 2 = Ln+2 2 2 2 2 Ln+1 = Ln /2 Ln+2 = Ln /4 Ln+1 = Ln /2 Ln+2 = Ln /2 2 1.4 1/2 0.7 29 Moore’s Law driven by scaling 1000 All leading-edge logic products: 0.5m 0.35m Technology Node nm) 0.25m (( = 2x transistor 0180.18m density of previous 0.13m node 0.2m 90nm size size 65nm 100 130nm ee 45nm Transistor 70nm 30nm 50nm atur Physical Gate ee 30nm F Length 20nm 15nm 10 1990 1995 2000 2005 2010 Year Source ITRS 2001 30 Moore’s Law driven by scaling All leading-edge logic products: 10000 nm) (( 1000 y node y 100 gg 10 echnolo TT 1 1970 1980 1990 2000 2010 2020 2030 year 31 Source: ITRS 2015 Top-down MOS transistors 32 J. Maiz, Intel, 2007 Top-down MOS transistors 14 nm 2014 Intel, 2011 33 Top-down MOS transistors Intel, 2010 34 Predicted Feature Sizes in CMOS NB: Sizes are predicted, manufacturing solutions have not been identified/optimised for all nodes. Source ITRS ’11, Executive Summary 35 Predicted Feature Sizes in CMOS NB: Sizes are predicted, manufacturing solutions have not been identified/optimised for all nodes. 36 Source ITRS ’11, Executive Summary Lithography Challenges (Near Term) Source: ITRS ’11, Lithography Section 37 http://www.itrs2.net/itrs-reports.html Lithography Challenges (Near Term) YEAR OF PRODUCTION 2015 2017 2019 2021 2024 2027 2030 Logic device technology naming P70M56 P48M36 P42M24 P32M20 P24M12G1 P24M12G2 P24M12G3 Logic industry "Node Range" Labeling (nm) "16/14" "11/10" "8/7" "6/5" "4/3" "3/2.5" "2/1.5" finFET finFET finFET finFET Logic device structure options LGAA VGAA, M3D VGAA, M3D VGAA, M3D FDSOI FDSOI LGAA VGAA DRAM DRAM minimum ½ pitch (nm) 24 22 18.0 15.0 12.0 9.2 7.7 CD control (3 sigma) (nm) [B] 242.4 222.2 181.8 151.5 121.2 090.9 080.8 Mininum contact/via after etch (nm) [H] 24 22 18 15 12.0 9.2 7.7 Minimum contact/via pitch(nm)[H] 72 66 54 45 36 28 23 Overlay (3 sigma) (nm) [A] 4.8 4.4 3.6 3.0 2.4 1.8 1.5 Flash 2D Flash ½ pitch (nm) (un‐contacted poly) 15 14 12 12 12 12 12 Flash 3D Layer half‐pitch targets (nm) 80.0 80.0 80.0 80.0 80.0 80.0 80.0 3D NAND minimum metal pitch(nm) 20.0 20.0 20.0 20.0 20.0 20.0 20.0 CD control (3 sigma) (nm) [B] 1.5 1.4 1.2 1.2 1.2 1.2 1.2 Overlay (3 sigma) (nm) [A] 5.1 4.7 3.9 3.9 3.9 3.9 3.9 MPU / Logic MPU/ASIC Min imum MlMetal ½ pihitch ()(nm) 26 18 12 10 606.0 606.0 606.0 MPU/ASIC finFET fin minimum 1/2 pitch (nm) 21 18 12 Lateral Gate All Around (LGAA) 1/2 pitch 12 10 Vertical Gate All Around (VGAA) 1/2 pitch 10 6.0 6.0 6.0 Contacted poly half pitch (nm) 35 24 21 16 Physical Gate Length for HP Logic (nm) 24 18 14 10 Vertical Gate All Around (VGAA) pitch (nm) 20 12 12 12 Gate CD control (3 sigma) (nm) [B] 2.4 1.8 1.4 1.0 Metal CD control (3 sigma) (nm) [B] 2.6 1.8 1.2 1.0 0.6 0.6 0.6 Fin CD control (3 sigma) (nm) [B] 0.40 0.30 0.30 FIN or LGAA LER [C] 0.40 0.30 0.30 Gate LER [C] 2.4 1.8 1.4 1.0 Metal LWR [C] 3.9 2.7 1.8 1.5 0.9 0.9 0.9 Source: ITRS 2.0, 2015, Lithography Section, 38 http://www.itrs2.net/itrs-reports.html Market estimations Players: Intel, Samsung, TSMC,..... Changggypgpes in strategy ahead: optimizing performance at each node prior to lauch next one 39 http://spectrum.ieee.org/semiconductors/devices/intel-finds-moores-laws-next-step-at-10-nanometers Lithography (Optical) 1.A laser beam writes the circuit pattern for a microchippy on a layer of light-sensitive ppyolymer (photoresist) that rests atop a layer of chromium on a transparent substrate (e.g. quartz). The sections of polymer struck by the beam can be selectively removed (developed). 2.The exposed sections of chromium are removed by etching, and the rest of the polymer is then dissolved. The result is a mask—the equivalent of a photographic negative. 3.When a beam of monochromatic ultraviolet light is directed at the mask, the light passes through the gaps in the chromium.