Scaling of the conventional MOSFET devices Chapter 4 4 Scaling of the Conventional MOSFET Devices The previous section outlined the integrated process and device simulation methodology that has been followed throughout this research in the modelling and analysis of real 35 nm MOSFETs. This chapter deals with the implementation of this methodology and the scaling of the 35 nm transistor to its ultimate limits. The first section presents the general concept of the calibration process and the practical steps which have to be followed to achieve both a good understanding of the device structure and good agreement with the measured device characteristics. The structure and the electrical properties of the well- calibrated 35nm CMOS device which is used as a starting point of the scaling study is presented in the second section. Section three describes work on the scaling of the MOSFETs based on predictions for the future four generations of technology nodes by the ITRS. Additionally, the device structures and the electrical and physical properties of the scaled devices have been analysed. Further discussions and conclusions are presented in the last section of this chapter 4.1 Calibration strategy and its role in device simulation In general, calibration is a process in which the parameters used in the simulation are tuned to deliver repeatable results in all simulation conditions within the space of reasonable input parameters [4:1] [4:2]. In device simulation, the calibration process helps to validate our physical models by comparing simulated results with real device characteristics. Hence, the calibration process from the device simulation point of view can be defined as a methodical approach which leads to the synchronisation between the simulation results and valid experimental data. 81 Scaling of the conventional MOSFET devices Chapter 4 This matching process is very important in order to validate the simulation results, to build confidence in the models and to allow reliable analysis based on these results. Therefore, the aim of calibration is to tune the model parameters in order to produce simulation results which are as close as possible to the experimental data. At the same time it is very important to make sure that all the input parameters that have been used and tuned in the calibration process are physically meaningful, leading to trustworthy simulation results. Therefore, a carefully and systematically executed calibration is the stepping-stone to a successful device simulation and modelling strategy. This means that calibration plays an important role in the device simulation practice. One of the advantages of device calibrations is the possibility of implementing various physical models with different degrees of complexity. Unfortunately, all the models typically available in TCAD tools are not expected to give identical simulation results for the same devices structure. At the same time, some of them are not sufficiently robust to be applied in the simulation of nano-scale MOSFETs. Hence, to stick to a particular model throughout the simulation practice independent of the device size or the bias conditions is highly unwise. It is always important to evaluate the available models and it is essential to perform a test in order to select an optimum simulation model both in terms of accuracy and computational efficiency Through device calibration it is possible to achieve both accurate and physically meaningful simulation results. This in turn can empower the technologists and the device engineers to develop the optimum device structure and the corresponding fabrication steps that can deliver the desired electrical parameters. It is important to note that the default parameters in the relevant TCAD tools are not always optimal for particular types of devices and as a rule do not deliver good agreement with the experimental data straight away unless calibration has been performed systematically and thoroughly. In order to achieve a reliable and effective simulation based device scaling, a systematic calibration methodology has been developed and applied in the course of this work, which is outlined in the next subsection. 82 Scaling of the conventional MOSFET devices Chapter 4 4.1.1 Systematic calibration It is a good strategy in the calibration process to start from the simplest physical model and work up the ladder to the more complex and comprehensive models. Although simple models are inherently attractive because of a small number of input parameters and computational efficiency, in most cases they can only provide basic qualitative and semi- quantitative results. The introduction of more complex models is usually needed to improve the quantitative agreement. Therefore a hierarchical strategy can be applied to the device calibration process without compromising its final outcome. The calibration starts with the gathering of all the important available information about the structure and the characteristics of the calibrated device. The careful analysis of the device structure and characteristics provide indications about the appropriate models. The choice of appropriate physical models prompts the beginning of the calibration processes. The overall calibration strategy is illustrated in figure 4:1. Detail of the important calibration steps with the corresponding models of choices, will be discussed in the next three sections. The systematic calibration methodology illustrated in figure 4:1 can be summarised in to the following 6 step algorithm. 1 Start from the simple operation conditions which can be reproduce by simple models, for example, low field part of the I-V characteristics which can be described with constant mobility models. 2 Adjust the channel doping profile and the halo-doping concentration at constant mobility to capture the device electrostatics by matching the threshold voltage VT and the subthreshold slope-S. Test the effect of quantum corrections on VT, 3 At low drain voltage increase, the complexity of the mobility model to capture the perpendicular electric field and concentration dependence of the mobility 4 At high drain voltage refine the doping profile to capture the drain induced barrier lowering (DIBL) effects and introduce the lateral field dependence of the mobility to capture the velocity saturation effect 5 Examine the impact of non-equilibrium transport by switching-on hydrodynamic tools 83 Scaling of the conventional MOSFET devices Chapter 4 6 Compare the simulation result with the experimental data and analyse the developing variation between the two. If errors are outside of margin of tolerance, go back to the starting point or to a relevant calibration step for the necessary input parameter adjustments. Id Vg I D Vg I d V d Figure 4:1 Flow chart that illustrates the systematic calibration methodology 84 Scaling of the conventional MOSFET devices Chapter 4 4.2 The structure of the real 35 nm gate length MOSFET This subsection introduces the structure and the critical design parameters extracted from the 35 nm gate length MOSFET fabricated by Toshiba which has been used as a reliable experimental source for calibration of the simulator tools applied in this project. The quality of the experimental data is crucial for the successful calibration. Some of the most important parameters for the above device presented in table 4.1 below have been carefully extracted from published data [4.3] and from private communication with the authors. Figure 4:2 Transmission electron micrograph (TEM) photograph of the 35 nm n-channel device from which all data and process information have been obtained for this work. Reference [4.3] In respect of the channel profile engineering of the 35 nm transistor, the authors of [4.3] have investigated three different cases of indium implantation in order to establish the optimum doping profile for their n-channel MOSFET. The first case introduces a high dose of indium implantation with no halo doping. The second case introduces intermediate channel dose and intermediate halo doping concentration. The final case introduces low dose of channel implant and high dose of BF 2 halo implantation. The implantation 85 Scaling of the conventional MOSFET devices Chapter 4 conditions in the above three cases have been simulated based on the information provided by the authors of [4.3]. A significant effort has been invested in reproducing a realistic device structure using proper process simulation steps. Figure 4:2 shows the transmission electron microscopy cross-section view of the Toshiba 35 nm physical gate length MOSFET, from which the essential structural data were extracted for the calibration process in this work. The extracted structural data are summarised in table 4:1 for both n- and p-channel devices. The corresponding electrical parameters are summarised in table 4:2. Although the 35 nm gate length transistor is not specified explicitly in the ITRS, its electrical and structural parameters are very close to that of the 37 nm physical gate length MOSFET which is required for late stage of the 90 nm technology node. Junction depth Oxide thickness S/D doping Channel doping Halo doping 2 2 2 xj [nm] tox [nm] [ion/cm ] [ion/cm ] [ion/cm ] Unpublished n-MOSFET 20 1-1.2 1.0 - 5.0 ×10 13 < 3.0 ×10 13 data * Unpublished Unpublished p-MOSFET 33 1-1.2 1.0 – 4.0 ×10 13 data * data * Table 4:1 Important device dimensions and doping information of the 35 nm gate length p-type MOSFET. Threshold Subthreshold Subthreshold Saturated drive Supply voltage voltage slope