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Ann Aibor, MI 48106 T h e VAMPIRE C h ip : A V e c t o r - q u a n t iz in g A sso c ia t iv e M em o r y P r o c e sso r Implementing R e a l - t im e E n c o d in g dissertation Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in the Graduate School of The Ohio State University By Kenneth Christopher Adkins, B.S., M.S. $ $ $ $ $ The Ohio State University 1993 Dissertation Committee: Approved by Steven B. Bibyk Steven Bibyk Adviser / y Stanley Ahalt Department of Electrical Mohammed Ismail Engineering © Copyright by Kenneth Christopher Adkins 1993 To Cirnnny anti Gnmtlntl ii A cknowledgements I express sincere appreciation to Dr. Steven Bihyk for his continued support and guidance over the past five years. Thanks go to the other members of my advisory committee, Dr. Stanley C. Alialt and Dr. Mohammed Ismail, for their comments, time, and flexibility. Gratitude is expressed to Mary Jo Shnlkhauscr and Joe Harrold at NASA Lewis for support via grant NAG3-1802 and funding of the VAMPIRE chip. The assistance of Changku Hwang for running SPICE simulations and of Jim Fowler for providing the satisfaction of Hccing the chip run in a real-time application is gratefully acknowledged. I thank my parents and family for their ever-present support and encouragement. To Thcrese Patnesky and our stray cat Sadie, I offer sincere thanks for enduring the fortunes and misfortunes that have characterized the push to complete this research. Vour devotion, encouragement, and cooking will not be forgotten. V i t a December 28, 19GC . ..................................Horn * Cincinnati, Ohio June, 1988 ................................................... B.S. in Electrical Engineering, The Ohio Slate University, Columbus, Ohio 1988-1991 ..................................................... Teaching and Research Assistant, Department of Electrical Engineering, The Ohio Slate University March, 1991 ................................................. M.S. in Electrical Engineering, The Ohio State University, Columbus, Ohio 1991-1992 ..................................................... Teaching and Research Assistant, Department of Electrical Engineering, The Ohio State University P ublications (Bibliographic entries of previously published material) F i e l d s O f S t u d y Major Field: Electrical Engineering Studies in VLSI Circuit Design, Communication Systems T a b l e o f C o n t e n t s DEDICATION ................ ACKNOWLEDGEMENTS VITA ................................. LIST OF FIGURES . LIST OF TABLES ...................................................................................................... xiii LIST OF PLATES ...................................................................................................... xiv CHAPTER PAGE I Introduction ......................................................................... 1 1.1 Overview ................................................................................................... 1 1.2 Nature of the Problem ............................................................................ 1 1.3 Problem Statement ............................................................................... 4 1.4 Dissertation Structure ............................................................................ 5 II Background ......................................................................................................... 6 2.1 M o tiv a tio n ............................................................................................... 6 2.2 Previous Work ............... 10 2.2.1 Associative M em o ries ................................................................ 10 2.2.2 Vector Quantization ............................................... 15 2.2.3 Hardware Implementations of VQ ............................................. 22 2.3 S u m m a ry .................................................................................................. 24 III Design Considerations ...........................................'........................ 26 3.1 Analog vs. D ig ita l ................................................................................... 26 3.2 Distortion Calculation ............................................................................ 28 3.3 Absolute Value ......................................................................................... 35 3.4 Parallel vs. S erial...................................................................................... 38 3.5 Carry Propagation ................................................................................... 42 3.6 Winner Selection .............................................................................. 44 3.7 VQ Codcbook Design .................................................. 48 3.8 Summary .................................................................................................. 49 IV VAMPIRE Architecture .................................................................................... 51 4.1 Structural O verview ............................................................................... 51 4.2 Computation Cell ................................................................................... 55 4.2.1 Codeword S to ra g e ........................................................................ 56 4.2.2 “Grcatcr-Than” C irc u it ............................................................... 59 4.2.3 Absolute Difference V alu e ........................................................... 62 4.2.4 Component Sum s ........................................................................... 64 4.2.5 Global Compare Circuit ............................................................... 66 4.3 Overflow C e ll ............................................................................................ 69 4.4 Right-End C e ll .............................................. 72 4.5 Priority Encoder ...................................................................................... 72 4.6 Intcr-Chip Circuitry ............................................................................... 75 4.7 Address Decoder ...................................................................................... 80 4.8 Pad FVame ............................................................................................... 80 4.9 Reset .................................................... 81 V Implementations ................................................................................................. 82 5.1 Computation Cell ................................................................................... 83 5.2 Tiny Chip .................................................................................................. 85 5.3 fiill-Scalc Chip ......................................................................................... 87 VI Chip A nalysis .................................................................................... 89 6.1 Equipment and Procedure ...................................................................... 89 6.1.1 Data Acquisition and Control Adapter ..................................... 90 6.1.2 Evaluation Board ........................................................................... 92 vi 6.1.3 Testing Procedure and Sample O p e ra tio n .............................. 96 6.2 Experimental Results ............................................................................ 101 6.2.1 Functional/Steady-Statc T esting .............................................. 101 6.2.2 High-Speed Testing ........................................................................ 102 6.2.3 Baseline Performance ................................................................. 106 6.2.4 Initial