Cleveland State University EngagedScholarship@CSU Electrical Engineering & Computer Science Electrical Engineering & Computer Science Faculty Publications Department 10-2005 Dynamic Voltage Scaling Techniques for Power Efficient Video Decoding Ben Lee Oregon State University, [email protected] FErikoollow Nur thisvitadhi and additional works at: https://engagedscholarship.csuohio.edu/enece_facpub Carnegie Mellon University, [email protected] Part of the Computer and Systems Architecture Commons, and the Electrical and Computer EngineeringReshma Dixit Commons Oregon State University, [email protected] How does access to this work benefit ou?y Let us know! PublisherChansu Yu 's Statement NOClevTICE:eland thisState is Univ theersity author, [email protected]’s version of a work that was accepted for publication in Journal of MyungchulSystems Ar chitecturKim e. Changes resulting from the publishing process, such as peer review, Informationediting, corr andections, Communications structural formatting, University, [email protected] and other quality control mechanisms may not be reflected in this document. Changes may have been made to this work since it was submitted for publication. A definitive version was subsequently published in Journal of Systems Architecture, 51, 10-11, (10-01-2005); 10.1016/j.sysarc.2005.01.002 Original Citation Lee, B., Nurvitadhi, E., Dixit, R., Yu, C., , & Kim, M. (2005). Dynamic voltage scaling techniques for power efficient video decoding. Journal of Systems Architecture, 51(10-11), 633-652. doi:10.1016/ j.sysarc.2005.01.002 Repository Citation Lee, Ben; Nurvitadhi, Eriko; Dixit, Reshma; Yu, Chansu; and Kim, Myungchul, "Dynamic Voltage Scaling Techniques for Power Efficient Video Decoding" (2005). Electrical Engineering & Computer Science Faculty Publications. 66. https://engagedscholarship.csuohio.edu/enece_facpub/66 This Article is brought to you for free and open access by the Electrical Engineering & Computer Science Department at EngagedScholarship@CSU. It has been accepted for inclusion in Electrical Engineering & Computer Science Faculty Publications by an authorized administrator of EngagedScholarship@CSU. For more information, please contact [email protected]. Dynamic voltage scaling techniques for power efficient video decoding Ben Lee "", Erik o Nurvitadhi b, Reshma Dixit ", Chansu Yu " Myungchul Kim d • Scllool of EII'clriml Ellgilll'aillg tlllIl Compllier Sciellce. Oregoll Siall' Ullin:".,"/),. Corw!lis, OR 9733 /. Vllill'lf S[o/<'s b Dl'/lflrIllWIlI of Electriclil (//11/ CompUler £lIgillcerillg. ClifIlegie Mellol/ Ullit'l'rsif)'. Pilliiburgl!. P A 15213. Vlliteli SWII'S <; Deparlmcnl (J/ Elect'ira/lmd COIIJfI"ler £lIg;",:er;II8. Clerdmul SllIle U" hw.lil),. Cfen'/mul. OH 44115·2425, U"iled SII1lI','- d Schild 0/ EngineerillK. Ill/ormatioll alld CommrllliculiollS Ul1il ~ l'rsil)'. 103-6 ,I[""ii-Dong. YllSl'l"'g-GII, Dmj"oll 305-714, SOIllI! Korell • Corresponding author. Tel.: +1 541 737 3148: fax: +1 541 737 1300. E·mail (ltli/res,,'''.\': [email protected] (8 . Lee). cnurvi\[email protected] (E. Nurvi\adhi). [email protected] (R. Dixi!). c.yu91 @csuohio.cdu (C. Yu). mckim @;icu.ac.kr(M. Kim). 1. Introduction time span allowed. Thus, there is no power wasted by an idle processor waiting for a frame to be Power efficient design is one of the most impor­ played. In practice, decoding time estimation leads tant goals for mobile devices, such as laptops, to errors that result in frames being decoded either PDAs, handhelds, and mobile phones. As the pop­ before or after their playout time. When the ularity of multimedia applications for these porta­ decoding finishes early, the processor will be idle ble devices increases, reducing their power while it waits for the frame to be played, and some consumption will become increasingly important. power will be wasted. When decoding finishes late, Among multimedia applications, delivering video the frame will miss its playout time, and the per­ will become the most challenging and important ceptual quality of the video could be reduced. applications of future mobile devices. Video con­ Even if decoding time prediction is very accu­ ferencing and multimedia broadcasting are already rate, the maximum DVS performance can be becoming more common, especially in conjunction achieved only if the processor can scale to very with the third generation (3G) wireless network ini­ precise processor settings. Unfortunately, such a tiative [11]. However, video decoding is a computa­ processor design is impractical since there is cost tionally intensive, power ravenous process. In associated with having different processor supply addition, due to different frame types and varia­ voltages. Moreover, the granularity of voltage/fre­ tion between scenes, there is a great degree of var­ quency settings induces a tradeoff between power iance in processing requirements during execution. savings and deadline misses. For example, fine- For example, the variance in per-frame MPEG grain processor settings may even increase the decoding time for the movie Terminator 2 can be number of deadline misses when it is used with as much as a factor of three [1], and the number an inaccurate decoding time predictor. Coarse- of inverse discrete cosine transforms (IDCTs) per­ grain processor settings, on the other hand, lead formed for each frame varies between 0 and 2000 to overestimation by having voltage and frequency [7]. This high variability in video streams can be set a bit higher than required. This reduces dead­ exploited to reduce power consumption of the pro­ line misses in spite of prediction errors, but at cessor during video decoding. the cost of reduced power savings. Therefore, the Dynamic voltage scaling (DVS) has been shown impact of processor settings on video decoding to take advantage of the high variability in pro­ with DVS needs to be further investigated. cessing requirements by varying the processor's Based on the aforementioned discussion, this operating voltage and frequency during run-time paper provides a comparative study of the existing [4,10]. In particular, DVS is suitable for eliminat­ DVS techniques developed for low-power video ing idle times during low workload periods. Re­ decoding, such as Dynamic [33], GOP [21],and cently, researchers have attempted to apply DVS Direct [18,24], with respect to prediction accuracy to video decoding to reduce power [18,17,21, and the corresponding impact on performance. 19,24,33]. These studies present approaches that These approaches are designed to perform well predict the decoding times of incoming frames or even with a high-motion video by either using static group of pictures (GOPs), and reduce or increase prediction model or dynamically adapting its pre­ the processor setting based on this prediction. As diction model based on the decoding experience a result, idle processing time, which occurs when of the particular video clip being played. However, a specific frame decoding completes earlier than they also require video streams to be preprocessed its playout time, is minimized. In an ideal case, to obtain the necessary parameters for the the decoding times are estimated perfectly, and DVS algorithm, such as frame sizes, frame-size/ all the frames (or GOPs) are decoded at the exact decoding-time relationship, or both. To overcome this limitation, this paper also proposes an alterna­ ing low workload periods [4,9,10,12–24,33]. The tive method called frame-data computation aware advantage of DVS can be observed from the (FDCA) method. FDCA dynamically extracts useful power consumption characteristics of digital static frame characteristics while a frame is being decoded CMOS circuits [21] and the clock frequency equa­ and uses this information to estimate the decoding tion [24]: time. Extensive simulation study based on Simpl­ 2 P / Ceff V DDfCLK ð1Þ eScalar processor model [5], Wattch power tool [3] and Berkeley MPEG Player [2] has been con­ 1 V DD ducted to compare these DVS approaches. / s / 2 ð2Þ fCLK ðV DD - V TÞ Our focus is to investigate two important trade­ offs: The impact of decoding time predictions and where Ceff is the effective switching capacitance, granularity of processor settings on DVS perfor­ VDD is the supply voltage, fCLK is the clock fre­ mance in terms of power savings, playout accu­ quency, s is the circuit delay that bounds the upper racy, and characteristics of deadline misses. To limit of the clock frequency, and VT is the threshold the best of our knowledge, a comprehensive study voltage. Decreasing the power supply voltage would that provides such a comparison has not been per­ reduce power consumption significantly (Eq. (1)). formed, yet such information is critical to better However, it would lead to higher propagation de­ understand the notion of applying DVS for low- lay, and thus force a reduction in clock frequency power video decoding. For example, existing (Eq. (2)). While it is generally desirable to have methods only use a specific number of processor the frequency as high as possible for faster instruc­ settings and thus do not provide any guidelines tion execution, for some tasks where maximum on an appropriate granularity of processor settings execution speed is not required, the clock fre­ when designing DVS techniques for video decod­ quency and supply voltage can be reduced to save ing. Moreover, these studies quantified the DVS power. performance by only looking at power savings DVS takes advantage of this tradeoff between and the number of