9/9/14 CS 240, Fall 2014! WELLESLEY CS! CS 240, Fall 2014! WELLESLEY CS! Childhood dream? Pilot. First <me on a plane? This past summer. High school graduang class: 11 students. CS 240 Administrivia, Sept. 9 Drums + bass + guitar Swimming 3d prinng Shakespeare Society Water polo ¢ Everything is on the website: h>p://cs.wellesley.edu/~cs240/ Performed in bungra group in UK for an audience of 3500. § PS1 due Friday – how’s it going? a cappella USGS stream gauge expert § Readings – geng more relevant Figure skater Social network research § Google Group: ask ques<ons, link for anonymous feedback Volunteer coordinator Interviewing this fall Financial regulator ¢ Double-check your textbook: President of Hawai’i Club Computer Organizaon and Design: The Hardware/SoSware Interface Study abroad in Paris Study abroad in Budapest § NOT: Computer Architecture: A Quan<tave Approach, same authors. Cogni<ve science research If all else fails I’ll start a restaurant. § Abacus, not columns. Animal rescue Alternave break program ¢ MIPS card in front cover El Table Trekked Inca Trail ¢ Office Hours: Food poisoning on small island in the middle of nowhere in Indonesia. § Monday 4-6, Tuesday 9-10, 3-4, Thursday 4-5:30, Friday 11:30-12:30 Has a twin here ¢ Names Rowing Tennis Literature Society ¢ What you do Researching stereotype threat. Built a 40-foot boat and paddled it out on the Charles to watch fireworks. CS 240, Fall 2014! WELLESLEY CS! CS 240, Fall 2014! Program, ApplicaPon WELLESLEY CS! Today Programming Language ¢ MIPS instrucPon set (part 1) § Design principles § Arithme<c § Data transfer (memory access) Soware § Translaon from Java/C § Immediate operands You are here. InstrucPon Set Architecture ¢ Bitwise boolean algebra and logical operators § Java § MIPS § Bit vector manipulaons Devices (transistors, etc.) Hardware Solid-State Physics 1 9/9/14 CS 240, Fall 2014! WELLESLEY CS! CS 240, Fall 2014! WELLESLEY CS! InstrucPon Set Architecture General ISA Design Decisions ¢ The ISA defines: ¢ Registers § The system state (registers, memory, program counter, etc.) § How many registers are there? § The instruc<ons the CPU can execute § How wide are they? § The effect that each instruc<on has on the system state MIPS Memory! ¢ Memory MIPS private regs! (232-1)! . § How do you specify a memory locaon? PC! (A+24)! IR! (A+20)! MIPS user regs! (A+16)! ¢ $zero! 0 0 0 0 InstrucPons (A+12)! $v0! § What instruc<ons are available? What do they do? . (A+8)! $a0! (A+4)! § . How are they encoded? $t0! (A)! . $t1! (12)! $t2! . (8)! $s0! (4)! $s1! . (0)! 5 6 CS 240, Fall 2014! WELLESLEY CS! CS 240, Fall 2014! WELLESLEY CS! MIPS Three Basic Kinds of Instrucons ¢ Early 1980s: MIPS designed by John Hennessy et al. at Stanford. ¢ Perform arithmec or logic on register data. (Today, Friday) § a = b + c; x = y << z; i = j & k; ¢ 1984: MIPS Computer Systems. (Later MIPS Technologies) ¢ 1996: Nintendo 64 – most famous MIPS processor? ¢ ¢ 2013: Sold to Imaginaon Technologies. Transfer data between memory and register. (Today) § Load data from memory into register § $register = Memory[address] § Store data from register into memory ¢ Reduced InstrucPon Set Computer (RISC) § Memory[address] = $register § vs. Complex Instruc<on Set Computer (CISC) ¢ Control what instrucon is executed next. (Next week) § Uncondi<onal jumps § Condi<onal branches 7 8 2 9/9/14 CS 240, Fall 2014! WELLESLEY CS! CS 240, Fall 2014! WELLESLEY CS! One general instrucon format: Design principle: Smaller is faster. ¢ <instruc)on> <operand>, <operand>, <operand> ¢ How do we apply this principle in modern computer Category Instruc<on Example Meaning systems? add add $s1,$s2,$s3 $s1=$s2+$s3 Arithme<c subtract sub $s1,$s2,$s3 $s1=$s2-$s3 ¢ Design principle: Simplicity favors regularity. § Many instruc<ons naturally require three operands. § Variable numbers of operands necessitate more complex hardware. ¢ Why is there no negate instrucon? CRT memory IBM 701 defense calculator, 1952 CS 240, Fall 2014! WELLESLEY CS! CS 240, Fall 2014! WELLESLEY CS! Registers! Translate to MIPS int f(int a0, int a1, int a2, int a3) {! Name Register Number Usage ...! $zero 0 the constant value 0 int v0 = -(a0 + a1 - (a2 + a3));! $v0-$v1 2-3 values for results and expression evaluation ...! $a0-$a3 4-7 arguments }! $t0-$t7 8-15 temporaries How? $s0-$s7 16-23 saved $t8-$t9 24-25 more temporaries Two steps: $gp 28 global pointer $sp 29 stack pointer 1. Break into several simple Java/C statements, each corresponding to a single MIPS instruc<on. Introduce temporary local variables as needed. $fp 30 frame pointer $ra 31 return address 2. Translate to MIPS instruc<ons, represen<ng temporary local variables with registers in $t0-$t7. Local variable v0 is represented by register $v0, a0 by $a0, etc. We will talk about the usage column when we cover procedures. Design principles at work? 3 9/9/14 CS 240, Fall 2014! WELLESLEY CS! CS 240, Fall 2014! WELLESLEY CS! Data transfer instrucons Data transfer instrucons Java/C-ish descripon Category Instruc<on Example Meaning load word load word lw $s1,100($s2) $s1=Memory[$s2+100] lw $s0, 16($s1)! $s0 = M[$s1+16] Data transfer store word sw $s1, 100($s2) Memory[$s2+100]=$s1 des<naon register immediate offset address register Explored yesterday in lab... source register sw $s0, 16($s1)! M[$s1+16] = $s0 store word Oming the offset "DATA bus" by James Willamor - Own work. Licensed under Creave Commons Atribu<on-Share Alike 3.0 via Wikimedia Commons Design principles at work? - hp://commons.wikimedia.org/wiki/File:DATA_bus.jpg means an offset of zero. CS 240, Fall 2014! WELLESLEY CS! CS 240, Fall 2014! WELLESLEY CS! No memory access Helpful pseudo-instrucPons Translate x = x + x; to MIPS load immediate Java/C-ish descripon x is a stac (global) variable stored in memory: li $s0, 240! $s0 = 240 .data! x: !.word 0x00000003! des<naon register immediate value ! load address C-ish descripon Two steps: la $s0, count! $s0 = &count 1. Break into several simple Java/C statements, each corresponding to a single MIPS instruc<on. Introduce temporary local variables as needed. des<naon register label 2. Translate to MIPS instruc<ons, represen<ng temporary local variables with registers.! Java/C-ish descripon ! move $s0, $s1! $s0 = $s1 des<naon register source register Design principles (not) at work? 4 9/9/14 CS 240, Fall 2014! WELLESLEY CS! CS 240, Fall 2014! WELLESLEY CS! Translate x = x + x;! MIPS Memory! int[] fibs = new int[6];! MIPS Memory! (232-1)! (232-1)! MIPS private regs! . MIPS private regs! . PC! (A+24)! PC! (A+24)! IR! (A+20)! IR! (A+20)! MIPS user regs! (A+16)! MIPS user regs! (A+16)! $zero! 0 0 0 0 (A+12)! $zero! 0 0 0 0 (A+12)! $v0! (A+8)! $v0! (A+8)! . $a0! (A+4)! $a0! (A+4)! . x! (A)! 0 0 0 3 (A)! $t0! $t0! . $t1! (12)! $t1! (12)! $t2! MIPS! . (8)! $t2! MIPS! . (8)! . $s0! (4)! $s0! (4)! $s1! (0)! $s1! (0)! . 3-18 Design CS 240, Fall 2014! WELLESLEY CS! CS 240, Fall 2014! WELLESLEY CS! Array RepresentaPon int[] fibs = new int[6];! MIPS Memory! (232-1)! ¢ (The basics – minor addi<ons/differences for full details of Java or C) MIPS private regs! . PC! ¢ Store in registers or memory? How? (draw) (A+24)! § Where is the base/start? IR! (A+20)!0 0 0 0 § Where is end? (How big is the array?) MIPS user regs! (A+16)!0 0 0 0 § Where is index i? $zero! 0 0 0 0 (A+12)!0 0 0 3 § $v0! (A+8)! 0 0 0 2 Why is zero-indexing such a good idea? . (A+4)! 0 0 0 1 fibs! $a0! 0 0 0 A array elements . (A)! 0 0 0 1 $t0! . $t1! (12)! $t2! MIPS! . (8)! . $s0! (4)! $s1! (0)! . 3-20 Design 5 9/9/14 CS 240, Fall 2014! WELLESLEY CS! CS 240, Fall 2014! WELLESLEY CS! Translaon fibs[4] = fibs[2] + fibs[3];! MIPS Memory! (232-1)! MIPS private regs! . Translate the following code to MIPS assembly code, assuming: PC! • $a0 represents the local variable fibs and holds the address (A+24)! IR! (A+20)! of a 6-element array of type int[]. 0 0 0 0 ( +16)! MIPS user regs! A 0 0 0 0 $zero! 0 0 0 0 (A+12)!0 0 0 3 fibs[4] = fibs[2] + fibs[3];! array $v0! (A+8)! 0 0 0 2 ! . Two steps: fibs! $a0! 0 0 0 A (A+4)! 0 0 0 1 . (A)! 0 0 0 1 1. Break into several simple Java/C statements, each $t0! corresponding to single MIPS instruc<on. Introduce temporary . $t1! (12)! local variables as needed. $t2! MIPS! . (8)! . 2. Translate to MIPS instruc<ons, represen<ng temporary local $s0! (4)! $s1! (0)! variables with registers. 3-22 Design CS 240, Fall 2014! WELLESLEY CS! CS 240, Fall 2014! WELLESLEY CS! Design principle: Make the common case fast. add immediate for (int i = 0; i < 1000; i++) {! ...! addi $s0, $s1, 8! $s0 = $s1 + 8 }! i = i + 1;! $s0! des<naon register immediate value MIPS: ???! source register Why no subi? (RISC!) 6 9/9/14 CS 240, Fall 2014! WELLESLEY CS! CS 240, Fall 2014! WELLESLEY CS! How could we implement li, la? Logical operaons CS 240, Fall 2014! WELLESLEY CS! CS 240, Fall 2014! WELLESLEY CS! Boolean Algebra General Boolean Algebras ¢ George Boole, 19th Century Operate bitwise on bit vectors ¢ Algebraic representaPon of logic 01101001 01101001 01101001 ¢ Encode boolean as bit: True = 1, False = 0 & 01010101 | 01010101 ^ 01010101 ~ 01010101 ¢ AND: A&B = 1 when both A is 1 and B is 1 ¢ OR: A|B = 1 when either A is 1 or B is 1 ¢ XOR: A^B = 1 when either A is 1 or B is 1, but not both All of the properPes of Boolean algebra apply ¢ 01010101 NOT: ~A = 1 when A is 0 and vice-versa ∀ e.g., a, a XOR a = 0 ^ 01010101 ¢ DeMorgan’s Law: ~(A | B) = ~A & ~B & 0 1 | 0 1 ^ 0 1 ~ How does this relate to set operaons? 0 0 0 0 0 1 0 0 1 0 1 1 0 1 1 1 1 1 1 0 1 0 Truth Tables 27 28 7 9/9/14 CS 240, Fall 2014! WELLESLEY CS! CS 240, Fall 2014! WELLESLEY