Intel® Itanium® Architecture Software Developer’s Manual Volume 2: System Architecture Revision 2.1 October 2002 Document Number: 245318-004 THIS DOCUMENT IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. 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All rights reserved. *Other names and brands may be claimed as the property of others. ii Volume 2: Intel® Itanium® Architecture Software Developer’s Manual Contents Part I: System Architecture Guide 1About this Manual .................................................................................................................. 2:1 1.1 Overview of Volume 1: Application Architecture.......................................................... 2:1 1.1.1 Part 1: Application Architecture Guide ........................................................... 2:1 1.1.2 Part 2: Optimization Guide for the Intel® Itanium® Architecture ..................... 2:2 1.2 Overview of Volume 2: System Architecture ............................................................... 2:2 1.2.1 Part 1: System Architecture Guide ................................................................. 2:2 1.2.2 Part 2: System Programmer’s Guide.............................................................. 2:3 1.2.3 Appendices..................................................................................................... 2:4 1.3 Overview of Volume 3: Instruction Set Reference....................................................... 2:4 1.3.1 Part 1: Intel® Itanium® Instruction Set Descriptions ....................................... 2:4 1.3.2 Part 2: IA-32 Instruction Set Descriptions....................................................... 2:4 1.4 Terminology................................................................................................................. 2:5 1.5 Related Documents..................................................................................................... 2:5 1.6 Revision History .......................................................................................................... 2:6 2Intel® Itanium® System Environment ................................................................................... 2:9 2.1 Processor Boot Sequence........................................................................................... 2:9 2.2 Intel® Itanium® System Environment Overview ........................................................ 2:10 3 System State and Programming Model.............................................................................. 2:13 3.1 Privilege Levels ......................................................................................................... 2:13 3.2 Serialization............................................................................................................... 2:13 3.2.1 Instruction Serialization ................................................................................ 2:14 3.2.2 Data Serialization ......................................................................................... 2:14 3.2.3 Definition of In-flight Resources ................................................................... 2:15 3.3 System State ............................................................................................................. 2:15 3.3.1 System State Overview ................................................................................ 2:16 3.3.2 Processor Status Register (PSR)................................................................. 2:18 3.3.3 Control Registers.......................................................................................... 2:24 3.3.4 Global Control Registers .............................................................................. 2:25 3.3.5 Interruption Control Registers ...................................................................... 2:29 3.3.6 External Interrupt Control Registers ............................................................. 2:34 3.3.7 Banked General Registers ........................................................................... 2:35 4 Addressing and Protection ................................................................................................. 2:37 4.1 Virtual Addressing ..................................................................................................... 2:37 4.1.1 Translation Lookaside Buffer (TLB).............................................................. 2:39 4.1.2 Region Registers (RR) ................................................................................. 2:48 4.1.3 Protection Keys ............................................................................................ 2:48 4.1.4 Translation Instructions ................................................................................ 2:50 4.1.5 Virtual Hash Page Table (VHPT).................................................................. 2:51 4.1.6 VHPT Hashing.............................................................................................. 2:54 Volume 2: Intel® Itanium® Architecture Software Developer’s Manual iii 4.1.7 VHPT Environment........................................................................................2:56 4.1.8 Translation Searching ...................................................................................2:57 4.1.9 32-bit Virtual Addressing ...............................................................................2:60 4.1.10 Virtual Aliasing...............................................................................................2:61 4.2 Physical Addressing...................................................................................................2:61 4.3 Unimplemented Address Bits .....................................................................................2:61 4.3.1 Unimplemented Physical Address Bits..........................................................2:62 4.3.2 Unimplemented Virtual Address Bits.............................................................2:62 4.3.3 Instruction Behavior with Unimplemented Addresses ...................................2:63 4.4 Memory Attributes ......................................................................................................2:63 4.4.1 Virtual Addressing Memory Attributes ...........................................................2:63 4.4.2 Physical Addressing Memory Attributes........................................................2:64 4.4.3 Cacheability and Coherency Attribute...........................................................2:65 4.4.4 Cache Write Policy Attribute..........................................................................2:66 4.4.5 Coalescing Attribute ......................................................................................2:66 4.4.6 Speculation Attributes ...................................................................................2:67 4.4.7 Sequentiality Attribute and Ordering .............................................................2:69 4.4.8 Not a Thing Attribute (NaTPage)...................................................................2:72 4.4.9 Effects of Memory Attributes on Memory Reference Instructions .................2:73 4.4.10 Effects of Memory Attributes on Advanced/Check Loads .............................2:73 4.4.11 Memory Attribute Transition ..........................................................................2:74 4.5 Memory Datum Alignment and Atomicity ...................................................................2:77 5 Interruptions ........................................................................................................................