Chapter to appear in Wiley Encyclopedia of Telecommunications and Signal Processing, John Proakis, ed., Dec. 2002 ATM Switching Thomas M. Chen Stephen S. Liu Dept. of Electrical Engineering Verizon Laboratories Southern Methodist University 40 Sylvan Road PO Box 750338 Waltham, MA 02451 Dallas, TX 75275-0338 Tel: 781-466-2809 Tel: 214-768-8541 Email: [email protected] Fax: 214-768-3573 Email: [email protected] Abstract: ATM switches are high-speed packet switches indication (EFCI). The CLP flag is used to indicate that designed to process and forward ATM cells. The lower priority (CLP=1) cells should be discarded before functional components of a general ATM switch CLP=0 cells in the event of congestion. The HEC field architecture are described. The switch fabric provides allows single bit-error correction and multiple bit-error the central function of cell forwarding. The switch detection over the cell header. fabric design involves trade-offs between various A generic ATM switch architecture with N input approaches and a choice of input or output buffering. In ports and N output ports is shown in Figure 1 (note addition to cell forwarding, ATM switches require switches can have any dimensions). The functions of an capabilities for connection admission control, traffic ATM switching system may be divided broadly into control, and OAM (operations and maintenance). user cell forwarding, connection control, and network Keywords: ATM, cells, switching, connection control, management (3). ATM cells containing user data are traffic control, buffering received at the input ports, and the input port processors prepare the cells for routing through the switch fabric. 1. Introduction The fabric in the center of the switching system ATM (asynchronous transfer mode) is an provides the interconnections between input port internationally standardized connection-oriented packet processors and output port processors. The output port switching protocol designed to support a wide variety of processors prepare the outgoing user cells for data, voice, and video services in public and private transmission from the switch. User cell forwarding is broadband networks (1,2). ATM networks generally characterized by parallelism and high-speed hardware consist of ATM switches interconnected by high-speed processing. The ATM protocol was intentionally transmission links. ATM switches are high-speed packet streamlined to allow incoming cells to be processed switches specialized to process and forward ATM cells simultaneously in hardware and routed through the (packets). Since ATM is a connection-oriented protocol, switch fabric in parallel. Thus, ATM switches have been ATM switches must establish a virtual connection from able to realize high-end performance in terms of one of its input ports to an output port before forwarding throughput and cell forwarding delay. incoming ATM cells along that virtual connection. Connection control, sometimes called the control An ATM cell consists of a 5-byte header followed plane, refers to the functions related to the establishment by a 48-byte information field or payload. The main and termination of ATM virtual connections. purpose of the ATM cell header is to identify the virtual Connection control functions generally encompass: connection of the cell which occupies most of the exchange and processing of signaling information; header bits. An ATM virtual connection is specified by participation in routing protocols; and decisions on the combination of a 12-bit virtual path identifier admission or rejection of new connection requests. (except the first 4 bits are used for generic flow control Network management is currently carried out by at the user-network interface) and a 16-bit virtual SNMP (simple network management protocol), the channel identifier. Virtual paths are bundles of virtual standard protocol for managing data networks. ATM channels. VP crossconnects are designed to route ATM switches typically support an SNMP agent and an ATM traffic on the basis of virtual paths only, which is MIB (management information base). The SNMP agent convenient when large amounts of traffic must be routed responds to requests from a network manager to report or rerouted at the same time. The VPI/VCI fields are status and performance data maintained in the MIB. The followed by a 3-bit payload type (PT), 1-bit cell loss agent might also send alarms to the network manager priority (CLP), and 8-bit header error control (HEC) when prespecified conditions are detected. Since ATM field. The PT field is used to distinguish control cells switches can be viewed as a specific type of network from data cells, and explicit forward congestion element covered within the SNMP framework, the 1 Chapter to appear in Wiley Encyclopedia of Telecommunications and Signal Processing, John Proakis, ed., Dec. 2002 details of SNMP functions in ATM switches are not In the case of SONET/SDH, cells are mapped into the discussed in detail here. payloads of SONET/SDH frames. Network management should also include standardized ATM-layer OAM (operations and 3. Switch Fabrics maintenance) functions. ATM switches carry out OAM It is often convenient to visualize the basic procedures by generating, exchanging, processing, and operation of an NxN switch synchronized to periodic terminating OAM cells. OAM cells are used for fault time intervals equal to the transmission time of one cell, management, performance management, and possibly referred to as a “cell time,” assuming that the other ATM-layer management functions. transmission rate on all links are equal. For example, the cell time for a 155-Mb/s transmission link would be 2. Input and Output Port Processing approximately 53 bytes/155 Mb/s = 2.7 ms. In each cell The input port processors carry out several time, a new set of N incoming cells may appear at the important functions. First, the physical layer signal is input ports and up to N outgoing cells may depart from terminated. For the common case of SONET/SDH the output ports. The N incoming cells are processed in (synchronous optical network/synchronous digital parallel by the input port processors and presented hierarchy), the SONET/SDH framing overhead fields simultaneously to the switch fabric. The switch fabric are processed, and the payload is extracted from the attempts to route the cells in parallel to their appropriate frame. Individual 53-byte ATM cells are delineated in output ports. the payload. There is a chance that more than one cell may Next, each cell header undergoes a number of attempt to reach the same output port at the same time, processing steps. The cell header is checked for bit called output contention, which has four significant errors using the HEC field, and cells with uncorrectable consequences. First, one cell may reach the output port header errors are discarded. The traffic rate of each but the other cells would be lost without buffers existing virtual path or virtual channel is monitored according to somewhere in the switch to temporarily store these an algorithm called the generic cell rate algorithm or cells. Switch fabric designs differ in their choice of GCRA, which is essentially a leaky bucket algorithm. A buffer placement. Second, queues may accumulate in switch may be configured to allow, discard, or “tag” the buffers resulting in random cell delay and cell delay cells (by setting CLP=1) exceeding the allowed traffic variation, which are usually two performance metrics of rate. The VPI/VCI value in each cell header is used to interest. Third, buffers are necessarily finite implying index a routing table to determine the proper output port the possibility of buffer overflow and cell loss. Some and outgoing VPI/VCI values. Incoming VPI/VCI fabric designs may not be able to handle a full traffic values must be translated to outgoing VPI/VCI values load without a probability of cell loss. A performance by every ATM switch. Cells requiring special handling, metric for switch fabrics is the normalized throughput or such as signaling cells and OAM cells, must be utilization defined as the overall fraction of a full traffic recognized and routed to the appropriate processors in load that can be forwarded successfully through the the switch. User cells are prepared for routing through fabric. Ideally, switch fabrics should be capable of 100 the switch fabric, often by prefixing a routing tag to the percent utilization. Fourth, some switch fabrics must cell. The routing tag may consist of the output port, operate at a rate faster than the transmission link rate. service priority, type of cell, timestamp, or other The ratio of the switch fabric rate to the transmission information for routing and housekeeping purposes. link rate is sometimes referred to as a “speedup factor.” Since the routing tag exists only within the switch, its A speedup factor is often related to the scalability of a contents may be chosen entirely by the switch designer. switch fabric design, that is, the difficulty of Before entering the switch fabric, cells may be queued constructing an arbitrarily large fabric (3). in a buffer in the input port processor. The output port processors have the opposite role of 3.1. Shared Memory and Shared Medium the input port processors, namely preparing ATM cells A speedup factor of N is evident in switch fabric for physical transmission from the switch. Cells from designs based on a shared memory or shared medium, the switch fabric may be queued in a buffer in the which are shown in Figure 2. In a shared memory output port processor, in which case the switch is called design, incoming cells are first converted from serial to an output buffered switch. If routing tags are used, the parallel form. They are written sequentially into a dual output port processors remove the routing tag from each port random access memory (4). Their cell headers with user cell.