The Need and Opportunities of Electromigration-Aware Integrated Circuit Design (Invited Paper) Steve Bigalke, Jens Lienig Göran Jerke Jürgen Scheible Roland Jancke Institute of Electronic Design Automotive Electronics Robert Bosch Center Fraunhofer Institute TU Dresden Robert Bosch GmbH for Power Electronics for Integrated Circuits Dresden, Germany Reutlingen, Germany Reutlingen, Germany Dresden, Germany [email protected], [email protected] [email protected] [email protected] [email protected] ABSTRACT 1 INTRODUCTION Electromigration (EM) is becoming a progressively severe reliability The International Roadmap for Devices and Systems (IRDS) [11] challenge due to increased interconnect current densities. A shift and the International Technology Roadmap for Semiconductors from traditional (post-layout) EM verification to robust (pro-active) (ITRS) [12] predict that semiconductors scale and interconnect EM-aware design - where the circuit layout is designed with in- cross-sections will decrease further over the coming years. Ac- dividual EM-robust solutions - is urgently needed. This tutorial companying this trend is a reduction in the necessary currents will give an overview of EM and its effects on the reliability of due to reduced gate capacitances. However, the currents are not present and future integrated circuits (ICs). We introduce the phys- decreasing to the same extent as conductor cross-sections, so that ical EM process and present its specific characteristics that can current densities (resulting from the quotient of the conductor’s be affected during physical design. Examples of EM countermea- current and cross-section) are increasing. sures which are applied in today’s commercial design flows are High current densities are the main driving force of electromi- presented. We show how to improve the EM-robustness of metal- gration (EM). Therefore, the reliability of integrated circuits (ICs) lization patterns and we also consider mission profiles to obtain is increasingly endangered by EM; hence, EM is one of the most application-oriented current-density limits. The increasing inter- important topics that design automation has to deal with nowadays. action of EM with thermal migration is investigated as well. We According to the ITRS [12], we have reached the point where EM conclude with a discussion of application examples to shift from must be considered in our design flows because the interconnects in the current post-layout EM verification towards an EM-aware phys- up-to-date technologies encounter already severe EM degradations ical design process. Its methodologies, such as EM-aware routing, (Fig. 1). The forecast for the next few years is even worse, as the increase the EM-robustness of the layout with the overall goal of ITRS predicts a lack of EM solutions in approximately 5 years [20]. reducing the negative impact of EM on the circuit’s reliability. Consequently, EM damages, such as hillocks or voids, are expected to be observed more and more frequently, limiting the interconnect CCS CONCEPTS reliability. 2 100 2 100 • Hardware → Physical synthesis; Hardware reliability; Circuit − − hardening; Unknown EM solution* 10 Unknown EM solution 10 EM degradation* Current density Current density KEYWORDS Reliability, Electromigration, Current Density, Thermal Migration 1 EM degradation 1 *Our assumption ACM Reference Format: Current density0.1 in MA cm Current density0.1 in MA cm 2018 2020 2022 2024 2026 2028 2018 2020 2022 2024 2026 2028 S. Bigalke, J. Lienig, G. Jerke, J. Scheible and R. Jancke. 2018. The Need and Year Year Opportunities of Electromigration-Aware Integrated Circuit Design: (Invited (a) (b) Paper). In IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER- Fig. 1: (a) The need to consider EM in circuit design can be AIDED DESIGN (ICCAD ’18), November 5–8, 2018, San Diego, CA, USA. San seen in the current densities projections (IRDS, ITRS), which Diego, CA, USA, Nov. 2018. https://doi.org/10.1145/3240765.3265971 has already entered the area of EM degradations and will de- velop into the range of unknown EM solutions [11, 12]. (b) Permission to make digital or hard copies of all or part of this work for personal or EM-aware integrated circuit design tolerates the future cur- classroom use is granted without fee provided that copies are not made or distributed rent density and performance increases by hardening lay- for profit or commercial advantage and that copies bear this notice and the full citation outs against EM through raising the EM thresholds. on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or To make matters worse, the increase of current density takes republish, to post on servers or to redistribute to lists, requires prior specific permission place at the same time as the thresholds of current density decrease and/or a fee. Request permissions from [email protected]. ICCAD ’18, November 5–8, 2018, San Diego, CA, USA (see the yellow and red borders in Fig. 1a). The reason is that smaller © 2018 Copyright held by the owner/author(s). Publication rights licensed to ACM. interconnects are more sensitive to EM damages because, among ACM ISBN 978-1-4503-5950-4/18/11. others, the volume to change the interconnect’s resistance decreases https://doi.org/10.1145/3240765.3265971 with its dimension. In other words, EM must move less material ICCAD ’18, November 5–8, 2018, San Diego, CA, USA S. Bigalke, J. Lienig, G. Jerke, J. Scheible and R. Jancke in smaller interconnects than in larger ones in order to increase T σt σc their resistance. In addition, the introduction of low-k (“softer”) j EM dielectrics further reduces the EM thresholds because their low Fel Fwind SM stiffness weakens the surrounding’s stability27 [ ]. Interconnects σt σc can therefore withstand less mechanical stress than before. The aggressive shrinkage of interconnects in recent decades has Fig. 2: Conduction electrons (blue) collide with atoms (red) left only a few atomic layers within their smallest structures. A creating a momentum exchange and, therefore, driving slowdown of the interconnect shrinking is expected in the future, atoms towards the anode. This reduces (increases) the as predicted in the ITRS [12]. With the introduction of FinFET atomic concentration at the cathode (anode) and introduces transistors, we have already crossed the line where the transistor tensile (compressive) stress σt (σc). itself could drive higher current densities than the contact elements. stresses within the interconnect. If the maximum (minimum) stress This means that the back end of line (BEOL, the portion of IC is higher (lower) than a technology-dependent EM-threshold value, fabrication where the individual devices get interconnected with then a void (hillock) might form. (Note that we use “might” because wiring on the wafer) is becoming the limiting factor for future EM is a statistical process with a certain degree of uncertainty.) performance increases. If voids or hillocks occur, the interconnect might fail as the dam- Another concerning aspect is that EM is accelerated by high age expands. The EM threshold for voids is usually lower than for temperatures. Specifically, the increase of currents densities, as hillocks due to a residual stress within the interconnect caused by well as frequencies, can cause local temperature hot spots within the manufacturing process. the interconnects. The resulting additional amplification of EM, known as “positive feedback loop” [19], leads to an even greater e- reliability degradation due to diffusion and void growth. 1 For all these reasons, EM-aware design has changed from some- σvoid threshold thing designers “should” think about to something they “must” σtensile think about, i.e., it is now a definite requirement. Since the number max σ 0 / t of EM violations will increase significantly in the verification step σ steady state t σcompressive in future technology nodes, a post-layout repair step is no longer 2 t1 feasible. In other words, it is highly important that today’s design -1 σhillock threshold flows change from the traditional (post-layout) EM verification 0 0.5 1 l towards a (pro-active) EM-aware design methodology, enabling /lmax the expected current density rise and ensuring reliable circuits (see Fig. 3: Stress development over time in a confined intercon- Fig. 1b). nect. The final steady-state condition is the balance between EM and SM, defining the maximum and minimum stresses. 2 ELECTROMIGRATION AND ITS The difficulty in this migration process is that the current density, MITIGATION IN TODAY’S DESIGN FLOWS stress and temperature gradient can each cause an atomic flux J® by 2.1 Fundamentals themselves (called EM, SM and TM, respectively) described by CD CD CD Electromigration (EM) is a process of material dislocation mainly J® = J® + J® + J® = eZ *ρ®j + Ωr®σ + Qr®T ; (1) EM SM TM kT kT 2 driven by high current densities. This process also depends on kT temperatures, interconnect geometries, material parameters and with the concentration C, diffusivity D, Boltzmann’s constant k, * manufacturing processes. However, the main cause of EM remains temperature T , electric charge e, effective charge number Z , resis- the movement of electrons driven by an electric field, which collide tivity ρ, current density j, atomic volume Ω, hydrostatic stress σ with the lattice atoms (Fig. 2). This momentum exchange creates an and transported heat Q [28]. Therefore, we have three different driv- electron wind force in electron flow direction, which is much greater ing forces but one problem – the (undesired) migration of atoms. than the (opposite) force of the electric field. The current flow also All three kinds of material migration can mutually amplify or com- heats the interconnect by Joule heating, which, in turn, increases pensate each other, making the distinction even harder. The total the EM effect and can cause thermal migration (TM, also labelled as atomic flux is subjected to the mass balance equation givenby thermomigration).