Ankit Kori Int. Journal of Engineering Research and Applications www.ijera.com ISSN: 2248-9622, Vol. 5, Issue 12, (Part - 3) December 2015, pp.101-108 RESEARCH ARTICLE OPEN ACCESS Ultra Low Power Design and High Speed Design of Domino Logic Circuit Ankit Kori, Mohammed Arif Gyan Ganga Institute of Technology and Science, Jabalpur (M.P.) Abstract The tremendous success of the low-power designs of VLSI circuits over the past 50 years has significant change in our life style. Integrated circuits are everywhere from computers to automobiles, from cell phones to home appliances. Domino logic is a CMOS based evolution of the dynamic logic techniques based on either PMOS or NMOS transistors. Dynamic logic circuits are used for their high performance, but their high noise and extensive leakage has caused some problems for these circuits. Dynamic CMOS circuits are inherently less resistant to noise than static CMOS circuits. In this paper we proposed different domino logic styles which increases performance compared to existing domino logic styles. According to the simulations in cadence virtuoso 65nm CMOS process, the proposed circuit shows the improvement of up thirty percent compared existing domino logics. Keywords:- Domino Logic, Dynamic Node, Evaluation Network, Low power Consumption. I. Introduction nano-scaling, enormous power is consumed as static The tremendous success of the low-power power dissipation[2]. designs of VLSI circuits over the past 50 years has significant change in our life style. Integrated circuits The domino circuits are used in various circuits, are everywhere from computers to automobiles, from especially-memory [3-5], multiplexor,comparator [6], cell phones to home appliances. The growth of the and arithmetic circuit. [7-8] and also used in full low-power circuits is predicted to continue at faster adders that are most important part of a CPU. pace. Since the first integrated circuit was invented in Additionally, domino circuits are important the labs of Texas instruments in 1958. The integrated components in other applications such as digital capacity of the transistors on a single chip is doubling signal processing (DSP) architectures and every two to three years [1]. In 1965, Gorden Moore microprocessors [9], which rely on the efficient showed that for any MOS transistor technology there implementation of generic arithmetic logic and exists a minimum cost that maximizes the number of floating point units to execute dedicated algorithms. components per integrated circuit. He also predicted Various design approaches had been investigated for that as transistor dimensions are shrunk from realizing domino CMOS topologies in the literature onetechnology generation to the next, the minimal [10]. The Extensive use of high speed domino circuits cost point allows doubling the number of transistor attracts many researchers in this field. There are every two to three years. This trend has been various issues related to domino circuits, such as sustained and is expected to be maintained well into power consumption, speed and noise immunity [11. first 20 years of this century. With the dramatic increase in chip complexity ULSI (Ultra Large Scale II. Literature Review Integration), number of transistors and power Domino logic is a CMOS logic style obtained by consumption are growing rapidly. The objective of adding a static inverter to the output of the basic designing digital VLSI circuits is to minimize silicon dynamic gate circuit, it can be used to implement area per logic circuit as to have large number of gates non-inverting functions [3, 12]. The resulting per chip. Area reduction occurs in three different structure is shown in Fig.1.6. Domino CMOS circuit ways: (i) advances in processing technology that has advantage in terms of high speed and wide fan-in enable reduction of the minimum device size (ii) over static CMOS circuits.The domino CMOS circuit circuit design techniques (iii) careful chip layout. suffers from noise margin problem due to charge Power consumption and signal delay are crucial redistribution between parasitic capacitances at the elements in designing of high-performance low internal nodes of the circuit and hence false output voltage VLSI circuits. The reduction of power may be resulted. Domino logic consists of a single dissipation and the improvement of the speed require clock, which is used to precharge the dynamic node optimization at all levels in the design procedure. In of the circuit in precharge phase and to evaluate the www.ijera.com 101|P a g e Ankit Kori Int. Journal of Engineering Research and Applications www.ijera.com ISSN: 2248-9622, Vol. 5, Issue 12, (Part - 3) December 2015, pp.101-108 function made by NMOS network in evaluation improvement in robustness of the standard domino phase. circuits, keeper upsizing can be done. But this Designs of digital integrated circuits rely on three upsizing of keeper transistor results in contention major criteria: Low power consumption, small chip which degrades the power and evaluation delay area and high speed. In VLSI design, the selection of characteristics of the conventional domino circuits logic family is dictated by the system performance as [15]. shown in Fig.1. Table.1. summarizes the performance comparisons of logic styles [13]. From the table VDD VDD domino CMOS circuit has higher speed and it require PRECHARGE TRANSISTOR KEEPER TRANSISTOR lower area as compared to other logic style. High speed operation of domino circuits is primarily due to CLK MP1 MP2 the lower noise margins of domino circuits as compared to static gates. VDD VDD MP3 Clock DYNAMIC NODE OUTPUT MN1 INn IN2 IN Output 1 Inputs NMOS Network Fig.2 Standard Footerless Domino Logic Circuit VDD VDD PRECHARGE TRANSISTOR KEEPER TRANSISTOR CLK MP1 MP2 Fig. 1. A domino CMOS circuit. VDD Table I. summarizes the performance comparisons of MP3 logic styles [13]. Logic Speed Power Noise Area DYNAMIC NODE OUTPUT Families Consump Margin MN1 tion INn IN2 IN1 Static Medium Medium High High CMOS Pseudo Fast High Medium Low NMOS CLK Dynamic Fast High Low Low CMOS Domino Fast High Low Low CMOS Fig.3 Standard Footed Domino logic circuit (a) Footless Standard Domino Logic & Footed (b) Conditional Keeper Domino Logic Standard Domino Logic Now considering the another efficient technique that Firstly considering the footless standard domino logic is Conditional Keeper Domino Logic (CKDL) which and footed standard domino logic as shown in Fig.2 is shown in Fig.4. that make use of two keeper and 3. In conventional domino logic, a keeper transistors [9]. One of the two keeper transistors is transistor is utilized as a feedback for retaining the weaker one (K1) and other one is stronger (K2) as state of the dynamic node. But the resulting shown in Fig.2. In the working, initially K1 is on contention between the keeper transistor and pull during the starting of evaluation phase for down networks reduces the power and speed maintaining the state of dynamic node. If the state of characteristics of the circuit [14]. Now in comparison dynamic node being retained high after the delay for with the footless standard domino logic, footed inverters, then that will make the stronger keeper K2 standard domino logic achieves better immunity to to be turned on. This method results in the reduction noise due to the stacking effect. To achieve the www.ijera.com 102|P a g e Ankit Kori Int. Journal of Engineering Research and Applications www.ijera.com ISSN: 2248-9622, Vol. 5, Issue 12, (Part - 3) December 2015, pp.101-108 of contention and also improves noise immunity. Diode footed domino logic is another technique Noise characteristics can further be reduced by the presented in [17]. Customization to the standard sizing of delay elements but this will give rise to the domino circuit has been done by adding NMOS higher power dissipation. And area overhead is also transistor in a diode configuration in series with the one disadvantage due to NAND gate for CKDL [16]. evaluation network as shown in Fig.6. This diode VDD footer (M1) results in the sub threshold leakage reduction due to the stacking effect [12,18-20]. But CLK Delay there is performance degradation due to the diode PK1 VDD footer that‟s why mirror transistor [M2] is employed VDD PRECHARGE TRANSISTOR to increase the performance characteristic. VDD VDD CLK MP1 PK2 CLK MPRE MK DYNAMIC NODE OUTPUT DYNAMIC NODE OUTPUT INn IN2 IN1 Evaluation Network Fig. 4 Conditional Keeper Domino Logic N_FOOT M1 M2 (c) High Speed Domino Logic High speed domino logic is another configuration shown in figure 3. The working of this domino logic results in the reduction of the contention between the CLK M3 M4 keeper transistor and the evaluation network with a use of clock delay as shown in Fig.5. As comparison to the CKDL technique it makes use of only strong keeper and eliminates the weaker one so as to Fig.6. Diode Footed Domino Logic enhancing speed. This keeper transistor remains off at the starting of the evaluation phase which results in Current-Comparison Domino the current reduction, but at the cost of power The proposed technique uses the difference and the consumption, area overhead and lower noise comparison between the leakage current of the OFF immunity due to the float dynamic node [10]. Transistors and the switching current of the ON transistors of the pull down network to control the PMOS keeper transistor,yielding reduction of the VDD VDD VDD contention between keeper transistor and the pull MP3 down network from which previously proposed techniques have suffered. Moreover, using the CLK stacking effect, leakage current is reduced and the MP1 MP2 MN1 performance of the current mirror is improved. In this circuit, the reference current is compared with the pull down network current.