This document is downloaded from DR‑NTU (https://dr.ntu.edu.sg) Nanyang Technological University, Singapore. Wire level encapsulation framework for increasing FPGA design productivity Oliver, Timothy Francis 2009 Oliver, T. F. (2009). Wire level encapsulation framework for increasing FPGA design productivity. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/19266 https://doi.org/10.32657/10356/19266 Downloaded on 24 Sep 2021 11:37:52 SGT ATTENTION: The Singapore Copyright Act applies to the use of this document. Nanyang Technological University Library A WIRE LEVEL ENCAPSULATION FRAMEWORK FOR INCREASING FPGA DESIGN PRODUCTIVITY Timothy Francis Oliver School of Computer Engineering A thesis submitted to the Nanyang Technological University in fulfilment of the requirement for the degree of Doctor of Philosophy 2009 ATTENTION: The Singapore Copyright Act applies to the use of this document. Nanyang Technological University Library ATTENTION: The Singapore Copyright Act applies to the use of this document. Nanyang Technological University Library Acknowledgements I would like to thank my supervisor Dr Douglas Maskell for his support, encouragement, and careful distillation of ideas during the production of this thesis. I would like to thank Dr. Timo Bretschneider for his suggestions and valuable insights. I thank Dr. Bertil Schmidt for his inspirational drive for accelerated computing. Many thanks to Dr Chris Clarke for the lively discussions and generous hospitality. I thank Mr. Saurav Bhattacharyya for his motivational speeches, Mr. Mohit Sindhwani for a thousand conversations about nothing, Mr. Konstantin Melikhov for his brilliance, and Mr. Tobias Trenschel for plentiful coffee breaks and philosophical discussions. I would like to thank Ms. Nah Kiat Joo and all the people at CHiPES for their excellent help and support. I would like to thank Dr. Ian McLoughlin, Dr. Lai Ming-Kit (Edmund) and Mr. John Rowe for helping me secure a place at NTU. I would like to thank my family and friends for supporting me from such a distance. I would like to thank Mrs Amy Jesudason for her encouragement and plentiful exam reminders and Mr Jeffrey Jesudason, who I probably owe a pint of pineapple juice. Finally I would like to thank Miss Joanne Jesudason for her love, support, patience, and undying belief that I can succeed. ATTENTION: The Singapore Copyright Act applies to the use of this document. Nanyang Technological University Library ATTENTION: The Singapore Copyright Act applies to the use of this document. Nanyang Technological University Library Table of Contents 1 Introduction................................................................................................................2 1.1 Problem Statement.........................................................................................................3 1.2 Contributions..................................................................................................................4 1.3 Journal Publications........................................................................................................5 1.4 Conference Publications.................................................................................................5 1.5 Organisation...................................................................................................................6 2 Background.................................................................................................................7 2.1 FPGA Technology..........................................................................................................7 2.1.1 History.....................................................................................................................7 2.1.2 Silicon Manufacture.................................................................................................8 2.1.3 Computing Performance..........................................................................................8 2.1.4 Reconfigurable Computing Architectures................................................................9 2.1.5 Discussion..............................................................................................................12 2.2 FPGA Architecture.......................................................................................................13 2.2.1 Overview................................................................................................................13 2.2.2 Computing Resource..............................................................................................13 2.2.3 Interconnect............................................................................................................14 2.3 Designer Productivity...................................................................................................17 2.3.1 Design Abstraction.................................................................................................17 2.3.2 Synthesis and Optimisation....................................................................................18 2.3.3 High Level Language Synthesis.............................................................................19 2.3.4 Packing and Placement..........................................................................................20 2.3.5 Routing...................................................................................................................22 2.3.6 Design Reuse.........................................................................................................24 2.3.7 Software Design Productivity................................................................................25 2.3.8 Compile Reuse.......................................................................................................26 2.3.9 Discussion..............................................................................................................27 2.4 Pre-Routed Component Encapsulation.........................................................................27 2.4.1 Abstraction of Component Based Systems............................................................28 2.4.2 Component Encapsulation.....................................................................................29 2.4.3 Communication Layer............................................................................................31 2.4.4 Discussion..............................................................................................................35 3 Framework................................................................................................................37 3.1 Introduction..................................................................................................................37 3.2 Architectural Model......................................................................................................39 3.2.1 Basic Tile Structure................................................................................................39 3.2.2 Tile Resource.........................................................................................................40 3.2.3 Interconnect ...........................................................................................................41 3.3 Net-List Mapping ........................................................................................................43 3.3.1 Placement ..............................................................................................................43 3.3.2 Routing ..................................................................................................................44 3.3.3 Interconnect usage..................................................................................................46 3.4 The Limits of Pre-Routing............................................................................................47 3.4.1 Component Encapsulation.....................................................................................47 3.4.2 Design Definition Framework................................................................................49 3.4.3 Wire Identification.................................................................................................50 3.4.4 Wire Use Policy.....................................................................................................50 3.4.5 Interface Definition................................................................................................51 3.4.6 Component Connection Extensions.......................................................................52 3.4.6.1 Interface Extension..........................................................................................52 3.4.6.2 Cornering Link Extension................................................................................53 ATTENTION: The Singapore Copyright Act applies to the use of this document. Nanyang Technological University Library 3.4.6.3 Tunnelling Link Extension..............................................................................55 3.4.7 Floor Planning and Component Shaping...............................................................56 3.5 Experimental Design Environment...............................................................................58 3.5.1 Design Entry..........................................................................................................58 3.5.2 Interconnect Graph Generator................................................................................59