Journal of Automation and Control Engineering Vol. 2, No. 4, December 2014 Software Architecture of Ladder Compiller to Opcode for Micro PLC Based on ARM Cortex Processor Muhammad A. Murti, Agung N. Jati, Lukam Mawardi, and Siti A.N.F. Agustina Telkom University, Bandung, Indonesia Email: {mam, ang}@ittelkom.ac.id, [email protected], [email protected] Abstract— Programmable Logic Controller (PLC) is an then to execute program. During in its process, PLC electronic circuit that can do a variety control function on conducts three main operation [1]-[3]: complex levels and used as a substitute of mechanic relays Reading input data from external equipment via components that used on control system. Over the past ten input module; to fifteen years, many different programming languages have been used to program the PLC. For one programming Executing a logic control program stored in the language such as ladder diagram, each type of PLC have the memory of PLC; rules and differences in the way of programming. In fact, Updating the data in the output module. modern industry usually uses not only one type of PLC Besides, PLC also consists of software element which alone but various types of PLC. It would be inefficient, both will construct ladder diagram or mnemonic code. That in terms of time and material. This paper discuss about code will be sent to PLC using programming device to ladder comppiler software design for micro class of PLC trigger instruction in PLC such as read data input or write based on ARM processor. The architecture software was data to output/memory. developed on the VB.Net platform. The designed software can work properly to compile ladder diagrams into Ladder diagram is the easiest program leanguage to commands/instructions and sent it to PLC. The design user for develop controlling rule on PLC. Ladder diagram included status monitoring which is received I/O PLC status. describes the instructions like Boolean/Logic operations The communications between ladder programmer software and switching operations. There are some samples of and PLC for each architecture part can work properly ladder diagram such as normally open/close, add, without any interruption with 100% reliable in terms of compare, coil, and, or, etc [5]. compiling from ladder diagram to ladder opcode. This This paper discuss as follows: second section will software has been able to do the compiling process less than discuss about the architecture of ladder diagram a second. programmer software; in the third section will be continued by discussing the result of implementation and Index Terms—Programmable Logic Controller, Ladder Programmer, Software Architecture experiment; and the last section will contain conclusions and suggestions. II. SYSTEM MODELLING I. INTRODUCTION A. Ladder Programmer Programmable Logic Controller (PLC) is basically a Fig. 1 show the shoftware architecture of Ladder controller specially designed to control a process or machine. Based on the number of inputs/outputs it has, programmer with four main menus. generally PLC can be divided into 3 (three) groups [1]-[3]: PLC Micro (I/O PLC < 32 terminal); PLC Mini (I/O PLC ~ 32 -128 terminal); PLC Large /PLC Rack (I/O PLC > 128 terminal). Generally, PLC consists of two main structuring components: Central Processing Unit (CPU) and interface system of input/output [1]-[4]. PLC works by reading the state of its inputs, for later used to change the state of its output. The changes that occurred in the PLC output is depending on the program. There is a compiler that compiles the ladder diagram to be opcode that will be loaded on PLC memory. PLC’s processor needs Operating System (OS) to read and interpret opcode and Manuscript received October 15, 2013; revised December 13, 2013. Figure 1. Software Architecture ©2014 Engineering and Technology Publishing 363 doi: 10.12720/joace.2.4.363-366 Journal of Automation and Control Engineering Vol. 2, No. 4, December 2014 This Ladder Programmer Software has several Fig. 2 shows all procedure which designed on VB.net. functions as follows : One of all is the serial communication procedure. This As a GUI between PLC and user, it will show procedure contains the UART protocol, so the software ladder design and I/O status of PLC can transfer data from / to PLC. We design the sofware Compile the ladder diagram to ladder opcode and work with baudrate 19200 bps. instruction list Other procedure is designed as like as usual given from Simulate processes the platform to simplify the software architecture. This Control the PLC, and consists instructions such as research is focused on ladder to opcode comppiler design. PLAY, STOP, MONITOR, LOAD TO PLC, and PLC PROGRAMMING C. Ladder to Opcode Comppiler Design Handle data communication using RS232 format. In this procedure, we described encode-decode process This software was developing on VB.Net platform from ladder diagram or instruction to binary opcode. because more compatible with many Windows OS, Opcode construct by three binary code ### and followed support GDI+ to build graphical pictures and text, and by <data>. Three binary code provide possiblility to also reduce the VGA load. compille up to 1000 instructions. Table I contains To develop the software, there was several steps in common use instructions list that developed on this work. developing the compiller. They are: Design page only use one picturebox and every cell Build serial communication based on UART create by lines from GDI+ makes every cell not deffine Protocol by array picturebox, but array region. Region is a velue Build the interface of Main Form thet represent viewer coordinate area from point (x1,y1) Design the algorithm of Ladder Diagram to (x2,y1), and (x1,y2) to (x2,y2)). The program will find Compilation region that contain ladder component and compille the Design of Compiling Procedures ladder to appreciate opcode. Build the Output Interface Build the Monitoring Status Interface TABLE I. OPCODE FORMAT B. Ladder Comppiller Concept Instructions Opcode Ladder Opcode Format The ladder compiller program software has the following working flow as can be seen on Fig. 2. LOAD 000 000<data> Fig. 2 shows all procedure which designed on VB.net. LOAD NOT 001 001<data> One of all is the serial communication procedure. This procedure contains the UART protocol, so the software OR 002 002<data> can transfer data from / to PLC. We design the sofware OR NOT 003 003<data> work with baudrate 19200 bps. AND 004 004<data> Start AND NOT 005 005<data> Choose serial No Compiling OR LOAD 006 006<data> communication design? AND LOAD 007 007<data> Yes Compile to Choose and drop ladder Yes Ladder ladder OUTPUT 008 008<data> component/s into the field Opcode opcode? No No OUT NOT 009 009<data> Compile to Yes No Sending Opcode Is design instructions Send to ROM? TIMER 020 020<timer value> to ROM PLC done? list? Yes Yes No COUNTER 022 022<counter value> No Simulate Instruction Status COMPARE 030 030<data><data2> List Monitoring? Yes ADD 070 070<data><data2> Is there any Yes error/s? Monitoring PLC SUBSTRACT 071 071<data><data2> No I/O No Save design? No Ladder opcode operand word will be classified into Stop Monitoring? Yes three categories below: Design file Yes is ready to If the first digit is “0”, then the operand is in BCD compile format If the first digit is “1”, then the operand is in No Exit? Binary format Yes If the first digit is “2”, then the operand is from register. End Table II contain the data memory area as designed Figure 2. Software design flow diagram PLC Format. ©2014 Engineering and Technology Publishing 364 Journal of Automation and Control Engineering Vol. 2, No. 4, December 2014 TABLE II. DATA AREA PLC FORMAT TABLE IV. TIME PROCESS COMPILATION No Instructions Output Timer/Counter Average Time Process (ms) Instructions Input Area Area Area 1 OR 1.566 LOAD, LOAD NOT, 000000- 000800- 2 AND OR, OR NOT, AND, 1.636 000715 001215 AND NOT, OR LOAD, (bit) (bit) 3 Timer AND LOAD 0.0818 000800- 4 Counter 0.1284 OUTPUT, OUTNOT 001215 5 ADD (bit) 0.0384 0097 – 0160 6 SUBSTRACT TIMER (TIM) 0.0429 (word) 7 COMPARE 0.0884 0233 – 0296 COUNTER (CNT) (word) Logical operation need more time to compile than 0008- other operation. It’s because in the logical operation 0000-0007 0097-0224/0233- COMPARE (CMP) 0012 (word) 0360 (word) system must convert the hexadecimal operand into binary (word) operand first and the execute them. Time proccess for 0008- 0000-0007 0097-0224/0233- ADD (ADD) 0012 single instruction has less then 2 ms. (word) 0360 (word) (word) C. Load Process 0008- 0000-0007 0097-0224/0233- SUBSTRACT (SUBS) 0012 (word) 0360 (word) Load process test is to prove that the opcode as (word) compiled result can be send to PLC ROM and readable by PLC processsor properly. It also proves that serial III. RESULTS AND DISCUSSION communication is work properly. The scenario is trying to send simplest opcode. There A. Opcode Decoding is the ladder diagram which only consist an input and an There are some tests to prove that all of the opcode ouput. See the picture below. instructions are true, compare with the design. All of the tests only use the simplest operation, which is consist two operands for each ladder. The reslut of tests can be seen on Table III. Figure 3. Simplest ladder diagram TABLE III. .LADDER TO OPCODE To send the opcode, first software will send a No Ladder Opcode command #LOADCPURDY and then the opcode. If load 1 OR 000000000004000001008000800@ opcode to PLC success, PLC will respond by replying software #LOADCPUSUCCESS and if not then PLC will 2 AND 000000000003000001009000800@ reply #LOADCPUOVERLOAD.