IEEE EMBEDDED SYSTEMS LETTERS, VOL. 4, NO. 3, SEPTEMBER 2012 69 Zebra: Building Efficient Network Message Parsers for Embedded Systems Julien Mercadal, Laurent Réveillère, Yérom-David Bromberg, Bertrand Le Gal, Tegawendé F. Bissyandé, and Jigar Solanki Abstract—Supporting standard text-based protocols in em- the limited resources, particularly with regard to the compu- bedded systems is challenging because of the often limited tational power, memory, and energy, embedded systems often computational resources that embedded systems provide. To provide. Indeed, such FSMs may contain several hundred states overcome this issue, a promising approach is to build parsers directly in the hardware. Unfortunately, developing such parsers and several thousand complex transitions, making the size of is a daunting task for most developers as it is at the crossroads of corresponding parsers too large (several dozen kilobytes) for several areas of expertise, such as low-level network programming embedded systems. To simplify parser construction, automatic or hardware design. In this letter, we propose Zebra, a generative approaches including Gapa [1] and Zebu [2] have been pro- approach that drastically eases the development of hardware posed for generating an FSM implementation from a high-level parsers and their use in network applications. To validate our approach, we used Zebra to generate hardware parsers for widely specification of a protocol. However, to the best of our knowl- used protocols, including HTTP, SMTP, SIP, and RTSP. Our edge, existing automatic approaches do not address embedded experiments show that Zebra-based parsers are up to 11 times systems requirements and, in particular, have not explored the faster than software-based parsers. use of dedicated hardware to improve their performance. Thus, Index Terms—Circuits and systems, client-server systems, the resulting generated code is still CPU intensive. computers and information processing software, distributed Implementing an FSM using a dedicated hardware archi- computing, embedded software, field programmable gate arrays, tecture, as compared to a software-based implementation, middleware. improves performance. Indeed, a hardware parser can be de- signed specifically to execute multiple computations in parallel I. INTRODUCTION and in one processor clock cycle. Moreover, conditional jumps, whicharemassivelyusedinsoftwareimplementationofFSMs, are processed in one clock cycle without pipeline break penal- MBEDDED systems are increasingly required to interact ties. Finally, a hardware-based FSM requires a lower working both among themselves as well as with legacy infrastruc- E frequency to reach the same performance than its software tures to provide advanced services to end-users. This kind of counterpart, and thus consumes less energy. communication among heterogeneous entities requires a pro- Nonetheless, developing a network application that uses tocol to manage their interaction. Traditionally, because of their hardware parsers is challenging, requiring not only exper- highly constrained resources, nonstandard application-specific tise in hardware design and integration, but also substantial binary protocols where message parsing and message construc- knowledge of the protocols involved and an understanding of tion are simple have been used [18]. The use of nonstandard pro- low-level network programming. These issues are challenging tocols, however, complicates the interaction with other systems, on an individual basis and the need to address all of them at as it is required in many emerging applications. Thus, the use of once makes the development of hardware protocol message standard text-based protocols has been getting greater attention. parsers particularly difficult. For example, the SIP protocol is now being used in sensor net- In this letter, we propose a codesign based architecture and a works [8] and mobile ad hoc networks [9], [16]. generative approach for building and using hardware parsers in Standard text-based protocol message parsers are typically a network application. To this end, we present a domain-specific implemented in software as finite state machines (FSMs), language, called Zebra, for describing standard text-based pro- using a low-level language such as C to provide efficiency. tocol message formats and related processing constraints. Zebra However, developing such parsers is challenging because of is an extension of augmented Backus-Naur form (ABNF) [6], the variant of Backus-Naur form (BNF) used in request for com- Manuscript received April 20, 2012; accepted June 08, 2012. Date of publica- ments (RFCs), to specify the syntax of network protocol mes- tion July 24, 2012; date of current version September 14, 2012. This manuscript was recommended for publication by S. K. Shukla. sages, implying that the programmer can simply copy a network J. Mercadal, L. Réveillère, Y.-D. Bromberg, T. F. Bissyandé, and J. Solanki protocol message grammar from an RFC to begin developing a are with Laboratoire Bordelais de Recherche en Informatique (LaBRI), Univer- parser. It extends ABNF with annotations indicating which mes- sity of Bordeaux, Talence cedex F-33405, France (e-mail: [email protected]; [email protected]; [email protected]; [email protected]; sage fragments should be stored in data structures, and other se- [email protected]) . mantic information. B. Le Gal is with Laboratoire de l’Integration du Materiau au Systeme AZebra specification is processed by a compiler that gener- (IMS), University of Bordeaux, Talence cedex F-33405, France (e-mail: [email protected]) . ates both the HDL source code of the hardware parser imple- Digital Object Identifier 10.1109/LES.2012.2208617 mented as an FSM and the associated C code to drive it. The 1943-0663/$31.00 © 2012 IEEE 70 IEEE EMBEDDED SYSTEMS LETTERS, VOL. 4, NO. 3, SEPTEMBER 2012 application runs on top of middleware that hides low-level de- tails to developers and manages the generated hardware parsers. The contributions of this letter are as follows: • We designed and implemented a generative approach for building hardware parsers for embedded systems. Our ap- proach is based on a codesign architecture to provide hard- ware parsing capabilities to software applications. • We conducted a set of experiments on protocols such as HTTP, RTSP, SIP, and SMTP to assess our approach. Pre- liminary results show a speedup of message parsing from 3.9to11comparedtosoftware-basedparsers. The remainder of this letter is structured as follows. Section II presents the Zebra hardware platform designed to support the execution of message parsers, the middleware to manage the Fig. 1. Zebra approach. underlying hardware units, and the Zebra language to describe message formats and a compiler that produces the necessary HDL and C code. Section III presents the performance evalua- the Zebra language to describe message formats and the com- tion of Zebra-based parsers. Finally, Section IV reviews related piler that produces the necessary HDL and C code. research works, and Section V concludes the letter and discusses future work. A. Zebra Hardware Platform We combined the microprocessor and the parsing units into II. ZEBRA APPROACH one chip (SoC) to 1) reduce power consumption; 2) simplify The most efficient way to implement an embedded system board layout; 3) preserve signal integrity; 4) avoid electromag- application is to develop a fully-customized architecture, netic interference and; and 5) allow very fast communication using programmable logic devices or even dedicated applica- links between them. We use field programmable gate array tion-specific integrated circuits (ASICs). However, hardware (FPGA) devices for system integration since they are particu- design is a tedious and time consuming process compared to larly suitable for embedded system prototyping [4]. However, traditional software development. To alleviate the burden in the proposed approach is not limited to FPGA devices and can hardware-based implementations, the codesign methodology easily be extended to ASIC targets. proposes to slice an application based on the performances it As illustrated in Fig. 1, the Zebra platform consists of a gen- requires. Parts of the application that require high performance eral-purpose microprocessor to execute the application logic, are implemented using dedicated hardware units. Less sensitive and a set of dedicated hardware units for message parsing. performance parts are implemented as software code running Our current implementation relies on a LEON3 soft CPU core, over a general-purpose microprocessor. Typically, the lowest which is an open-source implementation of the SPARC v8 part of a network application, known as the protocol-handling 32-bit architecture, allowing its instruction set to be extended. layer, consumes 25% of the total message processing time The use of such a soft CPU core, combined with the generation [5], [19]. This layer must thus be efficient and calls for a of generic HDL code, enables implementation of our system hardware-based implementation to reach the expected level of on any ASIC or FPGA target, without any changes. performance. To do so, we have developed the Zebra approach In Zebra, parsing units are implemented as coprocessors, in- dedicated to building efficient network message parsers. Our terconnected with the microprocessor through a set of dedicated approach consists of a hardware platform to support parser links. In particular, a parsing unit has a specificdesignthatin-