Washington University in St. Louis Washington University Open Scholarship All Computer Science and Engineering Research Computer Science and Engineering Report Number: WUCSE-2006-10 2006-01-01 Automatic Application-Specific Customization of Softcore Processor Microarchitecture, Masters Thesis, May 2006 Shobana Padmanabhan Applications for constrained embedded systems are subject to strict runtime and resource utilization bounds. With soft core processors, application developers can customize the processor for their application, constrained by available hardware resources but aimed at high application performance. The more reconfigurable the processor is, the more options the application developers will have for customization and hence increased potential for improving application performance. However, such customization entails developing in-depth familiarity with all the parameters, in order to configure them effectively. This is typically infeasible, given the tight time-to-market pressure on the developers. Alternatively, developers could explore all possible configurations, but... Read complete abstract on page 2. Follow this and additional works at: https://openscholarship.wustl.edu/cse_research Part of the Computer Engineering Commons, and the Computer Sciences Commons Recommended Citation Padmanabhan, Shobana, " Automatic Application-Specific Customization of Softcore Processor Microarchitecture, Masters Thesis, May 2006" Report Number: WUCSE-2006-10 (2006). All Computer Science and Engineering Research. https://openscholarship.wustl.edu/cse_research/159 Department of Computer Science & Engineering - Washington University in St. Louis Campus Box 1045 - St. Louis, MO - 63130 - ph: (314) 935-6160. This technical report is available at Washington University Open Scholarship: https://openscholarship.wustl.edu/ cse_research/159 Automatic Application-Specific Customization of Softcore Processor Microarchitecture, Masters Thesis, May 2006 Shobana Padmanabhan Complete Abstract: Applications for constrained embedded systems are subject to strict runtime and resource utilization bounds. With soft core processors, application developers can customize the processor for their application, constrained by available hardware resources but aimed at high application performance. The more reconfigurable the processor is, the more options the application developers will have for customization and hence increased potential for improving application performance. However, such customization entails developing in-depth familiarity with all the parameters, in order to configure them effectively. This is typically infeasible, given the tight time-to-market pressure on the developers. Alternatively, developers could explore all possible configurations, but being exponential, this is infeasible even given only tens of parameters. This thesis presents an approach based on an assumption of parameter independence, for automatic microarchitecture customization. This approach is linear with the number of parameter values and hence, feasible and scalable. For the dimensions that we customize, namely application runtime and hardware resources, we formulate their costs as a constrained binary integer nonlinear optimization program. Though the results are not guaranteed to be optimal, we find they are near-optimal in practice. Our technique itself is general and can be applied to other design-space exploration problems. Department of Computer Science & Engineering 2006-10 Automatic Application-Specific Customization of Softcore Processor Microarchitecture, Masters Thesis, May 2006 Authors: Shobana Padmanabhan Corresponding Author: [email protected] Web Page: http://www.arl.wustl.edu/~sp3/ Abstract: Applications for constrained embedded systems are subject to strict runtime and resource utilization bounds. With soft core processors, application developers can customize the processor for their application, constrained by available hardware resources but aimed at high application performance. The more reconfigurable the processor is, the more options the application developers will have for customization and hence increased potential for improving application performance. However, such customization entails developing in-depth familiarity with all the parameters, in order to configure them effectively. This is typically infeasible, given the tight time-to-market pressure on the developers. Alternatively, developers could explore all possible configurations, but being exponential, this is infeasible even given only tens of parameters. This thesis presents an approach based on an assumption of parameter independence, for automatic microarchitecture customization. This approach is linear with the number of parameter values and hence, feasible and scalable. For the dimensions that we customize, namely application runtime and hardware Type of Report: Other Department of Computer Science & Engineering - Washington University in St. Louis Campus Box 1045 - St. Louis, MO - 63130 - ph: (314) 935-6160 WASHINGTON UNIVERSITY THE HENRY EDWIN SEVER GRADUATE SCHOOL DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING AUTOMATIC APPLICATION-SPECIFIC CUSTOMIZATION OF SOFTCORE PROCESSOR MICROARCHITECTURE by Shobana Padmanabhan Prepared under the direction of Professors Ron K. Cytron and John W. Lockwood A thesis presented to the Henry Edwin Sever Graduate School of Washington University in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE May 2006 Saint Louis, Missouri WASHINGTON UNIVERSITY THE HENRY EDWIN SEVER GRADUATE SCHOOL DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING ABSTRACT AUTOMATIC APPLICATION-SPECIFIC CUSTOMIZATION OF SOFTCORE PROCESSOR MICROARCHITECTURE by Shobana Padmanabhan ADVISORS: Ron K. Cytron and John W. Lockwood May 2006 Saint Louis, Missouri Applications for constrained embedded systems are subject to strict runtime and resource utilization bounds. With soft core processors, application developers can customize the processor for their application, constrained by available hardware resources but aimed at high application performance. The more reconfigurable the processor is, the more options the application developers will have for customization and hence increased potential for improving application perfor- mance. However, such customization entails developing in-depth familiarity with all the parameters, in order to configure them effectively. This is typically infeasible, given the tight time-to-market pressure on the developers. Alternatively, developers could explore all possible configurations, but being exponential, this is infeasible even given only tens of parameters. This thesis presents an approach based on an assumption of parameter independence, for automatic microarchitecture customization. This approach is linear with the number of parameter values and hence, feasible and scalable. For the dimensions that we customize, namely application runtime and hardware resources, we formulate their costs as a con- strained binary integer nonlinear optimization program. Though the results are not guaran- teed to be optimal, we find they are near-optimal in practice. Our technique itself is general and can be applied to other design-space exploration problems. Dedicated to my mother Saraswathi and late father Padmanabhan. Contents List of Figures ................................... viii Acknowledgments ................................. xi 1 Introduction ................................... 1 1.1 Soft Core Processors . 2 1.2 Motivation . 5 1.3 Thesis Objectives . 7 1.4 Related Work . 8 1.5 Contributions . 11 1.6 Thesis Outline . 11 2 Background ................................... 13 2.1 Liquid Architecture Platform . 13 2.2 FPX Platform . 17 2.3 FPGA . 18 2.4 LEON Parameterization . 19 2.4.1 Processor System . 19 2.4.2 Synthesis Options . 26 2.4.3 Clock Generation . 27 2.4.4 Memory Controller . 27 2.4.5 AMBA Configuration . 28 2.4.6 Peripherals . 29 2.4.7 PCI . 29 2.4.8 Boot Options . 30 2.4.9 VHDL Debugging . 31 2.5 Parameters for Application-Specific Customization . 32 2.6 Constrained Binary Integer Nonlinear Programming . 34 2.7 Alternative Search Techniques . 36 iii 2.8 Benchmarks . 37 2.8.1 Benchmark I - BLASTN . 37 2.8.2 Benchmark II - Commbench DRR . 38 2.8.3 Benchmark III - Commbench FRAG . 38 2.8.4 Benchmark IV - BYTE Arith . 38 3 Approach .................................... 39 3.1 Cost functions . 40 3.1.1 Application Runtime Cost . 40 3.1.2 FPGA Resource Cost . 40 3.1.3 Total Cost . 41 3.2 Our Approach . 41 4 Problem Formulation .............................. 44 4.1 Parameter Validity Constraints . 45 4.1.1 Instruction Cache Parameter Validity Constraints . 45 4.1.2 Data Cache Parameter Validity Constraints . 48 4.1.3 Integer Unit Parameter Validity Constraints . 49 4.2 FPGA Resource Constraints . 49 4.3 Objective Function . 50 4.3.1 Application Runtime Optimization . 50 4.3.2 FPGA Resources Optimization . 51 4.3.3 Power Dissipation Optimization . 51 4.4 Overall Problem Formulation . 51 5 Evaluation of the Technique .......................... 55 5.1 Benchmark I - BLASTN . 57 5.1.1 Analysis of Parameter Independence Assumption . 57 5.1.2 Analysis of Cost Approximations . 57 5.2 Benchmark II - CommBench DRR . 59 5.2.1 Analysis of Parameter Independence Assumption . 59 5.2.2 Analysis of Cost Approximations . 60 5.3 Benchmark III - CommBench FRAG . 61 5.3.1 Analysis of Parameter Independence Assumption . 61 5.3.2 Analysis of Cost Approximations . 61 iv 5.4 Benchmark IV - BYTE Arith . 62 5.5 Summary of Evaluation . 62