|||||I|| USOO5484664A United States Patent 19 11 Patent Number: 5,484,664 Kitahara et al. (45) Date of Patent: Jan. 16, 1996 54. HETERO-EPITAXIALLY GROWN 4,933,300 6/1990 KoinuIma et al. ....................... 437/10 COMPOUND SEMCONDUCTOR 4,963,509 10/1990 Umeno et al..................... 437/132 SUBSTRATE 5,130,269 7/1992 Kitahara et al. 437/11 5,144,379 9/1992 Eshita et al. ....... ... 257/190 75 Inventors: Kuninori Kitahara, Zama; Nobuyuki 5,300,186 4/1994 Kitahara et al. ........................ 437/1 9th, Ag: Mashi Ozeki, FOREIGN PATENT DOCUMENTS OKO?anna, all OT Japan p 0207216 1/1987 European Pat. Off.. (73) Assignee: Fujitsu Limited, Kawasaki, Japan 0214610 3/1987 European Pat. Off.. 61-64118 4/1986 Japan. 62-291909 12/1986 Japan. 21 Appl. No.: 184,438 62-1225 1/1987 Japan. 63-228714 9/1988 Japan. 22 Filed: Jan. 21, 1994 62-1224 11/1988 Japan. Related U.S. Application Data OTHER PUBLICATIONS 62) Division of Ser. No. 864,552, Apr. 7, 1992, Pat. No. 5,300, Vernon et al, "Metalorganic Chemical Vapor Deposition of 186, which is a division of Ser. No. 342,785, Apr. 25, 1989, GaAs on Si’, Journal of Crystal Growth, vol. 77, 1986, pp. Pat. No. 5,130,269. 530-538. 30 Foreign Application Priority Data Mr.pplie F.yS1cs t A, axis-Layer Superlattices', Apr. 27, 1988 JP Japan .................................. 63-05036 Levine et al., "Long wavelength GaSb photoconductive Oct. 20, 1988 JP Japan .................................. 63-264618 detectors grown in Si substrates', 32o Applied Physics (51) Int. Cl. ............................................... HOL27/12 R R 1986, No. A. E. tress in inP 52 U.S. Cl. ........................... 428/641: 257/190: 257/200 1tSuru et a, Buller layer effects on reS1dual Stress 1n 1 (52) s 90; on Si substrate”, Appl. Phys. Lett. 54(18), May 1, 1989. 58) Field of Search ............................. 428/641; 257/190,257/200 Ozeki et al., "Kinetic6&T.--- processes in atomatic-layer epitaxy of GaAs and AlAs using a pulsed vapor-phased method”, J. 56 Ref Cited Vac. Sci. Technol.B.5(4). (56 S Shinohara, "Dislocation-free GaAs epitaxial growth with U.S. PATENT DOCUMENTS the use of modulation-doped AlAs-GaAs superlativve 4,058.430 11/1977 Suntola et al. .......................... buffer layers", Appl. Phys. Lett. 52(7), Feb. 15, 1988. 4,180,825 12/1979 Mason ....................................... 357/16 Primary Examiner-Robert Kunennund 2.5 : 3. Sheaa - a a a 2.26 Attorney, Agent, or Firm-Armstrong, Westerman, Hattori, 4,734,478 3/1988 Tsubakimoto et al. ................. E. McLeland & Naughton 4,767,492 8/1988 Kobayashi et al...................... 561606 57 ABSTRACT 4,806,996 2/1989 Luryi ......................................... 357/16 4,829,022 5/1989 Kobayashi et al. ..................... 437/107 A method of growing a gallium arsenide single crystal layer 4,833,103 5/1989 Agostinelli et al. .................... 437/23 on a silicon substrate comprises steps of growing a buffer 4,835,116 5/1989 Lee et al. ........................... 437.1111 layer of aluminium arsenide on the silicon substrate by 4,835,583 5/1989 Morioka et al. ........................ 2571.90 atomic layer epitaxy, and growing the gallium arsenide 23. g al . E. single crystal layer on the buffer layer epitaxially. 4859,627 8/1989 Sunakawa ... ... 437/81 4,861,47 8/1989 Michizuki et al. ..................... 1561610 4 Claims, 7 Drawing Sheets O. : Si o: A. U.S. Patent Jan. 16, 1996 Sheet 1 of 7 5,484,664 C EVACUATION EXHAUST FIG.1 U.S. Patent Jan. 16, 1996 Sheet 2 of 7 5,484,664 PHASE I TEMPERATURE OOO PHASE II PHASE II 6OO c. 500 2O 4O 6O 8O 18O TIME ( MNUTES) FIG. 2 FLOW RATE Ag As GROWTH GaAs GROWTH I MOCVD H H H-e- 2: TMA : TMG TMA OR TMG FIG.3B ASH3 F G. 3C i: :::::::: t ME U.S. Patent Jan. 16, 1996 Sheet 3 of 7 5,484,664 00|| 09 |Oglºy uÐquunN?osuºÁD?ououu I-‘7’€) Al Sueu SW-S peZ puON U.S. Patent Jan. 16, 1996 Sheet 4 of 7 5,484,664 09Z ISuosvog) d???n?SWO9)–BTW (,uus)?gausuDubu OLZ06Z --G'?)I A Sueu U.S. Patent Jan. 16, 1996 Sheet 7 of 7 5,484,664 E O 5,484,664 1. 2 HETERO-EPTAXIALLY GROWN gallium arsenide substrate layer is prevented. Unfortunately, COMPOUND SEMICONDUCTOR the formation of such a super lattice structure requires an SUBSTRATE extremely precise control of the crystal growth which is difficult to achieve with reliability in the presently available This is a division, of application Ser. No. 07/864,552, 5 technique. filed Apr. 7, 1992, U.S. Pat. No. 5,300,186, which is a Alternatively, it is proposed to interpose a polycrystalline division of application Ser. No. 342,785, filed Apr. 25, 1989, gallium arsenide buffer layer between the silicon substrate U.S. Pat. No. 5,130,269. and the gallium arsenide layer to absorb the mismatching of the lattice constant and thermal expansion. In this approach, O a thin gallium arsenide polycrystalline buffer layer having a BACKGROUND OF THE INVENTION thickness of typically 10 nm is deposited on the silicon substrate at a temperature of about 400° 450° C. prior to The present invention generally relates to fabrication of deposition of the single crystal gallium arsenide substrate semiconductor devices and more particularly to an epitaxial layer. Then, the temperature is raised to about 600-750° C. growth of a compound semiconductor layer such as gallium and the gallium arsenide substrate layer is deposited for a arsenide on a silicon wafer. 15 thickness of about a few microns. When the temperature is Gallium arsenide (GaAs) is a typical compound semicon raised from the first temperature to the second temperature, ductor material used for laser diodes and various fast speed the polycrystalline gallium arsenide buffer layer is recrys semiconductor devices such as metal-semiconductor field talized into single crystal and the gallium arsenide substrate effect transistor (MESFET), high electron mobility transistor layer deposited thereon grows while maintaining epitaxial (HEMT), heterojunction bipolar transistor (HBT) and the relation with the gallium arsenide buffer layer underneath. like because of its characteristic band structure and high In this technique, however, it is difficult to obtain a electron mobility. Such a semiconductor device is con satisfactorily flat surface for the single crystal gallium structed on a gallium arsenide wafer sliced from a gallium arsenide layer. This is because the polycrystalline gallium arsenide ingot grown as a single crystal or on a gallium arsenide buffer layer takes an island structure on the surface arsenide substrate grown epitaxially on a surface of a silicon 25 of the silicon wafer and the non-flat morphology of the wafer. In the latter construction, one can avoid the difficulty surface of the polycrystalline gallium arsenide buffer layer is of handling heavy and brittle gallium arsenide wafer during transferred to the gallium arsenide substrate layer provided the fabrication process of the device by using a light and thereon. In other words, the the surface of the gallium strong silicon wafer fabricated by a well established process arsenide substrate layer becomes waved in correspondence for the base of the substrate. Further, one can easily obtain 30 to the island structure of the buffer layer. In spite of the use a large diameter wafer in such a construction. As a result, of reduced temperature at the time of formation of the buffer one can handle the wafer easily and reduce the manufactur layer so as to suppress the formation of the island structure ing cost of the device. Further, such a wafer is suited for by reducing the growth rate, the island structure cannot be fabrication of a so called optoelectronic integrated circuit eliminated satisfactorily. Further, such a waved surface of (OEIC) devices wherein gallium arsenide laser diode and the 35 the gallium arsenide substrate cannot be eliminated even if like are assembled together with silicon transistors on a the thickness of the gallium arsenide layer is increased to a common semiconductor chip. few microns or more. When growing gallium arsenide on silicon wafer epitaxi Further, it is proposed to use other material such as ally, however, one encounters various difficulties. Such 40 silicon-germanium solid solution SiGe for the buffer difficulties are caused mainly due to large difference in the layer while changing the composition y continuously from lattice constant and thermal expansion between silicon and the surface of the silicon substrate to the bottom of the gallium arsenide. For example, the lattice constant of silicon gallium arsenide substrate layer as is described in the is smaller than that of gallium arsenide by about 4% and the Japanese Laid-open Patent Application No.62-87490. Alter thermal expansion coefficient of silicon is smaller than that 45 natively, it is proposed to use a gallium arsenide based of gallium arsenide by about 230%. From simple calculation mixed crystal such as InGaAs or AlGaAs with a based on the difference in the lattice constant, it is predicted composition x of about 4.5x10 for the buffer layer (Japa that the gallium arsenide substrate constructed as such nese Laid-open Patent Application No. 62-291909). In both contains dislocations with a density in the order of 10/cm’. of these alternatives, there is a problem in the surface Thus, a simple epitaxial growth of gallium arsenide layer 50 morphology as already described. made directly on silicon Substrate is usually unsuccessful. On the other hand, the applicants made a discovery during Even if successful, such a layer involves significant defects a series of experiments to deposit a group III-V compound such that they cannot be used as the substrate for a semi such as aluminium arsenide (AlAs) on a gallium arsenide conductor device.