IMPLEMENTATION OF HIERARCHICAL PREDECODER/DECODER STRUCTURE IN OPENRAM OPENSOURCE MEMORY COMPILER By MANJU KIRAN SUBBARAYAPPA Bachelor of Engineering in Electronics and Communication, Sir M Visveswaraya Institute of Technology, Bangalore, Karnataka, India July 2011 Submitted to the Faculty of the Graduate College of the Oklahoma State University in partial fulfillment of the requirements for the Degree of MASTER OF SCIENCE July, 2013 IMPLEMENTATION OF HIERARCHICAL PREDECODER/DECODER STRUCTURE IN OPENRAM OPENSOURCE MEMORY COMPILER Thesis Approved: Dr. James E Stine Thesis Adviser Dr. Louis Johnson Dr. Reza Abdolvand ii Name: MANJU KIRAN SUBBARAYAPPA Date of Degree: JULY, 2013 Title of Study: IMPLEMENTATION OF HIERARCHICAL REDECODER/DECODER STRUCTURE IN OPENRAM OPENSOURCE MEMORY COMPILER. Major Field: ELECTRICAL AND COMPUTER ENGINEERING ABSTRACT: This thesis deals with the implementation of the decoder structure within the OPENRAM, open-source memory compiler. Memory compilers are software scripts that are used to generate memory macros according to a user's specification. Standard- Random Access Memory (SRAM) consists of an architecture that is made up of memory arrays and peripheral circuits. The peripheral circuit includes row decoder, column selection, pre-charge, write drivers and sense amplifier circuits. In this thesis, Python software is utilized to hierarchically create a decoder that is constructed efficiently given a set of arguments. In order to accomplish this task, a hierarchical decoder utilizes two levels of decoding to build its structure efficiently. This module accepts parameters for a given SRAM size, detects the pre-decoder stages required for the given address size and generates the hierarchical decoder structure accordingly. Area and Delay results are demonstrated within the FREEPDK technology for several different sizes. iii TABLE OF CONTENTS Chapter Page I. INTRODUCTION ......................................................................................................1 1.1 Introduction ........................................................................................................1 1.2 Motivation ..........................................................................................................3 1.3 Thesis Organization ...........................................................................................4 II. BACKGROUND .......................................................................................................5 2.1 SRAM Memory Architecture .............................................................................5 2.2 6 T SRAM memory cell ......................................................................................7 2.3 Address Decoder ...............................................................................................10 2.4 Pre-charge Circuit .............................................................................................12 2.5 Write-Driver Circuit..........................................................................................13 2.6 Sense amplifier..................................................................................................14 2.7 Column Multiplexer ........................................................................................15 2.8 Complete memory operation.............................................................................16 2.8.1 Memory read operation ...........................................................................16 2.8.1 Memory write operation .........................................................................17 III. METHODOLOGY ................................................................................................19 3.1 Brief introduction to Python .............................................................................19 3.2 overview of memory implementation ...............................................................20 3.3 NCSU 45 Nanometer Process Design Kit ........................................................27 3.4 Supporting EDA tools .......................................................................................28 3.5 GDS-Mill Python Package ................................................................................29 3.6 Python script organization ................................................................................31 3.7 Using the compiler ............................................................................................33 iv Chapter Page IV.HIERARCHICAL DECODER IMPLEMENATION IN MEMORY COMPILER 35 4.1 Overview .........................................................................................................35 4.2 Software implementation of layout ..................................................................41 4.3 Hierarchical decoder Layout Generation using python scripts ........................45 4.4 Simulation using Nanosim ...............................................................................51 4.5 Timing analysis of different decoders size ......................................................56 4.6 Memory Layout Generation using the OPENRAM .........................................59 4.6.1 Memory Timing ......................................................................................60 4.6.3 Incorporation of Hierarchical decoder into Memory layout ...................61 V. RESULTS ...............................................................................................................65 5.1 Results and conclusion .....................................................................................65 5.3 Futures extensions for different memory structure generation ........................66 REFERENCES ............................................................................................................67 APPENDICES1 ...........................................................................................................68 APPENDICES2 ...........................................................................................................70 v LIST OF TABLES Table Page 1 Cache sizes in different processors ..........................................................................3 2 EDA tool set ..................................................................................................... 27-28 3 2:4 ADDRESS INPUT OUTPUT ..........................................................................34 4 4:16 Address decoder input and output .................................................................38 5 List of Nanosim Simulation files ...........................................................................50 6 List of Nanosim output files ..................................................................................51 6 Address decoder size delay area comparison ........................................................55 vi LIST OF FIGURES Figure Page 1 Intel’s I7 Quad Core Processor Die block diagram .................................................2 2 Performance gap between processor and memory ...................................................3 3 SRAM Memory Architecture ..................................................................................5 4 16 X 4 SRAM Memory............................................................................................6 5 6 T SRAM Cell ........................................................................................................7 6 Voltage Transfer Curve ............................................................................................8 7 Read operation .........................................................................................................9 8 Write operation ......................................................................................................10 9 2 to 4 address decoder ............................................................................................11 10 4 input nand gate using two input nand gates ......................................................12 11 Pre – Charge Circuit.............................................................................................12 12 Write Driver Circuit .............................................................................................13 13 Latch type sense amplifier Circuit .......................................................................14 14 Column Selection Circuit .....................................................................................15 15 OPENRAM Memory Compilers..........................................................................19 16 Layout of 6 transistor memory cell ......................................................................22 17 Layout of Pre Charge Circuit ...............................................................................23 18 Layout of the Sense amplifier ..............................................................................23 vii Figure Page 19 Layout Write driver cell .......................................................................................24 20 Layout of inverter ................................................................................................25 21 Layout of Nand gate .............................................................................................25 22 GDSMILL Python Package .................................................................................29 23 Python scripts arrangement ..................................................................................30