Engineer-to-Engineer Note EE-295 Technical notes on using Analog Devices DSPs, processors and development tools Visit our Web resources http://www.analog.com/ee-notes and http://www.analog.com/processors or e-mail [email protected] or [email protected] for technical support. a Implementing Delay Lines on SHARC® Processors Contributed by Divya Sunkara Rev 1 – October 25, 2006 Introduction algorithm with cross feedback. The left and right channels are coupled by introducing cross- This EE-Note discusses the implementation of a feedback coefficients, so that the delayed output delay line on the ADSP-2126x, ADSP-21362, of one channel is fed into the input of the other ADSP-21363, ADSP-21364, ADSP-21365, and channel, creating a stereo delay effect. For ADSP-21366 SHARC® series of processors, details, refer to the sample-based delay line code hereafter representatively referred to as ADSP- for the ADSP-21262 processor located in the 21262 processors. associated .ZIP file. Because ADSP-21262 processors access external The implementation of the above algorithm memory via the parallel port, special requires two delay lines: one for left channel, and considerations are required while implementing one for the right channel. The delay lines are delay lines on these processors when compared implemented as circular buffers in external to other SHARC processors. memory. The length of the delay line depends on Discrete filters can be implemented with sample- the required delay and the input sampling rate. based delay lines and a set of coefficients that For example, a 0.5-second delay requires a define the filter. Due to memory constraints, 24000 tap delay line for an 48-KHz input delay lines are usually implemented in external sampling rate. Since this implementation requires memory using various techniques. feedback from the delayed output, the total delay length is 24001, which includes the previous This document discusses two delay-line sample for the delay. Since the external memory implementations using the parallel port. First, a is 8 bits wide, each tap (32-bit word) requires sample-based delay line using parallel port core four external memory locations. Hence, the total access is discussed. Later in the document, delay-line buffer length is four times the number techniques used in a block-based delay line of taps. implemented via parallel port DMA are described. Due to its feedback structure, this algorithm requires a read from the delay-line buffer followed by a write. The read and write occur in Sample-Based Delay Lines a sample-based manner. Because the core accesses external memory via parallel port DMA Delay effects are achieved by implementing registers (EIPP, EMPP, and ECPP), the circular finite impulse response (FIR) or infinite impulse buffers in external memory are implemented by response (IIR) filters. For sample-based delay using the DAG registers. Even though the DAG lines, this document focuses on the registers cannot access external memory, the implementation of a simple stereo delay effect DAG registers' circular address capabilities are Copyright 2006, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer product design or the use or application of customers’ products or for any infringements of patents or rights of others which may result from Analog Devices assistance. All trademarks and logos are property of their respective holders. Information furnished by Analog Devices applications and development tools engineers is believed to be accurate and reliable, however no responsibility is assumed by Analog Devices regarding technical accuracy and topicality of the content provided in Analog Devices’ Engineer-to-Engineer Notes. a used to calculate the address to access the external memory via the parallel port. The DAG register pointing to external circular buffers are then assigned to the parallel port external index register (EIPP) in order for the core to access the data. Initially, the read pointer points to the buffer's last tap and the write pointer points to the first tap. Following each read and write, both Figure 1. FIR Filter pointers are decremented and the transfers continue sample by sample. For sample-based The impulse response of the filter is available in processing, a single output is transmitted at a Figure 2. Figure 3, which illustrates the FIR particular time. implementation using block-based delay lines in external memory, depicts the implementation Core-driven transfers to the external memory via with a block of eight samples, a filter length of the parallel port can be initiated using four six, and two tap accesses (tap2 and tap4). techniques as described in the ADSP-2126x Figure 1 shows the FIR implementation of a SHARC Processors Peripherals Manual as well single block of data. as in the ADSP-2136x SHARC Processor Hardware Reference. The known-duration access The FIR implementation of a single block of technique, which is the most efficient of all the input data requires three processes: a write accesses, is used for reads and writes. With 8-bit DMA, read DMAs, and the delay process external memory, each 32-bit access via the (convolution of input and coefficient values). parallel port requires a known duration of 15 Each of these processes is discussed in detail cycles [(1 ALE-cycle * 3 CCLK) + (4 data- below. cycles * 3 CCLK)] with a PPDUR (parallel port Even though the block-based delay line code duration setting) of 3. The program can use the implements the filter shown in Figure 1 and 15 cycles that occur after the data is written to Figure 2, Figure 3 shows the implementation of the transmit register (or read from the receive only two taps of the filter to simplify the register of parallel port) efficiently for other illustration; the additional taps follow the same purposes. template. Another consideration while accessing data via the parallel port is the addressing of external memory. This is due to the fact that the parallel port no longer accepts logical addresses but requires physical addresses of the external memory to transfer data. Consecutive 32-bit values in external memory are addressed by an offset of 4 because each 32-bit value occupies four-byte-wide locations of external memory. Block-Based Delay Lines For the block-based delay-line technique, this document discusses the implementation of a low- Figure 2. FIR Filter Response reflection setting FIR as shown in Figure 1. Implementing Delay Lines on SHARC® Processors (EE-295) Page 2 of 7 a both channels is the same (Listing 1). The parameters passed to this function vary, and are based on a particular channel. The DMA for the left channel takes place with the internal index register pointing to TrLptr and the external index register of parallel port pointing to WrLptr. Similarly, for the right channel, the internal index register points to TrRptr and external index register points to WrRptr. The internal modify register is set to 2 and the external modify register is set to -1, placing each channel data in counter clockwise direction in external delay line memory starting with the first sample located at the start of the delay line buffer as shown in Figure 4. Figure 3. FIR Filter Implementation void TransDMA(int *Tinptr, int Tcount, int *Textptr) { *pPPCTL = 0; Write DMA /* initiate parallel port DMA registers for The sample data arrives as a block of first DMA*/ *pIIPP = Tinptr; NUM_SAMPLES. The data in the input buffer *pIMPP = 2; contains the left and right channel samples as *pICPP = Tcount; shown in Figure 4. Therefore, two delay lines are *pEMPP = -1; *pEIPP = Textptr; required for each of the channel. The processing /* For 8-bit external memory, the External on each of the channels is identical. The length count is four times the internal count */ *pECPP = Tcount * 4; of each delay line is equal to: *pPPCTL = PPTRAN| PPBHC| PPDUR4; Filter Length + ((NUM_SAMPLES/2) -1) *pPPCTL |= PDEN|PPEN; // enalble parallel port DMA For block-based FIR implementations, the /*poll to ensure parallel port has completed processing starts with writing a block of data the transfer*/ do{ (write DMA) to the delay-line buffer in external ;} memory. Figure 4 illustrates the write DMA while( (*pPPCTL & (PPBS|PPDS) ) != 0); process to the left and right delay lines. With a *pPPCTL = 0; // disable parallel port block length ( ) of eight and a filter // start of second DMA NUM_SAMPLES } length of six, the delay length of each of the channels is nine. Each of the nine locations of the Listing 1. TransmitDMA.c delay line shown in Figure 4 corresponds to four locations in external byte-wide memory. Therefore, the total delay line length in external memory is 28 (9 x 4). The write pointers for each of the channels are initialized to the first locations of the left and right delay line buffers shown as WrLptr and WrRptr in Figure 4. Two write DMAs take place, one for each channel. The function used to perform a write DMA for Implementing Delay Lines on SHARC® Processors (EE-295) Page 3 of 7 a void WriteDMA( int *Inptr, int *Wrptr, int *TestDMA, int *BUF) { int DMAcount1,DMAcount2,Inc; int*Wrptr1,*Wrptr2,*Inptr1,*Inptr2; if (Wrptr < TestDMA) { DMAcount2 = (TestDMA-Wrptr)/4; DMAcount1 = ((NUM_SAMPLES)/2) - DMAcount2; Wrptr1 = Wrptr; // Pointer to the start DMA Inc = -(DMAcount1 * 4); Wrptr2 = Wrptr1; // external pointer for first DMA Wrptr2 = circptr(Wrptr2, Inc, BUF, LENGTH); // external pointer for second DMA Inptr1 = Inptr; // internal pointer for first DMA Inptr2 = Inptr1+ DMAcount1*2; // internal pointer for second DMA TransDMA(Inptr1, DMAcount1, Wrptr1); TransDMA(Inptr2, DMAcount2, Wrptr2); } else { TransDMA(Inptr, NUM_SAMPLES/2, Wrptr); Figure 4. Write DMA } RdptrInit= Wrptr; // Next Read pointer for Circular Buffering read DMA Inc =-((NUM_SAMPLES/2)*4); Since the parallel port DMA parameter registers WrptrTemp = Wrptr; do not take into account the wrapping of circular WrptrTemp = circptr(WrptrTemp,Inc,BUF,LENGTH); buffers, if the write pointer needs to wrap around // Next write pointer for write DMA the end, the DMA is split into two separate DMA } sections.