TMS320C6452 DSP Host Port Interface (HPI) User's Guide Literature Number: SPRUF87A October 2007–Revised May 2008 2 SPRUF87A–October 2007–Revised May 2008 Submit Documentation Feedback Contents Preface ........................................................................................................................................ 6 1 Introduction......................................................................................................................... 9 1.1 Purpose of the Peripheral................................................................................................ 9 1.2 Features .................................................................................................................... 9 1.3 Functional Block Diagram .............................................................................................. 10 1.4 Industry Standard(s) Compliance Statement ........................................................................ 11 1.5 Terminology Used in This Document ................................................................................. 11 2 Peripheral Architecture ....................................................................................................... 12 2.1 Clock Control............................................................................................................. 12 2.2 Memory Map ............................................................................................................ 12 2.3 Signal Descriptions ...................................................................................................... 12 2.4 Pin Multiplexing .......................................................................................................... 12 2.5 Protocol Description ..................................................................................................... 12 2.6 Endianness Considerations ............................................................................................ 12 2.7 Architecture and Operation............................................................................................. 14 2.8 Reset Considerations ................................................................................................... 31 2.9 Initialization ............................................................................................................... 32 2.10 Interrupt Support......................................................................................................... 32 2.11 EDMA Event Support ................................................................................................... 34 2.12 Power Management ..................................................................................................... 34 2.13 Emulation Considerations .............................................................................................. 34 3 Registers........................................................................................................................... 35 3.1 Peripheral Identification Register (PID) ............................................................................... 35 3.2 Power and Emulation Management Register (PWREMU_MGMT) ............................................... 36 3.3 Host Port Interface Control Register (HPIC) ......................................................................... 37 3.4 Host Port Interface Write Address Register (HPIAW) .............................................................. 39 3.5 Host Port Interface Read Address Register (HPIAR)............................................................... 40 SPRUF87A–October 2007–Revised May 2008 Table of Contents 3 Submit Documentation Feedback www.ti.com List of Figures 1 HPI Block Diagram ......................................................................................................... 11 2 Example of Host-Processor Signal Connections....................................................................... 15 3 HPI Strobe and Select Logic.............................................................................................. 16 4 16-bit Multiplexed-Mode Host Read Cycle.............................................................................. 19 5 16-bit Multiplexed-Mode Host Write Cycle .............................................................................. 20 6 Multiplexed-Mode Single-Halfword HPIC Cycle (Read or Write) .................................................... 21 7 HRDY Behavior During an HPIC or HPIA Read Cycle in the 16-bit Multiplexed Mode........................... 22 8 HRDY Behavior During a Data Read Operation in the 16-bit Multiplexed Mode (Case 1: HPIA Write Cycle Followed by Nonauto-increment HPID Read Cycle) ........................................................... 22 9 HRDY Behavior During a Data Read Operation in the 16-bit Multiplexed Mode (Case 2: HPIA Write Cycle Followed by Auto-increment HPID Read Cycles) .............................................................. 23 10 HRDY Behavior During an HPIC Write Cycle in the 16-bit Multiplexed Mode ..................................... 23 11 HRDY Behavior During a Data Write Operation in the 16-bit Multiplexed Mode (Case 1: No Auto-incrementing)..................................................................................................... 24 12 HRDY Behavior During a Data Write Operation in the 16-bit Multiplexed Mode (Case 2: Auto-incrementing Selected, FIFO Empty Before Write).............................................................. 24 13 HRDY Behavior During a Data Write Operation in the 16-bit Multiplexed Mode (Case 3: Auto-incrementing Selected, FIFO Not Empty Before Write)......................................................... 24 14 HRDY Behavior During an HPIC or HPIA Read Cycle in the 32-Bit Multiplexed Mode .......................... 25 15 HRDY Behavior During a Data Read Operation in the 16-Bit Multiplexed Mode (Case 1: HPIA Write Cycle Followed by Non-auto-increment HPID Read Cycle) .......................................................... 25 16 HRDY Behavior During a Data Read Operation in the 32-Bit Multiplexed Mode (Case 2: HPIA Write Cycle Followed by Auto-increment HPID Read Cycles) .............................................................. 26 17 HRDY Behavior During an HPIC Write Cycle in the 32-Bit Multiplexed Mode..................................... 26 18 HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 1: No Auto-incrementing) ......................................................................................................... 27 19 HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 2: Auto-incrementing Selected, FIFO Empty Before Write).............................................................. 27 20 HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 3: Auto-incrementing Selected, FIFO Not Empty Before Write)......................................................... 28 21 FIFOs in the HPI ........................................................................................................... 29 22 Host-to-CPU Interrupt State Diagram.................................................................................... 32 23 CPU-to-Host Interrupt State Diagram.................................................................................... 33 24 Peripheral Identification Register (PID).................................................................................. 35 25 Power and Emulation Management Register (PWREMU_MGMT) .................................................. 36 26 Host Port Interface Control Register (HPIC) – Owner (Host) Access Permissions................................ 37 27 Host Port Interface Control Register (HPIC)–Non-owner (DSP) Access Permissions ............................ 37 28 Host Port Interface Write Address Register (HPIAW) ................................................................. 39 29 Host Port Interface Read Address Register (HPIAR) ................................................................. 40 4 List of Figures SPRUF87A–October 2007–Revised May 2008 Submit Documentation Feedback www.ti.com List of Tables 1 HPI Pins ..................................................................................................................... 13 2 Options for Connecting Host and HPI Data Strobe Pins.............................................................. 17 3 Access Types Selectable With the HCNTL Signals ................................................................... 17 4 Cycle Types Selectable With the HCNTL and HR/W Signals ........................................................ 18 5 HPI Registers Relative to Base Address 0200 0030h................................................................. 35 6 Peripheral Identification Register (PID) Field Descriptions ........................................................... 35 7 Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions............................ 36 8 Host Port Interface Control Register (HPIC) Field Descriptions ..................................................... 38 9 Host Port Interface Write Address Register (HPIAW) Field Descriptions........................................... 39 10 Host Port Interface Read Address Register (HPIAR) Field Descriptions ........................................... 40 SPRUF87A–October 2007–Revised May 2008 List of Tables 5 Submit Documentation Feedback Preface SPRUF87A–October 2007–Revised