SYSTEM MANAGEMENT I2C, I3C AND SPI SELECTOR GUIDE A BROAD CATALOG OF INTERFACE COMPONENTS FOR ALL YOUR DESIGN NEEDS I2C-BUS: THE SERIAL REVOLUTION By replacing complex parallel interfaces with a 2 straightforward yet powerful serial structure, the I C-bus SDA revolutionized chip-to-chip communications. SCL Invented by NXP (Philips) more than 30 years ago, the 2 I C- bus uses a simple two-wire format to carry data one uC bit at a time. It performs inter-chip addressing, selection, control and data transfer. Speeds are up to 400 kHz (fast mode), 1 MHz (fast mode plus), 3.4 MHz (high-speed mode), or 5 MHz (ultra-fast mode). New 12.5 MHz I3C controllers with backwards compatibility to I2C are starting to hit the market which complete with the higher speeds of the SPI bus. Parallel Interface I2C Serial Interface The I2C-bus shrinks the IC footprint and leads to lower IC costs. Plus, since far fewer copper traces are needed, it enables a smaller PCB, reduces design complexity and lowers system cost. MCU I/O A/D LCD RTC MCU D/A New Function I2C-bus devices are available in a wide range of functions. Each target device has its own I2C-bus address, selectable using address pins set high (1) or low (0). Information is transmitted byte by byte, and each byte is acknowledged by the receiver. There can be multiple devices on the same bus, and more than one IC can act as controller. The controller role is typically played by a microcontroller. Write data Controller Target SDA S Target Address W A Data A Data A P Transmitter Receiver < n data bytes > SCL Read data SDA S Target Address R A Data A Data A P Receiver Transmitter < n data > last data byte SCL bytes The controller always sends the clock S = Start condition R/W = read/write A = Acknowledge A = Not acknowledge P = Stop condition 2 www.nxp.com OVERVIEW OF MIPI I3C Energy Consumption Data Rate milliJoules per Megabit for I3C Data Modes (100pf) Mbps for I3C Data Modes (@ 12.5 MHz) vs. I2C (100pf, 3.54KOhm) vs. I2C (@400 KHz) MIPI I3C (and the publicly available MIPI I3C Basic) provide 4.5 45 a scalable, medium-speed, utility and control bus for 4 40 connecting peripherals to an application processor. Its 3.5 35 3 30 2 design incorporates key attributes from both I C-bus and 2.5 25 SPI interfaces to provide a unified, high-performance, 2 20 low-power interface solution that delivers a flexible 1.5 15 1 10 2 upgrade path for I C-bus and SPI implementers. Originally .5 5 introduced in 2017, I3C was the culmination of a multi-year 0 0 SDR HDR-DDR HDR-TSL HDR-TSP I2C SDR HDR-DDR HDR-TSL HDR-TSP I2C development project based on extensive collaboration I3C I3C mJ per Megabit, VDD=3.3 V Assumptions: 1 All symbols in each mode have equal probability for use. with the MEMS and Sensors Industry Group and across the mJ per Megabit, VDD=1.8 V 2 Energy consumption is the energy delivered by pull-up broader electronics ecosystem. devices to the bus (which includes drivers and resistors) 2 As shown in Figure 1, I C-bus targets (with 50 ns filter) Figure 2 - Comparison of Energy Consumption and Data Rates: can coexist with I3C controllers operating at 12.5 MHz, I3C vs I2C enabling the migration of existing I2C-bus designs to the I3C Additional technical highlights for I3C include multi- specification. Conversely, I3C targets operating at typical controller support, dynamic addressing, command-code 400 kHz or 1 MHz I2C-bus speeds can coexist with existing compatibility and a uniform approach for advanced power I2C-bus controllers. management features, such as sleep mode. It provides Interrupt synchronous and asynchronous timestamping to improve the accuracy of applications that fuse signals from various I3C I2C I3C Target 1 Target 1 Target 4 peripherals. It can also batch and transmit data quickly to I3C minimize energy consumption of the host processor. Controller I3C I3C I2C SoC Target 2 Target 3 Target 2 Figure 1 – I2C and I3C targets coexisting with I3C controller Just like I2C, I3C is implemented with standard CMOS I/O pins using a two-wire interface, but unlike I2C it supports in-band interrupts enabling target devices to notify controllers of interrupts, a design feature that eliminates the need for a separate general-purpose input/output (GPIO) interrupt for each target, reducing system cost and complexity. Support for dynamic address assignments help minimize pin counts, which is key for accommodating space- constrained form factors. I3C supports a multi-drop bus that, at 12.5MHz, supports standard data rate (SDR) of 10 Mbps with options for high- data-rate (HDR) modes. The net result is that I3C offers a leap in performance and power efficiency compared with I2C as shown in Figure 2. www.nxp.com 3 COMPARISON OF FEATURES While the full version of I3C is available only to MIPI Alliance Feature I3C I3C I3C I3C Basic members, MIPI has released a public version called I3C v1.0 Basic v1.1 v1.1 Basic that bundles the most commonly needed I3C features 12.5 MHz SDR (Controller, for use by developers and other standards organizations. Target and Legacy I2C Target √ √ √ √ I3C Basic is available for implementation without MIPI Compatibility) membership and is intended to facilitate a royalty-free Target can operate as I2C device on I2C bus and on I3C bus using √ √ √ √ licensing environment for all implementers. Figure 3 HDR modes summarizes the key features supported by I3C and I3C Target Reset √ √ √ √ Basic. Specified 1.2V-3.3V Operation for √ √ √ √ 50pf C load To support developers, compatibility between different In-Band Interrupt (w/MDB) √ √ √ √ I3C implementations has been confirmed through multiple Dynamic Address Assignment √ √ √ √ interoperability workshops, and several supporting MIPI Error Detection and Recovery √ √ √ √ resources are available. These include: Secondary Controller √ √ √ √ • I3C Host Controller Interface – MIPI I3C HCISM Hot-Join Mechanism √ √ √ √ Common Command Codes • I3C HCI Driver for Linux √ √ √ √ √ √ (Required/Optional) • I3C Discovery and Configuration Specification – DisCo for Specified 1.0V Operation for 100pf √ √ √ √ SM C load I3C Set Static Address as Dynamic SM √ √ √ √ • I3C Debug and Test Interface – MIPI Debug for I3C Address CCC (SETAASA) Synchronous Timing Control √ √ √ √ I3C intellectual property (IP) is available from multiple Asynchronous Timing Control vendors, including a licence free version for I3C Basic. I3C √ √ √ √ (Mode 0) conformance testing and verification IP test suites are also Asynchronous Timing Control √ √ √ √ available from multiple vendors. (Mode 1-3) HDR-DDR √ √ √ √ More information on I3C and I3C Basic is available via the HDR-TSL/TSP √ √ √ MIPI Alliance website. HDR-BT (Multi-Lane Bulk Transport) √ √ √ √ Grouped Addressing √ √ √ √ Device to Device(s) Tunneling √ √ √ √ Multi-Lane for Speed (Dual/Quad √ √ √ √ for SDR and HDR-DDR) Monitoring Device Early √ √ √ √ Termination Figure 3 - Comparison of I3C and I3C Basic Features 4 www.nxp.com OVERVIEW OF THE SPI BUS SCLK SCLK SPI is the full duplex synchronous serial interface consisting MOSI MOSI SPI of four signals: SCLK (serial clock), MOSI (master out, slave SPI MISO MISO Target Controller in), MISO (master in, slave out) and SS (slave select). SPI bus SS SS operates with a single controller (master) device and one or more target (slave) devices. Data rate ranges from 5 to 20 SCLK MOSI SPI 2 Mbps which is much higher than the I C-bus rate but like MISO Target the new I3C-bus. SS SCLK SCLK SCLK MOSI SPI SPI MOSI MOSI SPI MISO Target Controller MISO MISO Target SS SS SS Alternatively, targets could be connected in a daisy chain Though target devices might operate in one polarity or configuration to reduce number of the target select signals. phase only, clock polarity and phase of the SPI bus could The controller output is connected to the first target input. be configured with respect to the data to establish the valid The first target output is connected to the second target communication link by the controller. CPOL determines the input and so on. Then the last target output is connected polarity of the clock. When CPOL = 0, clock is low when back to the controller input. Each target is designed to idle. The leading edge is the rising edge and the trailing send out during the second group of the clock pulses the edge is the falling edge. When CPOL = 1, clock is high exact copy of the data it received during the first group of when idle. The leading edge is the failing edge and the clock pulses. The master receives data from the last target trailing edge is the rising edge. first then data from the first target last during the same CPHA determines the timing of the data bits relative to the clock group. It requires two clock groups to complete each clock pulse. When CPHA = 1, the transmitting side changes operation which would be only one clock group in the data on the leading edge of the clock and the receiving parallel configuration side captures data on the trailing edge of the clock. When CPHA = 0, the transmitting side changes data on the CPOL=0 SCK CPOL=1 trailing edge of the clock and the receiving side captures data on the leading edge of the clock. SS 1 2 3 4 5 6 7 8 SCLK SCLK Cycle # MOSI MOSI SPI CPHA=0 MISO Z 1 2 3 4 5 6 7 8 Z SPI MISO MISO Target MOSI Z 1 2 3 4 5 6 7 8 Z Controller SS1 SS SS2 Cycle # 1 2 3 4 5 6 7 8 SS3 SCLK MISO Z 1 2 3 4 5 6 7 8 Z MOSI SPI CPHA=1 MISO Target MOSI Z 1 2 3 4 5 6 7 8 Z SS SCLK MOSI SPI MISO Target SS The controller could connect with multiple independent targets in parallel.