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Systemverilog 3.0 Accellera's Extensions to Verilog SystemVerilog 3.0 Accellera’s Extensions to Verilog® Abstract: a set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language to aid in the creation and verification of abstract architectural level models SystemVerilog 3.0 Accellera’s Extensions to Verilog® Abstract: a set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language to aid in the creation and verification of abstract architectural level models Approved by the Accellera Board of Directors on 3 June 2002. Copyright © 2002 by Accellera Organization, Inc. 1370 Trancas Street #163 Napa, CA 94558 Phone: (707) 251-9977 Fax: (707) 251-9877 All rights reserved. No part of this document may be reproduced or distributed in any medium what- soever to any third parties without prior written consent of Accellera Organization, Inc. Accellera SystemVerilog 3.0 Extensions to Verilog-2001 Verilog is a registered trademark of Cadence Design Systems, San Jose, CA ii Copyright 2002 Accellera. All rights reserved. Accellera Extensions to Verilog-2001 SystemVerilog 3.0 Acknowledgements This SystemVerilog 3.0 reference manual was developed by experts from many different fields, including design and verification engineers, Electronic Design Automation (EDA) companies, EDA vendors, and mem- bers of the IEEE 1364 Verilog standard working group. The primary contributors to the development of Sys- temVerilog 3.0 include: Vassilios Gerousis, Chair Dave Kelf, Co-chair Stefen Boyd Dennis Brophy Kevin Cameron Cliff Cummings Simon Davidmann Tom Fitzpatrick Peter Flake Harry Foster Paul Graham David Knapp Adam Krolnik Mike McNamara Phil Moorby Prakash Narian Anders Nordstrom Rajeev Ranjan John Sanguinetti David Smith Alec Stanculescu Stuart Sutherland Bassam Tabbara Andy Tsay Stuart Sutherland served at the technical editor for this document. Stefen Boyd served as editor of the BNF annex. Copyright 2002 Accellera. All rights reserved. iii Accellera SystemVerilog 3.0 Extensions to Verilog-2001 iv Copyright 2002 Accellera. All rights reserved. Accellera Extensions to Verilog-2001 SystemVerilog 3.0 Table of Contents Section 1 Introduction to SystemVerilog ...................................................................................................... 1 Section 2 Literal Values.................................................................................................................................. 2 2.1 Introduction (informative) .................................................................................................................. 2 2.2 Literal value syntax............................................................................................................................. 2 2.3 Integer and logic literals ..................................................................................................................... 3 2.4 Real literals ......................................................................................................................................... 3 2.5 Time literals ........................................................................................................................................ 3 2.6 String literals....................................................................................................................................... 3 2.7 Array literals ....................................................................................................................................... 3 2.8 Structure literals.................................................................................................................................. 4 Section 3 Data Types....................................................................................................................................... 5 3.1 Introduction (informative) .................................................................................................................. 5 3.2 Data type syntax.................................................................................................................................. 6 3.3 Integer data types ................................................................................................................................ 6 3.4 Other basic data types......................................................................................................................... 7 3.5 User-defined types .............................................................................................................................. 8 3.6 Enumerations ...................................................................................................................................... 8 3.7 Structures and Unions....................................................................................................................... 10 3.8 Casting .............................................................................................................................................. 12 Section 4 Arrays ............................................................................................................................................ 14 4.1 Introduction (informative) ................................................................................................................ 14 4.2 Packed and unpacked arrays ............................................................................................................. 14 4.3 Multiple dimensions ......................................................................................................................... 15 4.4 Indexing and slicing of arrays........................................................................................................... 16 4.5 Array querying functions .................................................................................................................. 17 Section 5 Data Declarations ......................................................................................................................... 18 5.1 Introduction (informative) ................................................................................................................ 18 5.2 Data declaration syntax..................................................................................................................... 18 5.3 Constants........................................................................................................................................... 18 5.4 Variables ........................................................................................................................................... 19 5.5 Scope and lifetime ............................................................................................................................ 19 5.6 Nets, regs, and logic.......................................................................................................................... 20 Section 6 Attributes....................................................................................................................................... 21 6.1 Introduction (informative) ................................................................................................................ 21 6.2 Attribute syntax for interfaces .......................................................................................................... 21 Section 7 Operators and Expressions.......................................................................................................... 22 7.1 Introduction (informative) ................................................................................................................ 22 7.2 Operator syntax................................................................................................................................. 22 7.3 Assignment, incrementor and decrementor operations..................................................................... 22 7.4 Operations on logic and bit types ..................................................................................................... 23 7.5 Real operators ................................................................................................................................... 23 7.6 Size.................................................................................................................................................... 23 7.7 Sign ................................................................................................................................................... 23 7.8 Operator precedence and associativity ............................................................................................. 23 7.9 Concatenation ................................................................................................................................... 24 Copyright 2002 Accellera. All rights reserved. v Accellera SystemVerilog 3.0 Extensions to Verilog-2001 Section 8 Procedural Statements and Control Flow.................................................................................. 25 8.1 Introduction (informative) ................................................................................................................ 25 8.2 Blocking and nonblocking assignments ........................................................................................... 26 8.3 Selection statements.......................................................................................................................... 27 8.4 Loop statements
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