R

Intel® 815E Chipset Platform

For Use with Universal Socket 370

Design Guide

September 2002

Document Number: 298350-002

R

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel 815E chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM.

Intel, Celeron, Pentium, and MMX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright© 2001-2002, Intel Corporation

2 Intel® 815E Chipset Platform Design Guide

R

Contents

1 Introduction...... 15 1.1 Terminology ...... 16 1.2 Reference Documents ...... 18 1.3 System Overview ...... 19 1.3.1 System Features ...... 20 1.3.2 Component Features...... 21 1.3.2.1 Intel® 82815 GMCH Features ...... 21 1.3.2.2 Intel® 82801BA I/O Controller Hub 2 (ICH2) ...... 22 1.3.2.3 Firmware Hub (FWH)...... 23 1.3.3 Platform Initiatives ...... 23 1.3.3.1 Universal Motherboard Design ...... 23 1.3.3.2 Intel® PC 133...... 23 1.3.3.3 Accelerated Hub Architecture Interface ...... 23 1.3.3.4 Internet Streaming SIMD Extensions...... 23 1.3.3.5 AGP 2.0...... 24 1.3.3.6 Integrated LAN Controller ...... 24 1.3.3.7 Ultra ATA/100 Support...... 24 1.3.3.8 Expanded USB Support...... 24 1.3.3.9 Manageability and Other Enhancements...... 24 1.3.3.10 AC’97 6-Channel Support ...... 25 1.3.3.11 Low-Pin-Count (LPC) Interface...... 27 2 General Design Considerations...... 29 2.1 Nominal Board Stack-up...... 29 2.2 Electrostatic Discharge Platform Recommendations ...... 30 3 Component Layouts...... 33

4 Universal Motherboard Design ...... 37 4.1 Universal Motherboard Definition Details...... 37 4.2 Processor Design Requirements ...... 39 4.2.1 Use of Universal Motherboard Design With Incompatible GMCH ...... 39 4.2.2 Identifying the Processor at the Socket...... 40 4.2.3 Setting the Appropriate Processor VTT Level...... 41 4.2.4 VTT Processor Pin AG1...... 42 4.2.5 Identifying the Processor at the GMCH...... 43 4.2.6 Configuring Non-VTT Processor Pins ...... 44 4.2.7 VCMOS Reference...... 45 4.2.8 Processor Signal PWRGOOD...... 46 4.2.9 APIC Clock Voltage Switching Requirements ...... 47 4.2.10 GTLREF Topology and Layout...... 48 4.2.11 P-MOS Kicker “ON” Support ...... 49 4.3 Power Sequencing on Wake Events ...... 49 4.3.1 Gating of Intel® CK-815 to VTTPWRGD ...... 50 4.3.2 Gating of PWROK to ICH2...... 51 5 System Bus Design Guidelines ...... 53

Intel® 815E Chipset Platform Design Guide 3

R

5.1 System Bus Routing Guidelines ...... 53 5.1.1 Initial Timing Analysis...... 53 5.2 General Topology and Layout Guidelines...... 56 5.2.1 Motherboard Layout Rules for AGTL/AGTL+ Signals ...... 57 5.2.1.1 Motherboard Layout Rules for Non-AGTL/AGTL+ (CMOS) Signals ...... 59 5.2.1.2 THRMDP and THRMDN...... 60 5.2.1.3 Additional Routing and Placement Considerations...... 60 5.3 Electrical Differences for Universal PGA370 Designs ...... 61 5.3.1 THERMTRIP Circuit ...... 61 5.3.1.1 THERMTRIP Timing ...... 62 5.3.1.2 THERMTRIP Support for Tualatin A-1 Stepping...... 62 5.4 PGA370 Socket Definition Details ...... 63 5.5 BSEL[1:0] Implementation Differences...... 67 5.6 CLKREF Circuit Implementation...... 68 5.7 Undershoot/Overshoot Requirements ...... 68 5.8 Processor Reset Requirements...... 69 5.9 Processor PLL Filter Recommendations ...... 70 5.9.1 Topology...... 70 5.9.2 Filter Specification ...... 70 5.9.3 Recommendation for Intel Platforms...... 72 5.9.4 Custom Solutions ...... 73 5.10 Voltage Regulation Guidelines...... 74 5.11 Decoupling Guidelines for Universal PGA370 Designs ...... 74 5.11.1 VCCCORE Decoupling Design...... 74 5.11.2 VTT Decoupling Design ...... 75 5.11.3 VREF Decoupling Design...... 75 5.12 Thermal Considerations...... 76 5.12.1 Heatsink Volumetric Keepout Regions...... 76 5.13 Debug Port Changes ...... 78 6 System Memory Design Guidelines...... 79 6.1 System Memory Routing Guidelines...... 79 6.2 System Memory 2-DIMM Design Guidelines ...... 80 6.2.1 System Memory 2-DIMM Connectivity ...... 80 6.2.2 System Memory 2-DIMM Layout Guidelines ...... 81 6.3 System Memory 3-DIMM Design Guidelines ...... 83 6.3.1 System Memory 3-DIMM Connectivity ...... 83 6.3.2 System Memory 3-DIMM Layout Guidelines ...... 84 6.4 System Memory Decoupling Guidelines ...... 85 6.5 Compensation...... 86 7 AGP/Display Cache Design Guidelines...... 87 7.1 AGP Interface ...... 87 7.1.1 Graphics Performance Accelerator (GPA)...... 88 7.1.2 AGP Universal Retention Mechanism (RM)...... 88 7.2 AGP 2.0 ...... 90 7.2.1 AGP Interface Signal Groups ...... 91 7.3 Standard AGP Routing Guidelines ...... 92 7.3.1 1X Timing Domain Routing Guidelines ...... 92 7.3.1.1 Flexible Motherboard Guidelines ...... 92

4 Intel® 815E Chipset Platform Design Guide

R

7.3.1.2 AGP-Only Motherboard Guidelines...... 92 7.3.2 2X/4X Timing Domain Routing Guidelines...... 92 7.3.2.1 Flexible Motherboard Guidelines ...... 93 7.3.2.2 AGP-Only Motherboard Guidelines...... 94 7.3.3 AGP Routing Guideline Considerations and Summary...... 95 7.3.4 AGP Clock Routing ...... 96 7.3.5 AGP Signal Noise Decoupling Guidelines...... 96 7.3.6 AGP Routing Ground Reference...... 97 7.4 AGP Down Routing Guidelines...... 98 7.4.1 1X AGP Down Option Timing Domain Routing Guidelines...... 98 7.4.2 2X/4X AGP Down Timing Domain Routing Guidelines ...... 98 7.4.3 AGP Routing Guideline Considerations and Summary...... 99 7.4.4 AGP Clock Routing ...... 100 7.4.5 AGP Signal Noise Decoupling Guidelines...... 100 7.4.6 AGP Routing Ground Reference...... 101 7.5 AGP 2.0 Power Delivery Guidelines ...... 101 7.5.1 VDDQ Generation and TYPEDET#...... 101 7.5.2 VREF Generation for AGP 2.0 (2X and 4X)...... 103 7.6 Additional AGP Design Guidelines...... 105 7.6.1 Compensation ...... 105 7.6.2 AGP Pull-ups...... 105 7.6.2.1 AGP Signal Voltage Tolerance List...... 106 7.7 Motherboard / Add-in Card Interoperability...... 106 7.8 AGP / Display Cache Shared Interface...... 107 7.8.1 GPA Card Considerations ...... 107 7.8.1.1 AGP and GPA Mechanical Considerations...... 107 7.8.2 Display Cache Clocking...... 108 7.9 Designs That Do Not Use the AGP Port...... 108 8 Integrated Graphics Display Output...... 109 8.1 Analog RGB/CRT...... 109 8.1.1 RAMDAC/Display Interface ...... 109 8.1.2 Reference Resistor (Rset) Calculation...... 111 8.1.3 RAMDAC Board Design Guidelines ...... 111 8.1.4 RAMDAC Layout Recommendations ...... 113 8.1.5 HSYNC/VSYNC Output Guidelines...... 113 8.2 Digital Video Out ...... 114 8.2.1 DVO Interface Routing Guidelines ...... 114 8.2.2 DVO I2C Interface Considerations...... 114 8.2.3 Leaving the DVO Port Unconnected ...... 114 9 Hub Interface ...... 115 9.1.1 Data Signals ...... 116 9.1.2 Strobe Signals ...... 116 9.1.3 HREF Generation/Distribution...... 116 9.1.4 Compensation ...... 117 10 I/O Controller Hub 2 (ICH2) ...... 119 10.1 Decoupling ...... 119 10.2 1.85V/3.3V Power Sequencing ...... 120 10.3 Power Sequencing on Wake Events ...... 121 10.4 Power Plane Splits...... 122

Intel® 815E Chipset Platform Design Guide 5

R

10.5 Power Supply PS_ON Considerations...... 122 11 I/O Subsystem ...... 123 11.1 IDE Interface ...... 123 11.1.1 Cabling ...... 123 11.2 Cable Detection for Ultra ATA/66 and Ultra ATA/100...... 123 11.2.1 Combination Host-Side/Device-Side Cable Detection ...... 124 11.2.2 Device-Side Cable Detection...... 125 11.2.3 Primary IDE Connector Requirements...... 126 11.2.4 Secondary IDE Connector Requirements ...... 127 11.3 AC’97 ...... 128 11.3.1 Communications Network Riser (CNR)...... 129 11.3.2 AC’97 Audio Codec Detect Circuit and Configuration Options...... 130 11.3.2.1 Valid Codec Configurations ...... 133 11.3.3 SPKR Pin Considerations...... 133 11.3.4 AC’97 Routing ...... 134 11.3.5 Motherboard Implementation ...... 135 11.4 USB...... 135 11.4.1 Using Native USB Interface...... 135 11.4.2 Disabling the Native USB Interface of ICH2...... 136 11.5 IOAPIC Design Recommendation ...... 137 11.5.1 PIRQ Routing Example ...... 137 11.6 SMBus/SMLink Interface ...... 138 11.6.1 SMBus Architecture & Design Considerations ...... 139 11.6.1.1 General Design Issues and Notes ...... 140 11.7 PCI ...... 142 11.8 RTC...... 142 11.8.1 RTC Crystal...... 142 11.8.2 External Capacitors ...... 143 11.8.3 RTC Layout Considerations ...... 143 11.8.4 RTC External Battery Connection ...... 144 11.8.5 RTC External RTCRST Circuit...... 145 11.8.6 Power-Well Isolation Control...... 145 11.8.7 RTC Routing Guidelines...... 146 11.8.8 VBIAS DC Voltage and Noise Measurements ...... 146 11.9 LAN Layout Guidelines ...... 147 11.9.1 ICH2 – LAN Interconnect Guidelines ...... 148 11.9.1.1 Bus Topologies ...... 149 11.9.1.2 Point-to-Point Interconnect ...... 149 11.9.1.3 LOM/CNR Interconnect...... 150 11.9.1.4 Signal Routing and Layout ...... 150 11.9.1.5 Crosstalk Consideration...... 151 11.9.1.6 Impedances ...... 151 11.9.1.7 Line Termination ...... 151 11.9.2 General LAN Routing Guidelines and Considerations ...... 152 11.9.2.1 General Trace Routing Considerations...... 152 11.9.2.2 Power and Ground Connections...... 154 11.9.2.3 A 4-Layer Board Design...... 155 11.9.2.4 Common Physical Layout Issues...... 156 11.9.3 Intel® 82562EH Home/PNA* Guidelines...... 157 11.9.3.1 Power and Ground Connections...... 157 11.9.3.2 Guidelines for Intel® 82562EH Component Placement...... 157

6 Intel® 815E Chipset Platform Design Guide

R

11.9.3.3 Crystals and Oscillators ...... 158 11.9.3.4 Phoneline HPNA Termination ...... 158 11.9.3.5 Critical Dimensions ...... 159 11.9.4 Intel® 82562ET / Intel® 82562EM Guidelines ...... 160 11.9.4.1 Guidelines for Intel® 82562ET / Intel® 82562EM Component Placement ...... 160 11.9.4.2 Crystals and Oscillators ...... 161 11.9.4.3 Intel® 82562ET / Intel® 82562EM Termination Resistors...161 11.9.4.4 Critical Dimensions ...... 162 11.9.4.5 Reducing Circuit Inductance ...... 163 11.9.5 Intel® 82562ET/82562EM Disable Guidelines...... 164 11.9.6 Intel® 82562ET / Intel® 82562EH Dual Footprint Guidelines ...... 165 11.10 LPC/FWH...... 167 11.10.1 In-Circuit FWH Programming...... 167 11.10.2 FWH VPP Design Guidelines ...... 167 11.10.3 FWH Decoupling ...... 168 12 Clocking...... 169 12.1 2-DIMM Clocking ...... 169 12.2 3-DIMM Clocking ...... 171 12.3 Clock Routing Guidelines...... 173 12.4 Clock Driver Frequency Strapping ...... 175 12.5 Clock Skew Assumptions ...... 176 12.6 Intel® CK-815 Power Gating On Wake Events ...... 177 13 Power Delivery...... 179 13.1 Thermal Design Power ...... 182 13.1.1 Pull-Up and Pull-Down Resistor Values ...... 183 13.2 ATX Power Supply PWRGOOD Requirements...... 183 13.3 Power Management Signals ...... 184 13.3.1 Power Button Implementation ...... 185 13.3.2 1.85V/3.3V Power Sequencing...... 186 13.3.3 3.3V/V5REF Sequencing...... 187 13.4 Power Plane Splits...... 188 13.5 Glue Chip 3 (ICH2 Glue Chip) ...... 189 14 System Design Checklist...... 191 14.1 Design Review Checklist ...... 191 14.2 Processor Checklist ...... 191 14.2.1 GTL Checklist...... 191 14.2.2 CMOS Checklist ...... 192 14.2.3 TAP Checklist for 370-Pin Socket Processors...... 192 14.2.4 Miscellaneous Checklist for 370-Pin Socket Processors ...... 193 14.3 GMCH Checklist ...... 194 14.3.1 AGP Interface 1X Mode Checklist...... 194 14.3.2 Designs That Do Not Use the AGP Port ...... 195 14.3.3 System Memory Interface Checklist...... 195 14.3.4 Hub Interface Checklist ...... 196 14.3.5 Digital Video Output Port Checklist ...... 196 14.4 ICH2 Checklist ...... 196 14.4.1 PCI Interface ...... 196

Intel® 815E Chipset Platform Design Guide 7

R

14.4.2 Hub Interface...... 197 14.4.3 LAN Interface ...... 197 14.4.4 EEPROM Interface...... 197 14.4.5 FWH/LPC Interface ...... 197 14.4.6 Interrupt Interface ...... 198 14.4.7 GPIO Checklist...... 199 14.4.8 USB ...... 199 14.4.9 Power Management ...... 200 14.4.10 Processor Signals ...... 201 14.4.11 System Management ...... 201 14.4.12 RTC 201 14.4.13 AC’97 202 14.4.14 Miscellaneous Signals...... 203 14.4.15 Power 204 14.4.16 IDE Checklist...... 205 14.5 LPC Checklist ...... 207 14.6 System Checklist ...... 208 14.7 FWH Checklist...... 208 14.8 Clock Synthesizer Checklist...... 209 14.9 System Memory Checklist ...... 210 14.10 Power Delivery Checklist ...... 210 15 Third-Party Vendor Information ...... 211

Appendix A: Customer Reference Board CRB) ...... 213

8 Intel® 815E Chipset Platform Design Guide

R

Figures

Figure 1. System Block Diagram ...... 20 Figure 2. Component Block Diagram ...... 21 Figure 3. AC'97 Audio and Modem Connections...... 26 Figure 4. Board Construction Example for 60 Ω Nominal Stack-up ...... 29 Figure 5. GMCH 544-Ball µBGA* CSP Quadrant Layout (Top View)...... 33 Figure 6. ICH2 360-Ball EBGA Quadrant Layout (Top View) ...... 34 Figure 7. Firmware Hub (FWH) Packages ...... 35 Figure 8. 0.13 Micron Socket 370 Processor Safeguard for Universal Motherboard Designs Using A-2 GMCH ...... 39 Figure 9. Processor Detect Mechanism at Socket/TUAL5 Generation Circuit...... 40 Figure 10. VTT Selection Switch ...... 41 Figure 11. Switching Pin AG1...... 42 Figure 12. Processor Identification Strap on GMCH ...... 43 Figure 13. VTTPWRGD Configuration Circuit...... 44 Figure 14. GTL_REF/VCMOS_REF Voltage Divider Network ...... 45 Figure 15. Resistor Divider Network for Processor PWRGOOD...... 46 Figure 16 Voltage Switch for Processor APIC Clock...... 47 Figure 17. GTLREF Circuit Topology ...... 48 Figure 18. Gating Power to Intel® CK-815 ...... 50 Figure 19 PWROK Gating Circuit For ICH2 ...... 51 Figure 20. Topology for 370-Pin Socket Designs with Single-Ended Termination (SET)..56 Figure 21. AGTL/AGTL+ Trace Routing...... 57 Figure 22. Routing for THRMDP and THRMDN...... 60 Figure 23. Example Implementation of THERMTRIP Circuit ...... 61 Figure 24. BSEL[1:0] Circuit Implementation for PGA370 Designs...... 67 Figure 25. Examples for CLKREF Divider Circuit...... 68 Figure 26. RESET#/RESET2# Routing Guidelines ...... 69 Figure 27. Filter Specification ...... 71 Figure 28. Example PLL Filter Using a Discrete Resistor ...... 73 Figure 29. Example PLL Filter Using a Buried Resistor ...... 73 Figure 30. Core Reference Model ...... 74 Figure 31. Capacitor Placement on the Motherboard...... 75 Figure 32. Heatsink Volumetric Keepout Regions...... 77 Figure 33. Motherboard Component Keepout Regions...... 77 Figure 34. TAP Connector Comparison ...... 78 Figure 35. System Memory Routing Guidelines ...... 79 Figure 36. System Memory Connectivity (2 DIMM) ...... 80 Figure 37. System Memory 2-DIMM Routing Topologies...... 81 Figure 38. System Memory Routing Example ...... 82 Figure 39. System Memory Connectivity (3 DIMM) ...... 83 Figure 40. System Memory 3-DIMM Routing Topologies...... 84 Figure 41. Intel 815 Chipset Platform Decoupling Example ...... 85 Figure 42. Intel® 815 Chipset Decoupling Example...... 86 Figure 43. AGP Left-Handed Retention Mechanism ...... 89 Figure 44. AGP Left-Handed Retention Mechanism Keepout Information...... 89 Figure 45. AGP 2X/4X Routing Example for Interfaces < 6 inches and GPA/AGP Solutions...... 93 Figure 46. AGP Decoupling Capacitor Placement Example ...... 97 Figure 47. AGP Down 2X/4X Routing Recommendations ...... 99 Figure 48. AGP VDDQ Generation Example Circuit ...... 102

Intel® 815E Chipset Platform Design Guide 9

R

Figure 49. AGP 2.0 VREF Generation and Distribution...... 104 Figure 50. Display Cache Input Clocking...... 108 Figure 51. Schematic of RAMDAC Video Interface...... 110 Figure 52. Cross-Sectional View of a Four-Layer Board ...... 111 Figure 53. Recommended RAMDAC Component Placement and Routing ...... 112 Figure 54. Recommended RAMDAC Reference Resistor Placement and Connections 113 Figure 55. Hub Interface Signal Routing Example ...... 115 Figure 56. Single Hub Interface Reference Divider Circuit...... 117 Figure 57. Locally Generated Hub Interface Reference Dividers ...... 117 Figure 58. ICH2 Decoupling Capacitor Layout ...... 120 Figure 59. 1.85V/3.3V Power Sequencing Circuit Example ...... 121 Figure 60. Power Plane Split Example ...... 122 Figure 61. Combination Host-Side / Device-Side IDE Cable Detection ...... 124 Figure 62. Device-Side IDE Cable Detection...... 125 Figure 63. Connection Requirements for Primary IDE Connector...... 126 Figure 64. Connection Requirements for Secondary IDE Connector...... 127 Figure 65. ICH2 AC’97– Codec Connection...... 128 Figure 66. CNR Interface...... 129 Figure 67. CDC_DN_ENAB# Support Circuitry for a Single Codec on Motherboard...... 130 Figure 68. CDC_DN_ENAB# Support Circuitry for Multi-Channel Audio Upgrade...... 131 Figure 69. CDC_DN_ENAB# Support Circuitry for Two-Codecs on Motherboard / One- Codec on CNR ...... 131 Figure 70. CDC_DN_ENAB# Support for Two-Codecs on Motherboard / Two-Codecs on CNR...... 132 Figure 71. Example Speaker Circuit...... 133 Figure 72. USB Data Signals...... 136 Figure 73. Example PIRQ Routing ...... 138 Figure 74. SMBus/SMLink Interface...... 139 Figure 75. Unified VCC_Suspend Architecture ...... 140 Figure 76. Unified VCCCORE Architecture...... 141 Figure 77. Mixed VCC_Suspend/VCCCORE Architecture ...... 141 Figure 78. PCI Bus Layout Example...... 142 Figure 79. External Circuitry for the ICH2 RTC ...... 143 Figure 80. Diode Circuit to Connect RTC External Battery...... 144 Figure 81. RTCRST External Circuit for ICH2 RTC ...... 145 Figure 82. ICH2 / LAN Connect Section...... 148 Figure 83. Single-Solution Interconnect...... 149 Figure 84. LOM/CNR Interconnect ...... 150 Figure 85. LAN_CLK Routing Example ...... 151 Figure 86. Trace Routing...... 153 Figure 87. Ground Plane Separation...... 154 Figure 88. Intel® 82562EH Termination...... 158 Figure 89. Critical Dimensions for Component Placement...... 159 Figure 90. Intel® 82562ET/Intel® 82562EM Termination ...... 161 Figure 91. Critical Dimensions for Component Placement...... 162 Figure 92. Termination Plane ...... 164 Figure 93. Intel® 82562ET/82562EM Disable Circuit...... 165 Figure 94. Dual-Footprint LAN Connect Interface ...... 166 Figure 95. Dual-Footprint Analog Interface ...... 166 Figure 96. FWH VPP Isolation Circuitry ...... 168 Figure 97. Platform Clock Architecture for a 2-DIMM Solution...... 170 Figure 98. Platform Clock Architecture for a 3-DIMM Solution...... 172 Figure 99. Clock Routing Topologies ...... 173 Figure 100. Power Delivery Map...... 180

10 Intel® 815E Chipset Platform Design Guide

R

Figure 101. Pull-Up Resistor Example ...... 183 Figure 102. Example 1.85V/3.3V Power Sequencing Circuit ...... 186 Figure 103. 3.3V/V5REF Sequencing Circuitry ...... 187 Figure 104. Power Plane Split Example ...... 188 Figure 105. USB Data Line Schematic...... 200 Figure 106. ICH2 Oscillator Circuitry ...... 202 Figure 107. SPKR Circuitry...... 203 Figure 108. V5REF Circuitry...... 204 Figure 109. Host/Device Side Detection Circuitry...... 206 Figure 110. Device Side Only Cable Detection ...... 206

Intel® 815E Chipset Platform Design Guide 11

R

Tables

Table 1. Processor Considerations for Universal Motherboard Design ...... 37 Table 2. GMCH Considerations for Universal Motherboard Design...... 38 Table 3. ICH2 Considerations for Universal Motherboard Design...... 38 Table 4. Clock Synthesizer Considerations for Universal Motherboard Design ...... 39 Table 5. Determining the Installed Processor via Hardware Mechanisms ...... 43 Table 6. Intel® Pentium® III Processor AGTL/AGTL+ Parameters for Example Calculations...... 54 Table 7. Example TFLT_MAX Calculations for 133 MHz Bus ...... 55 Table 8. Example TFLT_MIN Calculations (Frequency Independent) ...... 55 Table 9. Trace Guidelines for Figure 20...... 56 Table 10. Trace Width:Space Guidelines...... 56 Table 11. Routing Guidelines for Non-AGTL/AGTL+ Signals ...... 59 Table 12. Processor Pin Definition Comparison...... 63 Table 13. Resistor Values for CLKREF Divider (3.3V Source)...... 68 Table 14. RESET#/RESET2# Routing Guidelines ...... 69 Table 15. Component Recommendations – Inductor...... 72 Table 16. Component Recommendations – Capacitor ...... 72 Table 17. Component Recommendation – Resistor ...... 72 Table 18. System Memory 2-DIMM Solution Space...... 81 Table 19. System Memory 3-DIMM Solution Space...... 84 Table 20. Retention Mechanism Vendors ...... 90 Table 21. AGP 2.0 Signal Groups ...... 91 Table 22. AGP 2.0 Data/Strobe Associations...... 91 Table 23. AGP 2.0 Routing Summary ...... 95 Table 24. AGP 2.0 Down Routing Summary...... 100 Table 25. TYPDET#/VDDQ Relationship ...... 102 Table 26. Connector/Add-in Card Interoperability ...... 106 Table 27. Voltage/Data Rate Interoperability...... 106 Table 28. Decoupling Capacitor Recommendation...... 119 Table 29. Signal Descriptions...... 132 Table 30. Codec Configurations ...... 133 Table 31. IOAPIC Interrupt Inputs 16 thru 23 Usage...... 137 Table 32. Pull-up Requirements for SMBus and SMLink ...... 139 Table 33. LAN Connect ...... 147 Table 34. Single-Solution Interconnect Length Requirements ...... 149 Table 35. LOM/CNR Length Requirements...... 150 Table 36. Critical Dimensions for Component Placement...... 159 Table 37. Critical Dimensions for Component Placement...... 162 Table 38. Intel® 82562ET Operating States...... 165 Table 39. Intel® CK-815 (2-DIMM) Clocks...... 169 Table 40. Intel® CK-815 (3-DIMM) Clocks...... 171 Table 41. Simulated Clock Routing Solution Space ...... 174 Table 42. Simulated Clock Skew Assumptions ...... 176 Table 43. Power Delivery Definitions...... 179 Table 44. Recommendations for Unused AGP Port...... 195

12 Intel® 815E Chipset Platform Design Guide

R

Revision History

Rev. No. Description Rev. Date

-001 • Initial Release. April 2001

-002 • Added Section 5.3.1.2, THERMTRIP Support for Tualatin A-1 Stepping August 2002 • Revised Checklist item RTCRST# in Section 14.4.12 • Revised Section 11.8.6, Power-Well Isolation Control. Added Figure 87. RTC – Power-well Isolation Control • Revised Table 39 and Table 40, in Section 12.1, 2-DIMM Clocking and Section 12.2, 3-DIMM Clocking • Revised Section 13.3.3, 3.3V/V5REF Sequencing • Added Section 2.2, Electrostatic Discharge Platform Recommendations • Replaced Figure 106, Power Delivery Map in Section 13 • Revised RSMRST# in Section 14.4.9, Power Management • Revised Packaging/Power bullet in Section 1.3.2.1 • Added Section 10.5, Power Supply PS_ON Considerations • Add SUSCLK to Section 14.4.12, RTC Checklist • Revised V5REF_SUS in Section 14.4.15, Power • Replaced Figure 92 in Section 11.9.2.1, General Trace Routing Considerations • Added Section 4.2.11, P-MOS Kicker “ON” Support

Intel® 815E Chipset Platform Design Guide 13

R

This page is intentionally left blank.

14 Intel® 815E Chipset Platform Design Guide

Introduction

R

1 Introduction

This design guide organizes Intel design recommendations for the Intel® 815E chipset platform for use with universal socket 370. In addition to providing motherboard design recommendations (e.g., layout and routing guidelines), this document also addresses system design issues (e.g., thermal requirements) for the chipset platform.

This design guide contains design recommendations, board schematics, debug recommendations, and a system checklist. These design guidelines are developed to ensure maximum flexibility for board designers while reducing the risk of board-related issues.

Board designers can use the schematics in Appendix A, “Customer Reference Board (CRB)” as a reference. While the included schematics cover specific designs, the core schematics will remain the same for most 815E chipset platforms that use the universal socket 370. Consult the debug recommendations when debugging your design. However, these debug recommendations should be understood before completing board design to ensure that the debug port, in addition to other debug features, are implemented correctly.

The 815E chipset platform supports the following processors: • Intel® Pentium® III processor based on 0.18 micron technology (CPUID = 068xh). • Intel® Celeron® processor based on 0.18 micron technology (CPUID = 068xh). This applies to Celeron 533A MHz and ≥566 MHz processors • 0.13 micron socket 370 processors

Note: The system bus speed supported by the design is based on the capabilities of the processor, chipset, and clock driver.

Note: The 815 chipset for use with the universal socket 370 is not compatible with the Intel® Pentium® II processor (CPUID = 066xh) 370-pin socket.

Intel® 815E Chipset Platform Design Guide 15

Introduction

R

1.1 Terminology

This section describes some of the terms used in this document. Additional power delivery term definitions are provided at the beginning of Chapter13, “Power Delivery”.

Term Description

AGP Accelerated Graphics Port

AGTL/AGTL+ Refers to processor bus signals that are implemented using either Assisted Gunning Transceiver Logic (AGTL+) or its lower voltage variant (AGTL), depending on which processor is being used.

Bus Agent A component or group of components that, when combined, represent a single load on the AGTL+ bus.

Crosstalk The reception on a victim network of a signal imposed by aggressor network(s) through inductive and capacitive coupling between the networks. • Backward Crosstalk–coupling that creates a signal in a victim network that travels in the opposite direction as the aggressor’s signal. • Forward Crosstalk–coupling that creates a signal in a victim network that travels in the same direction as the aggressor’s signal. • Even Mode Crosstalk–coupling from single or multiple aggressors when all the aggressors switch in the same direction that the victim is switching. • Odd Mode Crosstalk–coupling from single or multiple aggressors when all the aggressors switch in the opposite direction that the victim is switching.

GMCH Graphics and Memory Controller Hub. A component of the Intel® 815 chipset platform for use with the Universal Socket 370

Intel® ICH Intel® 82801AA I/O Controller Hub component.

ISI Inter-symbol interference is the effect of a previous signal (or transition) on the interconnect delay. For example, when a signal is transmitted down a line and the reflections due to the transition have not completely dissipated, the following data transition launched onto the bus is affected. ISI is dependent upon frequency, time delay of the line, and the reflection coefficient at the driver and receiver. ISI can impact both timing and signal integrity.

Network Length The distance between agent 0 pins and the agent pins at the far end of the bus.

Pad The electrical contact point of a semiconductor die to the package substrate. A pad is only observable in simulation.

Pin The contact point of a component package to the traces on a substrate such as the motherboard. Signal quality and timings can be measured at the pin.

Ringback The voltage that a signal rings back to after achieving its maximum absolute value. Ringback may be due to reflections, driver oscillations, or other transmission line phenomena.

Setup Window The time between the beginning of Setup to Clock (TSU_MIN) and the arrival of a valid clock edge. This window may be different for each type of bus agent in the system.

16 Intel® 815E Chipset Platform Design Guide

Introduction

R

Term Description

SSO Simultaneous Switching Output (SSO) Effects refers to the difference in electrical timing parameters and degradation in signal quality caused by multiple signal outputs simultaneously switching voltage levels (e.g., high-to-low) in the opposite direction from a single signal (e.g., low-to-high) or in the same direction (e.g., high- to-low). These are respectively called odd-mode switching and even-mode switching. This simultaneous switching of multiple outputs creates higher current swings that may cause additional propagation delay (or “push-out”), or a decrease in propagation delay (or “pull-in”). These SSO effects may impact the setup and/or hold times and are not always taken into account by simulations. System timing budgets should include margin for SSO effects.

Stub The branch from the bus trunk terminating at the pad of an agent.

System Bus The system bus is the processor bus.

Trunk The main connection, excluding interconnect branches, from one end agent pad to the other end agent pad.

Undershoot Minimum voltage observed for a signal to extend below VSS at the device pad.

Universal Socket 370 Refers to the 815E chipset using the “universal” PGA370 socket. In general, these designs support 66/100/133 MHz system bus operation, Intel® VRM guidelines for 0.13 micron processors, and Intel® Celeron® processors (CPUID=068xh), Intel® Pentium® III processor (CPUID=068xh), and future Pentium III processors in single- microprocessor based designs.

Victim A network that receives a coupled crosstalk signal from another network is called the victim network.

Intel® 815E Chipset Platform Design Guide 17

Introduction

R

1.2 Reference Documents

Document Document Number / Location

Intel® 815 Chipset Family: 82815 Graphics and Memory Controller Hub (GMCH) 298351 for use with the Universal Socket 370 Datasheet

Intel® 82802AB/82802AC Firmware Hub (FWH) Datasheet 290658

Intel® 82801BA I/O Controller Hub (ICH2) and Intel® 82801BAM I/O Controller 290687 Hub (ICH2-M) Datasheet

Intel® Pentium® III Processor Specification Update (latest revision from website) http://developer.intel.co m/design/PentiumIII/sp ecupdt/

AP 907 Intel® Pentium® III Processor Power Distribution Guidelines 245085

AP-585 Intel® Pentium® II Processor AGTL+ Guidelines 243330

AP-587 Intel® Pentium® II Processor Power Distribution Guidelines 243332

Accelerated Graphics Port Interface Specification, Revision 2.0

Graphics Performance Accelerator Specification ftp://download.intel.co m/technology/agp/dow nloads/agp20.pdf

PCI Local Bus Specification, Revision 2.2

AC ’97 2.1 Specification http://developer.intel.co m/pc- supp/platform/ac97/ind ex.htm.

82562EH HomePNA 1 Mb/s Physical Layer Interface Datasheet (Doc # 278313) http://developer.intel.co m

82562EH HomePNA 1 Mb/s Physical Layer Interface Brief Datasheet (Doc # 278314) http://developer.intel.co m

Communication Network Riser Specification, Revision 1.1 http://developer.intel.co m/technology/cnr/

Universal Serial Bus, Revision 1.0 Specification

18 Intel® 815E Chipset Platform Design Guide

Introduction

R

1.3 System Overview

The 815E chipset platform for use with the universal socket 370 contains a Graphics and Memory Controller Hub (GMCH) component and I/O Controller Hub 2 (ICH2) component for desktop platforms.

The GMCH provides the processor interface (optimized for the Pentium III processor (CPUID = 068xh) and 0.13 micron 370 socket processors), DRAM interface, hub interface, and an Accelerated Graphics Port (AGP) interface or internal graphics. This product provides flexibility and scalability in graphics and memory subsystem performance. Competitive internal graphics may be scaled via an AGP card interface, and PC100 SDRAM system memory may be scaled to PC133 system memory.

The Accelerated Hub Architecture interface (i.e., the chipset component interconnect) is designed into the chipset to provide an efficient, high-bandwidth communication channel between the GMCH and the I/O controller hub. The chipset architecture also enables a security and manageability infrastructure through the Firmware Hub component.

An ACPI-compliant 815E chipset platform can support the Full-on (S0), Stop Grant (S1), Suspend to RAM (S3), Suspend to Disk (S4), and Soft-off (S5) power management states. The chipset also supports wake-on-LAN* for remote administration and troubleshooting. The chipset architecture removes the requirement for the ISA expansion bus that was traditionally integrated into the I/O subsystem of PCIsets/AGPsets. This removes many of the conflicts experienced when installing hardware and drivers into legacy ISA systems. The elimination of ISA provides true plug-and-play for the platform. Traditionally, the ISA interface was used for audio and modem devices. The addition of AC ’97 allows the OEM to use software-configurable AC ’97 audio and modem coder/decoders (codecs), instead of the traditional ISA devices.

Intel® 815E Chipset Platform Design Guide 19

Introduction

R

1.3.1 System Features

The 815E chipset platform contains two components: the Intel® 82815 Graphics and Memory Controller Hub (GMCH) and the Intel® 82801BA I/O Controller Hub 2 (ICH2). The GMCH integrates a 66/100/133 MHz, P6 family system bus controller, integrated 2D/3D graphics accelerator or AGP (2X/4X) discrete graphics card, 100/133 MHz SDRAM controller, and a high- speed accelerated hub architecture interface for communication with the ICH2. The ICH2 integrates an UltraATA/100 controller, 2 Universal Serial Bus (USB) host controllers with a total of 4 ports, Low Pin Count (LPC) interface controller, Firmware Hub (FWH) interface controller, PCI interface controller, AC-link, integrated LAN controller, and a hub interface for communication with the GMCH.

Figure 1. System Block Diagram

Processor

66/100/133 MHz system bus

815E Chipset AGP graphics card or AGP 2X/4X display cache AIMM (AGP in-line memory module) 82815 B-0 GMCH 100/133 MHz Analog display out SDRAM Digital video out

Hub interface

4x USB PCI bus 2x IDE PCI slots

Audio codec AC97 82801BA ICH2

Modem codec LAN LPC I/F LAN connect connect KBC/SIO component

FWH Flash BIOS

Sys_Blk_815E_B0

20 Intel® 815E Chipset Platform Design Guide

Introduction

R

1.3.2 Component Features

Figure 2. Component Block Diagram

System bus (66/100/133 MHz)

Processor I/F SDRAM System 100/133 memory I/F MHz, 64 bit

Primary display AGP I/F GPA Overlay RAMDAC Monitor Data or AGP stream Digital 2X/4X H/W cursor FP / TVout control & video out card Local memory I/F dispatch 3D pipeline

2D (blit engine) Internal graphics

Hub I/F

Hub comp_blk_1

1.3.2.1 Intel® 82815 GMCH Features • Processor/System Bus Support  Optimized for Intel® Pentium® III processors at 133 MHz system bus frequency  Support for Intel® Celeron® processors (CPUID = 068xh) (66 MHz system bus)  Supports 32-bit AGTL or AGTL+ bus addressing  Supports uniprocessor systems  Utilizes AGTL and AGTL+ bus driver technology (gated AGTL/AGTL+ receivers for reduced power) • Integrated DRAM controller  32 MB to 512 MB using 16Mb/64Mb/128 Mb technology  Supports up to 3 double-sided DIMMS (6 rows)  100 MHz, 133 MHz SDRAM interface  64-bit data interface  Standard Synchronous DRAM (SDRAM) support (x-1-1-1 access)  Supports only 3.3V DIMM DRAM configurations  No registered DIMM support  Support for symmetrical and asymmetrical DRAM addressing  Support for x8, x16 DRAM device widths  Refresh mechanism: CAS-before-RAS only  Support for DIMM serial PD (presence detect) scheme via SMbus interface  Suspend-To-RAM (STR) power management support via self-refresh mode using CKE

Intel® 815E Chipset Platform Design Guide 21

Introduction

R

• Accelerated Graphics Port (AGP) Interface  Supports AGP 2.0, including 4X AGP data transfers, but not the 2X/4X Fast Write protocol  AGP universal connector support via dual-mode buffers to allow AGP 2.0 3.3V or 1.5V signaling  32-deep AGP request queue  AGP address translation mechanism with integrated fully associative 20-entry TLB  High-priority access support  Delayed transaction support for AGP reads that can not be serviced immediately  AGP semantic traffic to the DRAM not snooped on system bus and therefore not coherent with processor caches • Integrated Graphics Controller  Full 2D/3D/DirectX acceleration  Texture-mapped 3D with point sampled, bilinear, trilinear, and anisotropic filtering  Hardware setup with support for strips and fans  Hardware motion compensation assist for software MPEG/DVD decode  Digital Video Out interface for support of digital displays and TV-Out  PC99A/PC2001 compliant  Integrated 230 MHz DAC • Integrated Local Graphics Memory Controller (Display Cache)  0 MB to 4 MB (via Graphics Performance Accelerator) using zero, one or two parts  32-bit data interface  133 MHz memory clock  Supports ONLY 3.3V SDRAMs • Packaging/Power  544 BGA with local memory port  1.85 V core and mixed 3.3 V, 1.5 V, and AGTL+ IO. Note that the 82801BA ICH2 has a 1.8 V requirement and the 82815 GMCH has a 1.85V requirement. Instead of separate voltage regulators to meet these requirements, a single voltage regulator can be set to 1.795 V to 1.910 V. See Figure 100, Power Delivery Map. 1.3.2.2 Intel® 82801BA I/O Controller Hub 2 (ICH2) The Intel® I/O Controller Hub 2 allows the I/O subsystem to access the rest of the system, as follows: • Upstream accelerated hub architecture interface for access to the GMCH • PCI 2.2 interface (6 PCI Request/Grant pairs) • 2 channel Ultra ATA/100 Bus Master IDE controller • USB controller (Expanded capabilities for 4 ports) • I/O APIC • SMBus controller • FWH interface • LPC interface • AC ’97 2.1 interface • Integrated system management controller • Alert-on-LAN* • Integrated LAN controller • Packaging/Power

22 Intel® 815E Chipset Platform Design Guide

Introduction

R

 360 EBGA  1.8V (± 3% within margins of 1.795 V to 1.9 V) core and 3.3V standby

1.3.2.3 Firmware Hub (FWH)

The hardware features of the firmware hub include: • An integrated hardware Random Number Generator (RNG) • Register-based locking • Hardware-based locking • 5 General Purpose Interrupts (GPI) • Packaging/Power  40L TSOP and 32L PLCC  3.3V core and 3.3V / 12V for fast programming

1.3.3 Platform Initiatives

1.3.3.1 Universal Motherboard Design

The 815E chipset platform for use with the universal socket 370 allows systems designers to build one system that is compatible with the Pentium III processor (CPUID=068xh), Celeron processor (CPUID=068xh), and 0.13 micron socket 370 processors. When implemented, the 815E chipset universal socket 370 platform can detect which processor is present in the socket and function accordingly.

1.3.3.2 Intel® PC 133

The Intel® PC133 initiative provides the memory bandwidth necessary to obtain high performance from the processor and AGP graphics controller. The platform’s SDRAM interface supports 100 MHz and 133 MHz operation. The latter delivers 1.066 GB/s of theoretical memory bandwidth compared with the 800 MB/s theoretical memory bandwidth of 100 MHz SDRAM systems.

1.3.3.3 Accelerated Hub Architecture Interface

As I/O speeds increase, the demand placed on the PCI bus by the I/O bridge becomes significant. With the addition of AC ’97 and Ultra ATA/100, coupled with the existing USB, I/O requirements could impact PCI bus performance. The 815E platform’s accelerated hub architecture ensures that the I/O subsystem, both PCI and the integrated I/O features (IDE, AC ’97, USB, LAN), receives adequate bandwidth. By placing the I/O bridge on the accelerated hub architecture interface instead of PCI, I/O functions integrated into the ICH2 and the PCI peripherals are ensured the bandwidth necessary for peak performance.

1.3.3.4 Internet Streaming SIMD Extensions

The Pentium III processors provide 70 new SIMD (single instruction, multiple data) instructions. The new extensions are floating-point SIMD extensions. Intel® MMX™ technology provides integer SIMD instructions. The Internet Streaming SIMD extensions complement the MMX

Intel® 815E Chipset Platform Design Guide 23

Introduction

R

technology SIMD instructions and provide a performance boost to floating-point-intensive 3D applications.

1.3.3.5 AGP 2.0

The AGP 2.0 interface allows graphics controllers to access main memory at over 1 GB/s, twice the bandwidth of previous AGP platforms. AGP 2.0 provides the infrastructure necessary for photorealistic 3D. In conjunction with the Internet Streaming SIMD extensions, AGP 2.0 delivers the next level of 3D graphics performance.

1.3.3.6 Integrated LAN Controller

The 815E chipset platform incorporates an ICH2 integrated LAN Controller. Its bus master capabilities enable the component to process high-level commands and perform multiple operations; this lowers processor utilization by off-loading communication tasks from the processor.

The ICH2 functions with several options of LAN connect components to target the desired market segment. The Intel® 82562EH provides a HomePNA 1 Mbit/sec connection. The Intel® 82562ET provides a basic Ethernet 10/100 connection. The Intel® 82562EM provides an Ethernet 10/100 connection with the added flexibility of Alert on LAN. More advanced LAN solutions can be implemented with the Intel® 82550 or other PCI-based product offerings.

1.3.3.7 Ultra ATA/100 Support

The 815E chipset platform incorporates an IDE controller with two sets of interface signals (primary and secondary) that can be independently enabled, tri-stated or driven low. The component supports Ultra ATA/100, Ultra ATA/66, Ultra ATA/33, and multiword PIO modes for transfers up to 100 MB/sec.

1.3.3.8 Expanded USB Support

The 815E chipset platform contains two USB Host Controllers. Each Host Controller includes a root hub with two separate USB ports each, for a total of 4 USB ports. The addition of a second USB Host Controller expands the functionality of the platform.

1.3.3.9 Manageability and Other Enhancements

The 815E chipset platform integrates several functions designed to manage the system and lower the total cost of ownership (TCO) of the system. These system management functions are designed to report errors, diagnose the system, and recover from system lockups, without the aid of an external microcontroller.

SMBus

The ICH2 integrates an SMBus controller. The SMBus provides an interface for managing peripherals such as serial presence detection (SPD) and thermal sensors. The slave interface allows an external microcontroller to access system resources.

24 Intel® 815E Chipset Platform Design Guide

Introduction

R

Interrupt Controller

The interrupt capabilities of the platform expand support for up to 8 PCI interrupt pins and PCI 2.2 message-based interrupts. In addition, the ICH2 supports system bus interrupt delivery.

Firmware Hub (FWH)

The platform supports firmware hub BIOS memory sizes up to 8 MB for increased system flexibility.

1.3.3.10 AC ’97 6-Channel Support

The Audio Codec ’97 (AC ’97) Specification defines a digital interface that can be used to attach an audio codec (AC), a modem codec (MC), an audio/modem codec (AMC), or both an AC and an MC. The AC ’97 Specification defines the interface between the system logic and the audio or modem codec known as the AC-link.

The 815E chipset platform’s AC ’97 (with the appropriate codecs) not only replaces ISA audio and modem functionality, but also improves overall platform integration by incorporating the AC- link. Using the platform’s integrated AC-link reduces cost and eases migration from ISA.

By using an audio codec, the AC-link allows for cost-effective, high-quality, integrated audio. In addition, an AC ’97 soft modem can be implemented with the use of a modem codec. Several system options exist when implementing AC ’97. The 815E chipset platform’s integrated digital link allows several external codecs to be connected to the ICH2. The system designer can provide audio with an audio codec, a modem with a modem codec, or an integrated audio/modem codec (Figure 3c). The digital link is expanded to support two audio codecs (Figure 3a) or a combination of an audio and modem codec (Figure 3b).

Modem implementation for different countries must be taken into consideration, as telephone systems may vary. By implementing a split design, the audio codec can be on board, and the modem codec can be placed on a riser. Intel is developing an AC-link connector. With a single integrated codec, or AMC, both audio and modem can be routed to a connector near the rear panel where the external ports can be located.

The digital link in the ICH2 is AC ’97 Rev. 2.1 compliant, supporting two codecs with independent PCI functions for audio and modem. Microphone input and left and right audio channels are supported for a high-quality, two-speaker audio solution. Wake-on-ring-from-suspend also is supported with the appropriate modem codec.

The 815E chipset platform expands audio capability with support for up to six channels of PCM audio output (i.e., full AC3 decode). Six-channel audio consists of Front Left, Front Right, Back Left, Back Right, Center and Woofer, for a complete surround sound effect. ICH2 has expanded support for two audio codecs on the AC-link.

Intel® 815E Chipset Platform Design Guide 25

Introduction

R

Figure 3. AC '97 Audio and Modem Connections

a) AC'97 with Audio Codecs (4-Channel Secondary)

AC’97 Audio AC’97 Digital Codec ICH2 Link 360 EBGA Audio Port

AC’97 Audio Codec

Audio Port

b) AC'97 with Modem and Audio Codecs

Modem Port

AC’97 Modem AC’97 Digital Codec ICH2 Link 360 EBGA

AC’97 Audio Codec

Audio Port

c) AC'97 with Audio/Modem Codec Modem Port

AC’97 Digital ICH2 Link AC’97 360 EBGA Audio/ Modem Codec

Audio Port

AC97_connections

26 Intel® 815E Chipset Platform Design Guide

Introduction

R

1.3.3.11 Low-Pin-Count (LPC) Interface

In the 815E chipset platform, the Super I/O (SIO) component has migrated to the Low-Pin-Count (LPC) interface. Migration to the LPC interface allows for lower-cost Super I/O designs. The LPC Super I/O component requires the same feature set as traditional Super I/O components. It should include a keyboard and mouse controller, floppy disk controller, and serial and parallel ports. In addition to the Super I/O features, an integrated game port is recommended because the AC ’97 interface does not provide support for a game port. In systems with ISA audio, the game port typically existed on the audio card. The fifteen-pin game port connector provides for two joysticks and a two-wire MPU-401 MIDI interface. Consult your preferred Super I/O vendor for a comprehensive list of the devices offered and the features supported.

In addition, depending on system requirements, specific system I/O requirements may be integrated into the LPC Super I/O. For example, a USB hub may be integrated to connect to the ICH2 USB output and extend it to multiple USB connectors. Other SIO integration targets include a device bay controller or an ISA-IRQ-to-serial-IRQ converter to support a PCI-to-ISA bridge. Contact your Super I/O vendor to ensure the availability of desired LPC Super I/O features.

Intel® 815E Chipset Platform Design Guide 27

Introduction

R

This page is intentionally left blank.

28 Intel® 815E Chipset Platform Design Guide

General Design Considerations

R

2 General Design Considerations

This design guide provides motherboard layout and routing guidelines for systems based on the 815E chipset for use with the universal socket 370. The document does not discuss the functional aspects of any bus or the layout guidelines for an add-in device.

If the guidelines listed in this document are not followed, it is very important that thorough signal integrity and timing simulations be completed for each design. Even when the guidelines are followed, critical signals should be simulated to ensure the proper signal integrity and flight time. As bus speeds increase, it is imperative that the guidelines documented are followed precisely. Any deviation from these guidelines should be simulated.

The trace impedance typically noted (i.e., 60 Ω ± 15%) is the “nominal” trace impedance for a 5 mil-wide trace. That is, it is the impedance of the trace when not subjected to the fields created by changing current in neighboring traces. When calculating flight times, it is important to consider the minimum and maximum impedance of a trace, based on the switching of neighboring traces. The use of wider spaces between the traces can minimize this trace-to-trace coupling. In addition, these wider spaces reduce crosstalk and settling time.

Coupling between two traces is a function of the coupled length, the distance separating the traces, the signal edge rate, and the degree of mutual capacitance and inductance. To minimize the effects of trace-to-trace coupling, follow the routing guidelines documented in this section.

The routing guidelines in this design guide have been created using a PCB stack-up similar to that shown in Figure 4. If this stack-up is not used, extremely thorough simulations of every interface must be completed. Using a thicker dielectric (prepreg) will make routing very difficult or impossible.

2.1 Nominal Board Stack-up

The 815E chipset platform requires a board stack-up yielding a target impedance of 60 Ω ± 15% with a 5 mil nominal trace width. Figure 4 shows an example stack-up that achieves this. It is a 4- layer printed circuit board (PCB) construction using 53%-resin FR4 material.

Figure 4. Board Construction Example for 60 Ω Nominal Stack-up

Component-side layer 1: ½ oz. Cu 4.5-mil prepreg Power plane layer 2: 1 oz. Cu Total thickness: ~48-mil core 62 mils

Ground layer 3: 1 oz. Cu 4.5-mil prepreg Solder-side layer 4: ½ oz. Cu board_4.5mil_stackup

Intel® 815E Chipset Platform Design Guide 29

General Design Considerations

R

2.2 Electrostatic Discharge Platform Recommendations

Electrostatic discharge (ESD) into a system can lead to system instability, and possibly cause functional failures when a system is in use. There are system level design methodologies that when followed can lead to higher ESD immunity. Electromagnetic fields due to ESD are introduced into a system through chassis openings such as the I/O back panel and PCI slots. These fields can introduce noise into signals and cause the system to malfunction. One can reduce the potential for issues at the I/O area by adding more ground plane on the motherboard around the I/O area. This can lead to a higher ESD immunity.

Intel recommends that the I/O area on the top and bottom signal layers of a 4-layer motherboard near the I/O back panel be filled with a ground fill as shown in Figures 1-4. In addition, a ground fill cutout should be placed on the Vcc layer in the area where the ground fill is done on the top and bottom layers. Intel recommends filling the I/O area as much as possible without effecting the signal routing. The board designer should fill the entire I/O area along the board edge.

The spacing from the ground fill to other shapes/traces should be at least 20 mils. It is recommended that these ground fill areas be connected to two chassis mounting holes (as seen in Figure 2). This will allow ESD current to travel to the chassis instead of the board. Ground stitching vias should be placed throughout the entire ground fill if possible. It is important that the vias are placed along the board edge. Ground stitching vias for the ground fill should be 100-150 mils apart or less.

In conclusion, Intel recommends the following: 1. Fill the I/O area with the ground fill in all layers including signal layers whenever possible 2. Extend the ground fill along the entire back I/O area 3. Connect the ground fill to mounting holes 4. Place stitching vias 100-150 mils apart in the entire ground fill

Figure 5. Top Signal Layer before the Ground Fill Near the I/O Layer

30 Intel® 815E Chipset Platform Design Guide

General Design Considerations

R

Figure 6. Top Signal Layer after the Ground Fill Near the I/O Layer

Ground Fill

Figure 7. Bottom Signal Layer before The Ground Fill Near the I/O Area

Figure 8. Bottom Signal Layer after the Ground Fill Near the I/O

Ground Fill

Intel® 815E Chipset Platform Design Guide 31

General Design Considerations

R

This page is intentionally left blank.

32 Intel® 815E Chipset Platform Design Guide

Component Layouts

R

3 Component Layouts

Figure 9 illustrates the relative signal quadrant locations on the GMCH ballout. It does not represent the actual ballout. Refer to the Intel® 82815 Chipset Family: 82815 Graphics and Memory Controller Hub (GMCH) for use with the Universal Socket 370 Datasheet for the actual ballout.

Figure 9. GMCH 544-Ball µBGA* CSP Quadrant Layout (Top View)

Pin 1 corner System Memory Hub Interface

AGP / Display Cache GMCH

System Bus Video

Quad_GMCH

Intel® 815E Chipset Platform Design Guide 33

Component Layouts

R

Figure 10 illustrates the relative signal quadrant locations on the ICH2 ballout. It does not represent the actual ballout. Refer to the Intel® 82801BA I/O Controller Hub (ICH2) and Intel® 82801BAM I/O Controller Hub (ICH2-M) Datasheet for the actual ballout.

Figure 10. Intel® ICH2 360-Ball EBGA Quadrant Layout (Top View)

Hub interface Processor

IDE

LAN

ICH2

SM bus AC'97

PCI LPC USB

Quad_ICH2

34 Intel® 815E Chipset Platform Design Guide

Component Layouts

R

Figure 11. Firmware Hub (FWH) Packages

43 2 1 323130

1 40 2 39 5 29 3 38 4 37 6 28 5 36 6 35 7 27 7 34 FWH Interface 8 33 8 (32-Lead PLCC, 26 9 FWH Interface 32 0.450" x 0.550") 10 31 (40-Lead TSOP) 9 25 11 30 Top View 12 29 10 24 13 28 14 27 11 23 15 26 16 25 12 22 17 24 18 23 13 21 19 22 20 21

14 15 16 17 18 19 20

pck_fwh.vsd

Intel® 815E Chipset Platform Design Guide 35

Component Layouts

R

This page is intentionally left blank.

36 Intel® 815E Chipset Platform Design Guide

Universal Motherboard Design

R

4 Universal Motherboard Design

4.1 Universal Motherboard Definition Details

The universal socket 370 platform supports Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh) as well as 0.13 micron socket 370 processors. The Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh) have different requirements for functioning properly in a platform than socket 370 processors. It is necessary to understand these differences and how they affect the design of the platform. Refer to Table 1 through

Table 4 for a high-level description of the differences that require additional circuitry on the motherboard. Specific details on implementing this circuitry are discussed further in this chapter. For a detailed description of the differences between the Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh), and socket 370 processor pins, refer to Section 0.

Table 1. Processor Considerations for Universal Motherboard Design

Signal Function In Function In 0.13 Implementation for Name or Intel® Pentium® III micron Socket Universal Socket 370 Design Pin Processor 370 Processors Number (CPUID=068xh) and Intel® Celeron® Processor (CPUID=068xh)

AF36 VSS DETECT Addition of circuitry that generates a processor identification signal used to configure board-level operation.

AG1 VSS VTT Addition of FET switch to ground or VTT, controlled by processor identification signal. Note: FET must have no more than 100 milliohms resistance between source and drain.

AJ3 VSS RESET2# Addition of stuffing option for pull-down to ground, which lets designer prevent 0.13 micron socket 370 processors from being used with incompatible stepping of Intel® 82815 GMCH.

AK22 GTL_REF VCMOS_REF Addition of resistor-divider network to provide 1.0 V, which will satisfy voltage tolerance requirements of the Intel® Pentium® III processor (CPUID=068xh) and Intel® Celeron® processor (CPUID=068xh) as well as 0.13 micron socket 370 processors.

PICCLK Requires 2.5V Requires 2.0V Addition of FET switch to provide proper voltage, controlled by processor identification signal.

Intel® 815E Chipset Platform Design Guide 37

Universal Motherboard Design

R

Signal Function In Function In 0.13 Implementation for Name or Intel® Pentium® III micron Socket Universal Socket 370 Design Pin Processor 370 Processors Number (CPUID=068xh) and Intel® Celeron® Processor (CPUID=068xh)

PWRGOOD Requires 2.5V Requires 1.8V Addition of resistor-divider network to provide 2.1V, which will satisfy voltage tolerance requirements of the Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh) as well as 0.13 micron socket 370 processors.

VTT Requires 1.5V Requires 1.25V Modification to VTT generation circuit to switch between 1.5V or 1.25V, controlled by processor identification signal.

VTTPWRGD Not used Input signal to Addition of VTTPWRGD generation circuit. 0.13 micron socket 370 processors to indicate that VID signals are stable

Table 2. GMCH Considerations for Universal Motherboard Design

Pin Issue Implementation For Name/Number Universal Socket 370 Design

SMAA[12] New strap required for determining Addition of FET switch controlled by processor identification signal. Intel® Pentium® III Processor (CPUID=068xh) and Intel® Celeron® Processor (CPUID=068xh) or 0.13 micron socket 370 processors

Table 3. Intel® ICH2 Considerations for Universal Motherboard Design

Signal Issue Implementation For Universal Motherboard Design

PWROK GMCH and Intel® CK815 must not Addition of circuitry to have VTTPWRGD sample BSEL[1:0] until VTTPWRGD gate PWROK from power supply to ICH2. is asserted. The ICH2 must not The ICH2 will hold the GMCH in reset until initialize before the Intel CK815 VTTPWRGD asserted plus 20 ms time clocks stabilize. delay to allow Intel CK815 clocks to stabilize.

38 Intel® 815E Chipset Platform Design Guide

Universal Motherboard Design

R

Table 4. Clock Synthesizer Considerations for Universal Motherboard Design

Signal Issue Implementation For Universal Motherboard Design

VDD Intel® CK815 does not support Addition of FET switch that supplies power VTTPWRGD to VDD only when VTTPWRGD is asserted. Note: FET must have no more than 100 milliohms resistance between source and drain.

4.2 Processor Design Requirements

4.2.1 Use of Universal Motherboard Design With Incompatible GMCH

The universal socket 370 design is intended for use with the 815 chipset platform for use with the universal socket 370. A universal socket 370 design populated with an earlier stepping of the GMCH is not compatible with 0.13 micron socket 370 processors and, if used, will cause eventual failure of these processors. To prevent a 0.13 micron socket 370 processor from being used with an incompatible stepping of the GMCH, the recommendation is to lay out the site for a 0 Ω pull- down to ground on processor pin AJ3. This pin is a RESET# signal on 0.13 micron socket 370 processors and, by populating the resistor, these future processors will be prevented from functioning when placed in a board with an incompatible stepping of the GMCH. All Pentium III (CPUID=068xh) and Celeron (CPUID=068xh) processors will continue to boot normally. Not populating the resistor will allow 0.13 micron socket 370 processors to boot. Refer to Figure 12 for an example implementation.

Figure 12. 0.13 Micron Socket 370 Processor Safeguard for Universal Motherboard Designs Using A-2 GMCH

Future 0.13 Micron Socket 370 Processors

AJ3

0 Ω

Tual_pin_aj3

Intel® 815E Chipset Platform Design Guide 39

Universal Motherboard Design

R

4.2.2 Identifying the Processor at the Socket

For the platform to configure for the requirements of the processor in the socket, it must first identify whether the processor is a Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh), or a 0.13 micron socket 370 processors. Pin AF36 is a ground pin on a Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh); pin AF36 is an unconnected pin on 0.13 micron Socket 370 processors. Referring to Figure 13, the platform uses a detect circuit connected to this processor pin. If a 0.13 micron Socket 370 processor is present in the socket, the TUAL5 reference schematic signal will be pulled to the 5V rail and the TUAL5# reference schematic signal will be pulled to ground. Otherwise, for a Pentium III processor (CPUID=068xh) or Celeron processor (CPUID=068xh), the TUAL5 reference schematic signal will be pulled to ground and the TUAL5# will be pulled to the 5V rail.

Figure 13. Processor Detect Mechanism at Socket/TUAL5 Generation Circuit

VCC5

VCC5

VTT 2.2 KΩ

TUAL5 2.2 KΩ 1 KΩ MOSFET N

Processor Pin NPN AF36

TUAL5#

Proc_Detect_815E_B0

40 Intel® 815E Chipset Platform Design Guide

Universal Motherboard Design

R

4.2.3 Setting the Appropriate Processor VTT Level

Because the Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh), and 0.13 micron socket 370 processors require different VTT levels, the platform must be able to provide the appropriate voltage level after determining which processor is in the socket. Referring to Figure 14, the TUAL5 reference schematic signal serves to control the FET, and by doing so determines whether the voltage regulator supplies 1.25V or 1.5V to VTT for AGTL or AGTL+, respectively.

Figure 14. VTT Selection Switch

VCC3_3

LT1587-ADJ

Vout VTT Vin

ADJ 10 µ F 49.9 Ω 1% 22 µF Tantalum

0.1 µ F

MOSFET N 10 Ω TUAL5 1%

Vtt_Sel_Sw_815E_B0

Intel® 815E Chipset Platform Design Guide 41

Universal Motherboard Design

R

4.2.4 VTT Processor Pin AG1

Processor pin AG1 requires additional attention since it is a ground pin on a Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh) and a VTT pin on a 0.13 micron socket 370 processor. A separate switch controlled by the TUAL5 reference schematic signal determines whether pin AG1 is pulled to ground or VTT. Refer to Figure 15 for an example implementation.

Figure 15. Switching Pin AG1

VTT

TUAL5

Processor Pin AG1

Note: The FET must have no more than 100 milliohms resistance between the source and the drain. 1 KΩ

AG1_Switch_815E_B0

42 Intel® 815E Chipset Platform Design Guide

Universal Motherboard Design

R

4.2.5 Identifying the Processor at the GMCH

The GMCH determines whether the socket contains a 0.13 micron socket 370 processor or Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh) based on the input to pin SMAA12 on the GMCH. In a system using 0.13 micron socket 370 processors, SMAA12 will be pulled down during reset to indicate to the GMCH that a 0.13 micron socket 370 processor is in the socket. Refer to Figure 16. for an implementation example.

Figure 16. Processor Identification Strap on GMCH

SMAA[12]

10 KΩ

TUAL5

Proc_ID_Strap_815E_B0

Table 5 provides the logic decoding to determine which processor is installed in a PGA370 design.

Table 5. Determining the Installed Processor via Hardware Mechanisms

Processor Pin CPUPRES# Notes AF36

Hi-Z 0 0.13 micron socket 370 processor installed.

Low 0 Intel® Pentium® III processor (CPUID=068xh) or Intel® Celeron® processor (CPUID=068xh) installed.

X 1 No processor installed.

Intel® 815E Chipset Platform Design Guide 43

Universal Motherboard Design

R

4.2.6 Configuring Non-VTT Processor Pins

When asserted, the VTTPWGRD signal must be level-shifted to 12V to properly drive the gating circuitry of the Intel® CK815. Furthermore, while the VTTPWRGD signal is connected to the VTTPWRGD pin on a 0.13 micron socket 370 processor, on a Pentium III processor (CPUID=068xh) or Celeron processor (CPUID=068xh) that same pin is a ground. To provide proper functionality, a 1.0 kΩ resistor must be placed in series between the circuitry that generates the signal VTTPWRGD and the processor pin VTTPWRGD. Refer to Figure 17 for an example implementation. Voltage regulators that generate the standard VTTPWRGD signal are available.

Figure 17. VTTPWRGD Configuration Circuit

VCC12

VCC5 2.2 KΩ

3 VTTPWRGD12 BAT54C

VCC5 VTT

2 1

VCC5 MOSFET N ASSERTED VTTPWRGD V1_8SB LOW 1 KΩ

V1_8SB VCC5 1 KΩ 1 KΩ 20 KΩ MOSFET N 732 Ω 5 1% Vcc 8 IN+ 2 3 6 VTT IN+ 1 1 7 Out 2 2 Out 1 IN- 2 IN- 1 4 Gnd 0.1 µ F LM393 Ch2 LM393 Ch1 1 ΚΩ 1% VTTPWRGD5# 2.0 ms delay nominal

VTTPWRGD_Config_815E_B0

NOTE: the diode is included so that repeated pressing of the reset or power button does not cause the capacitor to build up enough charge to circumvent the 20 ms delay.

44 Intel® 815E Chipset Platform Design Guide

Universal Motherboard Design

R

4.2.7 VCMOS Reference

In previous platforms supporting the Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh), VCMOS was generated by the same power plane as VTT. The 0.13 micron socket 370 processors do not generate VCMOS, and the universal platform is required to generate this separately on the motherboard. Processor pin AK22, which is a GTL_REF pin on a Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh), has been changed to a VCMOS_REF pin on 0.13 micron socket 370 processors. Referring to Figure 18, a network of resistors and a capacitor must be added so that this pin operates appropriately for whichever processor is in the socket.

Figure 18. GTL_REF/VCMOS_REF Voltage Divider Network

VCMOS

75 Ω 1%

Processor Pin AK22

150 Ω .1 µ F 1%

GTL_CMOS_Ref_815E_B0

Intel® 815E Chipset Platform Design Guide 45

Universal Motherboard Design

R

4.2.8 Processor Signal PWRGOOD

The processor signal PWRGOOD is specified at different voltage levels depending on whether it is a Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh), or whether it is a 0.13 micron socket 370 processor. As there is an overlap between the ranges of accepted voltage levels for these two processor groups, a resistor divider network that provides 2.1V will satisfy the requirements of all supported processors. See Figure 19 for an example implementation.

Figure 19. Resistor Divider Network for Processor PWRGOOD

VCC2_5

330 Ω

PWRGOOD from ICH2 PWRGOOD to Processor

1.8 ΚΩ

PWRGOOD_Divider_815E_B0

46 Intel® 815E Chipset Platform Design Guide

Universal Motherboard Design

R

4.2.9 APIC Clock Voltage Switching Requirements

The processor’s APIC clock is also specified at different voltage levels depending on whether it is for the Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh) or whether it is for a 0.13 micron socket 370 processor. There is no overlap in the range of accepted voltage levels for the two processor groups, so a voltage switch is required to ensure proper operation. Figure 20 shows an example implementation.

Figure 20 Voltage Switch for Processor APIC Clock

IOAPIC

30 Ω

APICCLK_CPU

130 Ω TUAL5

MOSFET N

API_CLK_SW_815E_B0

NOTE: The 30 Ω resistor represents the series resistor typically used in connecting the APIC clock to the processor.

Intel® 815E Chipset Platform Design Guide 47

Universal Motherboard Design

R

4.2.10 GTLREF Topology and Layout

In a platform supporting the 0.13 micron socket 370 processors, the voltage requirements for GTLREF are different for the processor and the chipset. The GTLREF on the processor is specified to be 2/3 * VTT, while the GTLREF on the chipset is 0.7 * VTT. This difference requires that separate resistor sites be added to the layout to split the GTLREF sources. In a universal motherboard design, a Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh) will be unaffected by the difference in GTLREF. The recommended GTLREF circuit topology is shown in Figure 21.

Note: If an A-2 stepping of the GMCH is used with the universal motherboard design, the GTLREF for the GMCH should be set at 2/3 * VTT. This requires changing the 63.4 Ω, 1% resistor on the GMCH side to 75 Ω, 1%.

Figure 21. GTLREF Circuit Topology

VTT

63.4 Ω 75 Ω

GMCH Processor

150 Ω 150 Ω

gtlref_circuit

GTLREF Layout and Routing Guidelines • Place all resistor sites for GTLREF generation close to the GMCH. • Route GTLREF with as wide a trace as possible. • Use one 0.1 µF decoupling capacitor for every two GTLREF pins at the processor (four capacitors total). Place as close as possible (within 500 mils) to the Socket 370 GTLREF pins. • Use one 0.1 µF decoupling capacitor for each of the two GTLREF pins at the GMCH (two capacitors total). Place as close as possible to the GMCH GTLREF balls.

Given the higher GTLREF level for the GMCH, a debug test hook should be added for validation purposes. The debug test hook should be placed on the processor signal ADS# and consists of laying down the site for a 56 Ω pull-up to VTT. The resistor site should be located within 150 mils of the GMCH, and placed as close to the ADS# signal trace as possible.

48 Intel® 815E Chipset Platform Design Guide

Universal Motherboard Design

R

4.2.11 P-MOS Kicker “ON” Support

The PSB P-MOS Kicker circuit should be enabled on all 815E Universal Socket 370 designs. This is accomplished by strapping SMAA[9] high through an internal 50 kΩ pull-up resistor which enables the P-MOS Kicker. Use of the P-MOS Kicker circuit improves PSB timings by improving AGTL and AGTL+ signal flight time.

Existing designs which have implemented the pull-down resistor circuit on the SMAA[9] signal as shown in the Customer Reference Board schematics and populated the resistor site to over-ride the internal pull-up resistor, may depopulate the site to enable the P-MOS Kicker circuit. This activity should be based on timing analysis of the specific platform.

P-MOS Kicker circuit “ON” is the recommended setting for all 815E Universal Socket 370 designs including those using 0.13 micron technology processors.

4.3 Power Sequencing on Wake Events

In addition to the mechanism for identifying the processor in the socket, special handling of wake events is required for the 815 chipset platform that support functionality of the 0.13 micron socket 370 processors. When a wake event is triggered, the GMCH and the CK815 must not sample BSEL[1:0] until the signal VTTPWRGD is asserted. This is handled by setting up the following sequence of events: 1. Power is not connected to the CK815-compliant clock driver until VTTPWRGD12 is asserted. 2. Clocks to the ICH2 stabilize before the power supply asserts PWROK to the ICH2. There is no guarantee this will occur as the implementation for the previous step relies on the 12V supply. Thus it is necessary to gate PWROK to the ICH2 from the power supply while the CK815 is given sufficient time for the clocks to become stable. The amount of time required is a minimum 20 ms. 3. ICH2 takes the GMCH out of reset. 4. GMCH samples BSEL[1:0]. CK815 will have sampled BSEL[1:0] much earlier.

Intel® 815E Chipset Platform Design Guide 49

Universal Motherboard Design

R

4.3.1 Gating of Intel® CK815 to VTTPWRGD

System designers must ensure that the VTTPWRGD signal is asserted before the CK815- compliant clock driver receives power. This is handled by having the 3.3V rail of the clock driver gated by the VTTPWRGD12 reference schematic signal. Unlike previous 815E chipset designs, the 3.3V standby rail is not used to power the clock because the VTTPWRGD12 reference schematic signal will cut power to the clock when going into any sleep state. Refer to Figure 22 for an example implementation.

Figure 22. Gating Power to Intel® CK815

VCC3_3

MOSFET N

VTTPWRGD12 VDD on CK-815

Note: The FET must have no more than 100 milliohms resistance between the source and the drain.

50 Intel® 815E Chipset Platform Design Guide

Universal Motherboard Design

R

4.3.2 Gating of PWROK to Intel® ICH2

With power being gated to the CK815 by the signal VTTPWRGD12, it is important that the clocks to the ICH2 are stable before the power supply asserts PWROK to the ICH2. As the clocking power gating circuitry relies on the 12 V supply, there is no guarantee that these conditions will be met. This is why an estimated minimum time delay of 20 ms must be added after power is connected to the CK815 to give the clock driver sufficient time to stabilize. This time delay will gate the power supply’s assertion of PWROK to the ICH2. After the time delay, the power supply can safely assert PWROK to the ICH2, with the ICH2 subsequently taking the GMCH out of reset. Refer to Figure 23 for an example implementation.

Figure 23 PWROK Gating Circuit for Intel® ICH2

VDD on CK-815 VCC3_3 Note: delay 20ms after VDD on CK-815 is powered

43k

ICH2_PWROK 1.0uF PWROK

ICH2_PWROK_GATING

NOTE: The diode is included so that repeated pressing of the reset or power button does not cause the capacitor to build up enough charge to circumvent the 20ms delay.

Intel® 815E Chipset Platform Design Guide 51

Universal Motherboard Design

R

This page is intentionally left blank.

52 Intel® 815E Chipset Platform Design Guide

System Bus Design Guidelines

R

5 System Bus Design Guidelines

The Pentium III processor delivers higher performance by integrating the Level 2 cache into the processor and running it at the processor's core speed. The Pentium III processor runs at higher core and system bus speeds than previous-generation IA-32 processors while maintaining hardware and software compatibility with earlier Pentium III processors. The new Flip Chip-Pin Grid Array 2 (FC-PGA2) package technology enables compatibility with previous Flip Chip-Pin Grid Array (FC-PGA) packages using the PGA370 socket.

This section presents the considerations for designs capable of using the 815E universal platform with the full range of Pentium III processors using the PGA370 socket.

5.1 System Bus Routing Guidelines

The following layout guide supports designs using Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh), and 0.13 micron socket 370 processors with the 815 chipset platform. The solution covers system bus speeds of 66/100/133 MHz for the Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh), and 0.13 micron socket 370 processors. All processors must also be configured to 56 Ω on-die termination.

5.1.1 Initial Timing Analysis

Table 6 lists the AGTL/AGTL+ component timings of the processors and 815E universal platform’s GMCH defined at the pins.

Note: These timings are for reference only. Obtain each processor’s specifications from the respective processor datasheet and the chipset values from the appropriate 815 chipset datasheet.

Intel® 815E Chipset Platform Design Guide 53

System Bus Design Guidelines

R

Table 6. Intel® Pentium® III Processor AGTL/AGTL+ Parameters for Example Calculations

IC Parameters Intel® Pentium® III Processor GMCH Notes at 133 MHz System Bus

Clock to Output maximum 3.25 ns (for 66/100/133 MHz system bus 4.1 ns 1, 2 (TCO_MAX) speeds) Clock to Output minimum 0.40 ns (for 66/100/133 MHz system bus) 1.05 ns 1, 2 (TCO_MIN)

Setup time (TSU_MIN) 1.20 ns for BREQ Lines 2.65 ns 1, 2,3 0.95 ns for all other AGTL/AGTL+ Lines @ 133 MHz 1.20 ns for all other AGTL/AGTL+ Lines @ 66/100 MHz

Hold time (THOLD) 1.0 ns (for 66/100/133 MHz system bus 0.10 ns 1 speeds)

NOTES: 1. All times in nanoseconds. 2. Numbers in table are for reference only. These timing parameters are subject to change. Check the appropriate component documentation for the valid timing parameter values. 3. TSU_MIN = 2.65 ns assumes that the GMCH sees a minimum edge rate equal to 0.3 V/ns.

Table 7 contains an example AGTL+ initial maximum flight time, and Table 8 contains an example minimum flight time calculation for a 133 MHz, uniprocessor system using the Pentium III processor and the 815E chipset platform’s system bus. Note that assumed values were used for the clock skew and clock jitter.

Note: The clock skew and clock jitter values depend on the clock components and the distribution method chosen for a particular design, and must be budgeted into the initial timing equations as appropriate for each design.

Table 7 and Table 8 were derived assuming the following:

• CLKSKEW = 0.20 ns (Note: This assumes that the clock driver pin-to-pin skew is reduced to 50 ps by tying the two host clock outputs together (i.e., “ganging”) at the clock driver output pins, and that the PCB clock routing skew is 150 ps. The system timing budget must assume 0.175 ns of clock driver skew if outputs are not tied together as well as the use of a clock driver that meets the CK815 Clock Synthesizer/Driver Specification.)

• CLKJITTER = 0.250 ns

54 Intel® 815E Chipset Platform Design Guide

System Bus Design Guidelines

R

See the respective processor datasheet and the appropriate 815 chipset platform documentation for details on clock skew and jitter specifications. Exact details regarding the host clock routing topology are provided with the platform design guideline.

Table 7. Example TFLT_MAX Calculations for 133 MHz Bus

Driver Receiver Clk TCO_MAX TSU_MIN ClkSKEW ClkJITTER MADJ Recommended Period2 TFLT_MAX

Processor GMCH 7.50 3.25 2.65 0.20 0.25 0.40 1.1

GMCH Processor 7.50 4.1 1.20 0.20 0.25 0.40 1.35

NOTES: 1. All times in nanoseconds 2. BCLK period = 7.50 ns @ 133.33 MHz

Table 8. Example TFLT_MIN Calculations (Frequency Independent)

Driver Receiver THOLD ClkSKEW TCO_MIN Recommended TFLT_MIN

Processor GMCH 0.10 0.20 0.40 0.10

GMCH Processor 1.00 0.20 1.05 0.15

NOTE: All times in nanoseconds

The flight times in Table 7 include margin to account for the following phenomena that Intel observed when multiple bits are switching simultaneously. These multi-bit effects can adversely affect the flight time and signal quality and sometimes are not accounted for during simulation. Accordingly, the maximum flight times depend on the baseboard design, and additional adjustment factors or margins are recommended. • SSO push-out or pull-in • Rising or falling edge rate degradation at the receiver caused by inductance in the current return path, requiring extrapolation that causes additional delay • Crosstalk on the PCB and inside the package which can cause variation in the signals

Additional effects exist that may not necessarily be covered by the multi-bit adjustment factor and should be budgeted as appropriate to the baseboard design. These effects are included as MADJ in the example calculations in Table 7. Examples include: • The effective board propagation constant (SEFF), which is a function of:  Dielectric constant (εr) of the PCB material  Type of trace connecting the components (stripline or microstrip)  Length of the trace and the load of the components on the trace. Note that the board propagation constant multiplied by the trace length is a component of the flight time, but not necessarily equal to the flight time.

Intel® 815E Chipset Platform Design Guide 55

System Bus Design Guidelines

R

5.2 General Topology and Layout Guidelines

Figure 24. Topology for 370-Pin Socket Designs with Single-Ended Termination (SET)

PGA370 GMCH Socket

Ω Z0 = 60 ± 15%

sys_bus_topo_PGA370

Table 9. Trace Guidelines for Figure 24 1, 2, 3

Description Min. Length (inches) Max. Length (inches)

GMCH to PGA370 socket trace 1.90 4.50

NOTES: 1. All AGTL/AGTL+ bus signals should be referenced to the ground plane for the entire route. 2. Use an intragroup AGTL/AGTL+ spacing : line width : dielectric thickness ratio of at least 2:1:1 for microstrip geometry. If εr = 4.5, this should limit coupling to 3.4%. For example, intragroup AGTL+ routing could use 10 mil spacing, 5 mil traces, and a 5 mil prepreg between the signal layer and the plane it references (assuming a 4-layer motherboard design). 3. The recommended trace width is 5 mils, but not greater than 6 mils.

Table 10 contains the trace width: space ratios assumed for this topology. Three types of crosstalk are considered in this guideline: Intragroup AGTL/AGTL+, Intergroup AGTL/AGTL+, and AGTL/AGTL+ to non-AGTL/AGTL+. Intragroup AGTL/AGTL+ crosstalk involves interference between AGTL/AGTL+ signals within the same group. Intergroup AGTL/AGTL+ crosstalk involves interference from AGTL/AGTL+ signals in a particular group to AGTL/AGTL+ signals in a different group. An example of AGTL/AGTL+ to non-AGTL/AGTL+ crosstalk is when CMOS and AGTL/AGTL+ signals interfere with each other. The AGTL/AGTL+ signals consist of the following groups: data signals, control signals, clock signals, and address signals.

Table 10. Trace Width:Space Guidelines

Crosstalk Type Trace Width:Space Ratios1, 2

Intragroup AGTL/AGTL+ signals (same group AGTL/AGTL+) 5:10 or 6:12

Intergroup AGTL/AGTL+ signals (different group AGTL/AGTL+) 5:15 or 6:18

AGTL/AGTL+ to System Memory Signals 5:30 or 6:36

AGTL/AGTL+ to non-AGTL/AGTL+ 5:25 or 6:24

NOTES: 1. Edge-to-edge spacing. 2. Units are in mils.

56 Intel® 815E Chipset Platform Design Guide

System Bus Design Guidelines

R

5.2.1 Motherboard Layout Rules for AGTL/AGTL+ Signals

Ground Reference

It is strongly recommended that AGTL/AGTL+ signals be routed on the signal layer next to the ground layer (referenced to ground). It is important to provide an effective signal return path with low inductance. The best signal routing is directly adjacent to a solid GND plane with no splits or cuts. Eliminate parallel traces between layers not separated by a power or ground plane. If a signal has to go through routing layers, the recommendations are:

Note: Following these layout rules is critical for AGTL/AGTL+ signal integrity, particularly for 0.18 micron and smaller process technology. • For signals going from a ground reference to a power reference, add capacitors between ground and power near the vias to provide an AC return path. One capacitor should be used for every three signal lines that change reference layers. Capacitor requirements are as follows: C=100nF, ESR=80mΩ, ESL=0.6nH. Refer to Figure 25 for an example of switching reference layers. • For signals going from one ground reference to another, separate ground reference, add vias between the two ground planes to provide a better return path.

Figure 25. AGTL/AGTL+ Trace Routing

GMCH Processor

Layer 2 1.2V Power Plane

Layer 3 Ground Plane Socket Pin

0-500 mils 1.5-3.5 inches

AGTL_trace_route

Reference Plane Splits

Splits in reference planes disrupt signal return paths and increase overshoot/undershoot due to significantly increased inductance.

Processor Connector Breakout

It is strongly recommended that AGTL/AGTL+ signals do not traverse multiple signal layers. Intel recommends breaking out all signals from the connector on the same layer. If routing is tight, break out from the connector on the opposite routing layer over a ground reference and cross over to main signal layer near the processor connector.

Intel® 815E Chipset Platform Design Guide 57

System Bus Design Guidelines

R

Minimizing Crosstalk

The following general rules minimize the impact of crosstalk in a high-speed AGTL/AGTL+ bus design: • Maximize the space between traces. Where possible, maintain a minimum of 10 mils (assuming a 5 mil trace) between trace edges. It may be necessary to use tighter spacing when routing between component pins. When traces must be close and parallel to each other, minimize the distance that they are close together and maximize the distance between the sections when the spacing restrictions are relaxed. • Avoid parallelism between signals on adjacent layers, if there is no AC reference plane between them. As a rule of thumb, route adjacent layers orthogonally. • Since AGTL/AGTL+ is a low-signal-swing technology, it is important to isolate AGTL/AGTL+ signals from other signals by at least 25 mils. This will avoid coupling from signals that have larger voltage swings (e.g., 5V PCI). • AGTL/AGTL+ signals must be well isolated from system memory signals. AGTL/AGTL+ signal trace edges must be at least 30 mils from system memory trace edges within 100 mils of the ball of the 82815 GMCH. • Select a board stack-up that minimizes the coupling between adjacent signals. Minimize the nominal characteristic impedance within the AGTL/AGTL+ specification. This can be done by minimizing the height of the trace from its reference plane, which minimizes crosstalk. • Route AGTL/AGTL+ address, data, and control signals in separate groups to minimize crosstalk between groups. Keep at least 15 mils between each group of signals. • Minimize the dielectric used in the system. This makes the traces closer to their reference plane and thus reduces the crosstalk magnitude. • Minimize the dielectric process variation used in the PCB fabrication. • Minimize the cross-sectional area of the traces. This can be done by means of narrower traces and/or by using thinner copper, but the trade-off for this smaller cross-sectional area is higher trace resistivity, which can reduce the falling-edge noise margin because of the I*R loss along the trace.

58 Intel® 815E Chipset Platform Design Guide

System Bus Design Guidelines

R

5.2.1.1 Motherboard Layout Rules for Non-AGTL/AGTL+ (CMOS) Signals

Table 11. Routing Guidelines for Non-AGTL/AGTL+ Signals

Signal Trace Spacing to Other Traces Trace Length Width

A20M# 5 mils 10 mils 1” to 9”

FERR# 5 mils 10 mils 1” to 9”

FLUSH# 5 mils 10 mils 1” to 9”

IERR# 5 mils 10 mils 1” to 9”

IGNNE# 5 mils 10 mils 1” to 9”

INIT# 5 mils 10 mils 1” to 9”

LINT[0] (INTR) 5 mils 10 mils 1” to 9”

LINT[1] (NMI) 5 mils 10 mils 1” to 9”

PICD[1:0] 5 mils 10 mils 1” to 9”

PREQ# 5 mils 10 mils 1” to 9”

PWRGOOD 5 mils 10 mils 1” to 9”

SLP# 5 mils 10 mils 1” to 9”

SMI# 5 mils 10 mils 1” to 9”

STPCLK 5 mils 10 mils 1” to 9”

THERMTRIP# 5 mils 10 mils 1” to 9”

NOTE: Route these signals on any layer or combination of layers.

Intel® 815E Chipset Platform Design Guide 59

System Bus Design Guidelines

R

5.2.1.2 THRMDP and THRMDN

These traces (THRMDP and THRMDN) route the processor’s thermal diode connections. The thermal diode operates at very low currents and may be susceptible to crosstalk. The traces should be routed close together to reduce loop area and inductance.

Figure 26. Routing for THRMDP and THRMDN

Signal Y

1 — Maximize (min. – 20 mils)

THRMDP

2 — Minimize

THRMDN

1 — Maximize (min. – 20 mils)

Signal Z

bus_routing_thrmdp-thrmdn

NOTES: 1. Route these traces parallel and equalize lengths within ± 0.5 inch. 2. Route THRMDP and THRMDN on the same layer.

5.2.1.3 Additional Routing and Placement Considerations • Distribute VTT with a wide trace. An 0.050 inch minimum trace is recommended to minimize DC losses. Route the VTT trace to all components on the host bus. Be sure to include decoupling capacitors. • The VTT voltage should be 1.5V ± 3% for static conditions, and 1.5V ± 9% for worst-case transient conditions when the Pentium III processor (CPUID=068xh) or Celeron processor (CPUID=068xh) is present in the socket. If a 0.13 micron socket 370 processor is being used, the VTT voltage should then be 1.25V ± 3% for static conditions, and 1.25V ± 9% for worst- case transient conditions. • Place resistor divider pairs for VREF generation at the GMCH component. VREF also is delivered to the processor.

60 Intel® 815E Chipset Platform Design Guide

System Bus Design Guidelines

R

5.3 Electrical Differences for Universal PGA370 Designs

There are several electrical changes between previous PGA370 designs and the universal PGA370 design, as follows: • Changes to the PGA370 socket pin definitions. • Addition of VTTPWRGD signal to ensure stable VID selection for 0.13 micron socket 370 processors. • Addition of THERMTRIP circuit to allow processor to detect catastrophic overheat. • Addition of VID[25mV] signal to support 0.13 micron socket 370 processors. • Processor VTT level is switchable to 1.25V or 1.5V, depending on which processor is present in the socket. • In designs using 0.13 micron socket 370 processors, the processor does not generate VCMOS_REF.

5.3.1 THERMTRIP Circuit

To ensure that the processor detects and prevents catastrophic overheat, THERMTRIP is required on all designs that support 0.13 micron socket 370 processors. Figure 27 offers one possible implementation that makes use of the 4s Power Button feature on the ICH2.

Figure 27. Example Implementation of THERMTRIP Circuit

1.8V

1.5V

1 KΩ SW_ON#

Ω 4.7 K 1 KΩ Q2 1 KΩ Thermtrip# Q1

2.2 KΩ CPU_RST# Q3

Thermstrip_2

NOTES: 1. The pull-up voltage on the collector of Q1 is required to be 1.8V derived from a 3.3V source. 2. THERMTRIP is not valid until after CPU_RST# is deasserted. This is handled by gating the assertion of THERMTRIP with CPU_RST#. Using the CPU_RST# in this manner has minimal impact to the signal quality. 3. THERMTRIP must not go higher than VccCMOS levels. The pull-up on THERMTRIP is now connected to 1.5V. 4. CPU_RST# must gate SW_ON# from ground. This prevents glitching on SW_ON# during power-up and power-down. 5. The resistance to the base of the transistor gating CPU_RST# must be at least 2.2 KΩ for proper Vih levels on CPU_RST#.

Intel® 815E Chipset Platform Design Guide 61

System Bus Design Guidelines

R

5.3.1.1 THERMTRIP Timing

When the THERMTRIP signal is asserted, both the VCC and VTT supplies to the processor must be turned off to prevent thermal runaway of the processor. The time required from THERMTRIP asserted to VCC rail at ½ nominal is 5 s, and THERMTRIP asserted to VTT rail at ½ nominal is 5 s. System designers must ensure that the decoupling scheme used on these rails does not violate the THERMTRIP timing specifications.

5.3.1.2 THERMTRIP Support for Tualatin A-1 Stepping

A platform supporting the 0.13 micron technology processor must implement a workaround required for the A-1 stepping of that processor, identified by CPUID = 6B1h.

The internal control register bit responsible for operation of the THERMTRIP circuit functionality may power up in an un-initialized state. As a result, THERMTRIP# may be incorrectly asserted during de-assertion of RESET# at nominal operating temperatures. When THERMTRIP# is asserted as a result of this, the processor may shut down internally and stop execution. In addition, when the THERMTRIP# pin is asserted the processor may incorrectly continue to execute, leading to intermittent system power-on boot failures. The occurrence and repeatability of failures is system dependent, however all systems and processors are susceptible to failure.

To prevent the risk of power-on boot failures, a platform workaround is required. The system must provide a rising edge on the TCK signal during the power-on sequence that meets all of the following requirements: • •Rising edge occurs after Vcc_core is valid and stable • •Rising edge occurs before or at the de-assertion of RESET# • •Rising edge occurs after all Vref input signals are at valid voltage levels • •TCK input meets the Vih min (1.3 V) and max (1.65 V) spec requirements

Specific workaround implementations may be platform specific. The following examples have been tested as acceptable workaround implementations.

Note: the example workaround circuits attached require circuit modification for ITP tools to function correctly. These modifications must remove the workaround circuitry from the platform and may cause systems to fail to boot. Review the accompanying notes with each workaround for ITP modification details. If the system fails to boot when using ITP, issuing the ITP ‘Reset Target’ command on failing systems will reset the system and provide a sufficient rising edge on the TCK pin to ensure proper system boot.

In addition, the example workaround circuits shown do not support production motherboard test methodologies that require the use of the processor JTAG/TAP port. Alternative workaround solutions must be found if such test capability is required.

62 Intel® 815E Chipset Platform Design Guide

System Bus Design Guidelines

R

Figure 28. Example Workaround Circuits

2.5V

R1 330 ohm

PWRGD

R2 510 ohm PGA370

R4 TCK 0 ohm

R3 1.3K ohm R5 39 ohm

ITP

TCK

• For Production Boards  Depopulate R5

• To use ITP  Install R5, Depopulate R4

5.4 PGA370 Socket Definition Details

Table 12 compares the pin names and functions of the Intel® processors supported in the 815E universal platform.

Table 12. Processor Pin Definition Comparison

Pin # Pin Name Pin Name Pin Name Function Intel® Celeron® Intel® Pentium® 0.13 micron Processor III Processor Socket 370 (CPUID=068xh) (CPUID=068xh) Processors

AA33 Reserved VTT VTT • AGTL/AGTL+ termination voltage

Intel® 815E Chipset Platform Design Guide 63

System Bus Design Guidelines

R

Pin # Pin Name Pin Name Pin Name Function Intel® Celeron® Intel® Pentium® 0.13 micron Processor III Processor Socket 370 (CPUID=068xh) (CPUID=068xh) Processors

AA35 Reserved VTT VTT • AGTL/AGTL+ termination voltage

® AB36 VCCCMOS VCCCMOS VTT • CMOS voltage level for Intel Pentium® III processor (CPUID=068xh) and Intel® Celeron® processor (CPUID=068xh). • AGTL termination voltage for socket 370 processors.

AD36 VCC1.5 VCC1.5 VTT • VCC1.5 for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh).

• VTT for 0.13 micron socket 370 processors.

AF36 VSS VSS DETECT • Ground for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). • DETECT for 0.13 micron socket 370 processors.

AG11 VSS VSS VTT • Ground for Pentium III processor (CPUID=068xh) and Celeron® processor (CPUID=068xh). • VTT for 0.13 micron socket 370 processors

AH4 Reserved RESET# RESET# • Processor reset for the Pentium III processor (068xh) and 0.13 micron socket 370 processors

AH20 Reserved VTT VTT • AGTL/AGTL+ termination voltage

AJ31 VSS VSS RESET2# • Ground for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). • RESET2# for 0.13 micron socket 370 processors

AK4 VSS VSS VTTPWRGD • Ground for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). • VID control signal on 0.13 micron socket 370 processors.

AK16 Reserved VTT VTT • AGTL/AGTL+ termination voltage

64 Intel® 815E Chipset Platform Design Guide

System Bus Design Guidelines

R

Pin # Pin Name Pin Name Pin Name Function Intel® Celeron® Intel® Pentium® 0.13 micron Processor III Processor Socket 370 (CPUID=068xh) (CPUID=068xh) Processors

AK22 GTL_REF GTL_REF VCMOS_REF • GTL reference voltage for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). • CMOS reference voltage for 0.13 micron socket 370 processors

AK36 VSS VSS VID[25mV] • Ground for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). • 25mV step VID select bit for 0.13 micron socket 370 processors

AL13 Reserved VTT VTT • AGTL/AGTL+ termination voltage

AL21 Reserved VTT VTT • AGTL/AGTL+ termination voltage

AN3 GND GND DYN_OE • Ground for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). • Dynamic output enable for 0.13 micron socket 370 processors

AN11 Reserved VTT VTT • AGTL/AGTL+ termination voltage

AN15 Reserved VTT VTT • AGTL/AGTL+ termination voltage

AN21 Reserved VTT VTT • AGTL/AGTL+ termination voltage

E23 Reserved VTT VTT • AGTL/AGTL+ termination voltage

G35 Reserved VTT VTT • AGTL/AGTL+ termination voltage

G37 Reserved Reserved VTT • Reserved for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). • AGTL termination voltage for 0.13 micron socket 370 processors

N372 NC NC NCHCTRL • No connect for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). • NCHCTRL for0.13 micron socket 370 processors

Intel® 815E Chipset Platform Design Guide 65

System Bus Design Guidelines

R

Pin # Pin Name Pin Name Pin Name Function Intel® Celeron® Intel® Pentium® 0.13 micron Processor III Processor Socket 370 (CPUID=068xh) (CPUID=068xh) Processors

S33 Reserved VTT VTT • AGTL/AGTL+ termination voltage

S37 Reserved VTT VTT • AGTL/AGTL+ termination voltage

U35 Reserved VTT VTT • AGTL/AGTL+ termination voltage

U37 Reserved VTT VTT • AGTL/AGTL+ termination voltage

W3 Reserved A34# A34# • Additional AGTL/AGTL+ address

X41 RESET# RESET2# VSS • Processor reset for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). • Ground for 0.13 micron socket 370 processors

X6 Reserved A32# A32# • Additional AGTL/AGTL+ address 2 X34 VCCCORE VCCCORE VTT • Reserved for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). • AGTL termination voltage for 0.13 micron socket 370 processors

Y1 Reserved Reserved Reserved • Reserved for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). • Reserved for 0.13 micron socket 370 processors

Y33 Reserved CLKREF CLKREF • 1.25V PLL reference

Z362 VCC2.5 VCC2.5 Reserved • VCC2.5 for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). • Reserved for 0.13 micron socket 370 processors

NOTES: 1. Refer to Section 4. 2. Refer to Section 14.2

66 Intel® 815E Chipset Platform Design Guide

System Bus Design Guidelines

R

5.5 BSEL[1:0] Implementation Differences

A 0.13 micron socket 370 processor will select the 133 MHz system bus frequency setting from the clock synthesizer. A Pentium III processor (CPUID=068xh) utilizes the BSEL1 pin to select either the 100 MHz or 133 MHz system bus frequency setting from the clock synthesizer. A Celeron processor (CPUID=068xh) will use both BSEL pins to select 66 MHz system bus frequency from the clock synthesizer. Processors in an FC-PGA or an FC-PGA2 are 3.3V tolerant for these signals, as are the clock and chipset.

The CK815 has been designed to support selections of 66 MHz, 100 MHz, and 133 MHz. The REF input pin has been redefined to be a frequency selection strap (BSEL1) during power-on and then becomes a 14 MHz reference clock output. Figure 29 details the new BSEL[1:0] circuit design for universal PGA370 designs. Note that BSEL[1:0] now are pulled up using 1 kΩ resistors. Also refer to Figure 30 for more details.

Note: In a design supporting 0.13 micron socket 370 processors, the BSEL[1:0] lines are not valid until VTTPWRGD is asserted. Refer to Section 4.3 for full details.

Figure 29. BSEL[1:0] Circuit Implementation for PGA370 Designs

3.3V 3.3V

Processor

Ω Ω 1 k 1 k BSEL0 BSEL1

Clock Driver

Chipset

sys_ bus_BSEL_PGA370

Intel® 815E Chipset Platform Design Guide 67

System Bus Design Guidelines

R

5.6 CLKREF Circuit Implementation

The CLKREF input (used by the Pentium III processor (CPUID=068xh), Celeron processor (CPUID=068xh), and 0.13 micron socket 370 processors) requires a 1.25V source. It can be generated from a voltage divider on the VCC2.5 or VCC3.3 sources utilizing 1% tolerant resistors. A 4.7 µF decoupling capacitor should be included on this input. See Figure 30 and Table 13 for example CLKREF circuits. Do not use VTT as the source for this reference!

Figure 30. Examples for CLKREF Divider Circuit

PGA370 PGA370 Vcc2.5 Vcc3.3 CLKREF CLKREF Y33 Y33

150 Ω, 1% R1

150 Ω, 1% 4.7 µF R2 4.7 µF

sys_bus_CLKREF_divider

Table 13. Resistor Values for CLKREF Divider (3.3V Source)

R1 (Ω), 1% R2 (Ω), 1% CLKREF Voltage (V)

182 110 1.243

301 182 1.243

374 221 1.226

499 301 1.242

5.7 Undershoot/Overshoot Requirements

Undershoot and overshoot specifications become more critical as the process technology for microprocessors shrinks due to thinner gate oxide. Violating these undershoot and overshoot limits will degrade the life expectancy of the processor.

The Pentium III processor (CPUID=068xh), Celeron processor (CPUID=068xh), and 0.13 micron socket 370 processors have more restrictive overshoot and undershoot requirements for system bus signals than previous processors. These requirements stipulate that a signal at the output of the driver buffer and at the input of the receiver buffer must not exceed the maximum absolute overshoot voltage limit or the minimum absolute undershoot voltage limit. Exceeding either of these limits will damage the processor. There is also a time-dependent, non-linear overshoot and undershoot requirement that depends on the amplitude and duration of the overshoot/undershoot. See the appropriate processor datasheet for more details on the processor overshoot/undershoot specifications.

68 Intel® 815E Chipset Platform Design Guide

System Bus Design Guidelines

R

5.8 Processor Reset Requirements

Universal PGA370 designs must route the AGTL/AGTL+ reset signal from the chipset to two pins on the processor as well as to the debug port connector. This reset signal is connected to the following pins at the PGA370 socket: • AH4 (RESET#). The reset signal is connected to this pin for the Pentium III processor (CPUID=068xh), Celeron processor (CPUID=068xh), and 0.13 micron socket 370 processors • X4 (Reset2# or GND, depending on processor). The X4 pin is RESET2# for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). X4 is GND for 0.13 micron socket 370 processors. An additional 1 kΩ resistor is connected in series with pin X4 to the reset circuitry since pin X4 is a ground pin in 0.13 micron socket 370 processors.

Note: The AGTL/AGTL+ reset signal must always terminate to VTT on the motherboard.

Designs that do not support the debug port will not utilize the 240 Ω series resistor or the connection of RESET# to the debug port connector. RESET2# is not required for platforms that do not support the Celeron processor (CPUID=068xh). Pin X4 should then be connected to ground.

The routing rules for the AGTL/AGTL+ reset signal are shown in Figure 31.

Figure 31. RESET#/RESET2# Routing Guidelines

lenITP ITP VTT VTT

86 Ω 91 Ω 240 Ω Daisy chain cs_rtt_stub cpu_rtt_stub Ω Chipset 1 k Pin X4

lenCS lenCPU Processor 22 Ω Pin AH4 10 pF

sys_bus_reset_routin

Table 14. RESET#/RESET2# Routing Guidelines (see Figure 31)

Parameter Minimum (in) Maximum (in)

LenCS 0.5 1.5

LenITP 1 3

LenCPU 0.5 1.5

cs_rtt_stub 0.5 1.5

cpu_rtt_stub 0.5 1.5

Intel® 815E Chipset Platform Design Guide 69

System Bus Design Guidelines

R

5.9 Processor PLL Filter Recommendations

Intel® PGA370 processors have internal phase lock loop (PLL) clock generators that are analog and require quiet power supplies to minimize jitter.

5.9.1 Topology

The general desired topology for these PLLs is shown in Figure 33. Not shown are the parasitic routing and local decoupling capacitors. Excluded from the external circuitry are parasitics associated with each component.

5.9.2 Filter Specification

The function of the filter is to protect the PLL from external noise through low-pass attenuation. The low-pass specification, with input at VCCCORE and output measured across the capacitor, is as follows: • < 0.2 dB gain in pass band • < 0.5 dB attenuation in pass band (see DC drop in next set of requirements) • > 34 dB attenuation from 1 MHz to 66 MHz • > 28 dB attenuation from 66 MHz to core frequency

The filter specification is graphically shown in Figure 32.

70 Intel® 815E Chipset Platform Design Guide

System Bus Design Guidelines

R

Figure 32. Filter Specification

0.2dB 0dB -0.5 dB

Forbidden Zone

Forbidden Zone -28dB

-34dB

DC 1Hz fpeak 1 MHz 66 MHz fcore

passband high frequency band

filter_spec

NOTES: 1. Diagram not to scale. 2. No specification for frequencies beyond fcore. 3. fpeak should be less than 0.05 MHz.

Other requirements: • Use shielded-type inductor to minimize magnetic pickup. • Filter should support DC current > 30 mA. • DC voltage drop from VCC to PLL1 should be < 60 mV, which in practice implies series R < 2 Ω. This also means pass-band (from DC to 1 Hz) attenuation < 0.5 dB for VCC = 1.1 V, and < 0.35 dB for VCC = 1.5 V.

Intel® 815E Chipset Platform Design Guide 71

System Bus Design Guidelines

R

5.9.3 Recommendation for Intel® Platforms

The following tables contain examples of components that meet Intel’s recommendations when configured in the topology of Figure 33.

Table 15. Component Recommendations – Inductor

Part Number Value Tolerance SRF Rated DCR (Typical) Current

TDK MLF2012A4R7KT 4.7 µH 10% 35 MHz 30 mA 0.56 Ω (1 Ω max.)

Murata LQG21N4R7K00T1 4.7 µH 10% 47 MHz 30 mA 0.7 Ω (±50%)

Murata LQG21C4R7N00 4.7 µH 30% 35 MHz 30 mA 0.3 Ω max.

Table 16. Component Recommendations – Capacitor

Part Number Value Tolerance ESL ESR

Kemet T495D336M016AS 33 µF 20% 2.5 nH 0.225 Ω

AVX TPSD336M020S0200 33 µF 20% 2.5 nH 0.2 Ω

Table 17. Component Recommendation – Resistor

Value Tolerance Power Note

1 Ω 10% 1/16 W Resistor may be implemented with trace resistance, in which case a discrete R is not needed. See Figure 34.

To satisfy damping requirements, total series resistance in the filter (from VCCCORE to the top plate of the capacitor) must be at least 0.35 Ω. This resistor can be in the form of a discrete component or routing or both. For example, if the chosen inductor has minimum DCR of 0.25 Ω, then a routing resistance of at least 0.10 Ω is required. Be careful not to exceed the maximum resistance rule (2 Ω). For example, if using discrete R1 (1 Ω ± 1%), the maximum DCR of the L (trace plus inductor) should be less than 2.0 – 1.1 = 0.9 Ω, which precludes the use of some inductors and sets a max. trace length.

Other routing requirements: • The capacitor (C) should be close to the PLL1 and PLL2 pins, < 0.1 Ω per route. These routes do not count towards the minimum damping R requirement. • The PLL2 route should be parallel and next to the PLL1 route (i.e., minimize loop area). • The inductor (L) should be close to C. Any routing resistance should be inserted between VCCCORE and L.

• Any discrete resistor (R) should be inserted between VCCCORE and L.

72 Intel® 815E Chipset Platform Design Guide

System Bus Design Guidelines

R

Figure 33. Example PLL Filter Using a Discrete Resistor

VCCCORE

R L <0.1 Ω route PLL1 Discrete resistor

C Processor

PLL2 <0.1 Ω route

PLL_filter_1

Figure 34. Example PLL Filter Using a Buried Resistor

VCCCORE

R L <0.1 Ω route PLL1 Trace resistance

C Processor

PLL2 <0.1 Ω route

PLL_filter_2

5.9.4 Custom Solutions

As long as designers satisfy filter performance and requirements as specified and outlined in Section 5.9.2, other solutions are acceptable. Custom solutions should be simulated against a standard reference core model, which is shown in Figure 35.

Intel® 815E Chipset Platform Design Guide 73

System Bus Design Guidelines

R

Figure 35. Core Reference Model

Processor PLL1 0.1 Ω

120 pF 1 kΩ

PLL2 0.1 Ω

sys_bus_core_ref_model

NOTES: 1. 0.1 Ω resistors represent package routing. 2. 120 pF capacitor represents internal decoupling capacitor. 3. 1 kΩ resistor represents small signal PLL resistance. 4. Be sure to include all component and routing parasitics. 5. Sweep across component/parasitic tolerances. 6. To observe IR drop, use DC current of 30 mA and minimum VCCCORE level. 7. For other modules (interposer, DMM, etc.), adjust routing resistor if desired, but use minimum numbers.

5.10 Voltage Regulation Guidelines

A universal PGA370 design will need the voltage regulation module (VRM) or on-board voltage regulator (VR) to be compliant with Intel® VRM guidelines for 0.13 micron processors.

5.11 Decoupling Guidelines for Universal PGA370 Designs

These preliminary decoupling guidelines for universal PGA370 designs are estimated to meet the specifications of Intel VRM guidelines for 0.13 micron processors.

5.11.1 VCCCORE Decoupling Design

• Sixteen or more 4.7 µF capacitors in 1206 packages.

All capacitors should be placed within the PGA370 socket cavity and mounted on the primary side of the motherboard. The capacitors are arranged to minimize the overall inductance between the VCCCORE/VSS power pins, as shown in Figure 36.

74 Intel® 815E Chipset Platform Design Guide

System Bus Design Guidelines

R

Figure 36. Capacitor Placement on the Motherboard

5.11.2 VTT Decoupling Design

For Itt = 2.3 A (max.) • Twenty 0.1 µF capacitors in 0603 packages placed as closed as possible to the processor VTT pins. The capacitors are shown on the exterior of Figure 36.

5.11.3 VREF Decoupling Design

• Four 0.1 µF capacitors in 0603 package placed near VREF pins (within 500 mils).

Intel® 815E Chipset Platform Design Guide 75

System Bus Design Guidelines

R

5.12 Thermal Considerations

5.12.1 Heatsink Volumetric Keepout Regions

Current heatsink recommendations are only valid for supported Celeron and Pentium III processor frequencies.

Figure 37 shows the system component keepout volume above the socket connector required for the reference design thermal solution for high frequency processors. This keepout envelope provides adequate room for the heatsink, fan and attach hardware under static conditions as well as room for installation of these components on the socket. The heatsink must be compatible with the Integrated Heat Spreader (IHS) used by higher frequency Pentium III processors.

Figure 38 shows component keepouts on the motherboard required to prevent interference with the reference design thermal solution. Note portions of the heatsink and attach hardware hang over the motherboard.

Adhering to these keepout areas will ensure compatibility with Intel boxed processor products and Intel enabled third-party vendor thermal solutions for high frequency processors. While the keepout requirements should provide adequate space for the reference design thermal solution, systems integrators should check with their vendors to ensure their specific thermal solutions fit within their specific system designs. Please ensure that the thermal solutions under analysis comprehend the specific thermal design requirements for higher frequency Pentium III processors.

While thermal solutions for lower frequency processors may not require the full keepout area, larger thermal solutions will be required for higher frequency processors, and failure to adhere to the guidelines will result in mechanical interference.

76 Intel® 815E Chipset Platform Design Guide

System Bus Design Guidelines

R

Figure 37. Heatsink Volumetric Keepout Regions

Figure 38. Motherboard Component Keepout Regions

Intel® 815E Chipset Platform Design Guide 77

System Bus Design Guidelines

R

5.13 Debug Port Changes

Due to the lower voltage technology employed with newer processors, changes are required to support the debug port. Previously, test access port (TAP) signals used 2.5V logic, as is the case with the Celeron processor in the PPGA package. Pentium III processor (CPUID=068xh), Celeron processor (CPUID=068xh), and 0.13 micron socket 370 processors utilize 1.5V logic levels on the TAP. As a result, the type of debug port connecter used in universal PGA370 designs is dependent on the processor that is currently in the socket. The 1.5V connector is a mirror image of the older 2.5V connector. Either connector will fit into the same printed circuit board layout. Only the pin numbers change (Figure 39). Also required, along with the new connector, is an In-Target Probe* (ITP) that is capable of communicating with the TAP at the appropriate logic levels.

Figure 39. TAP Connector Comparison

2.5 V connector, AMP 104068-3 vertical plug, top view

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

RESET# 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

1.5 V connector, AMP 104078-4 vertical receptacle, top view

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

RESET# 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

sys_bus_TAP_conn

Caution: The Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh) require an in- target probe (ITP) compatible with 1.5V signal levels on the TAP. Previous ITPs were designed to work with higher voltages and may damage the processor if connected to any of these specified processors.

See the processor datasheet for more information regarding the debug port.

78 Intel® 815E Chipset Platform Design Guide

System Memory Design Guidelines

R

6 System Memory Design Guidelines

6.1 System Memory Routing Guidelines

Ground plane reference all system memory signals. To provide a good current return path and limit noise on the system memory signals, the signals should be ground referenced from the GMCH to the DIMM connectors and from DIMM connector-to-DIMM connector. If ground referencing is not possible, system memory signals should be, at a minimum, referenced to a single plane. If single plane referencing is not possible, stitching capacitors should be added no more than 200 mils from the signal via field. System memory signals may via to the backside of the PCB under the GMCH without a stitching capacitor as long as the trace on the topside of the PCB is less than 200 mils.

Note: Intel recommends that a parallel plate capacitor between VCC3.3SUS and GND be added to account for the current return path discontinuity (See Decoupling section). Use (1) .01uf X7R capacitor per every (5) system memory signals that switch plane references. No more than two vias are allowed on any system memory signal.

If a group of system memory signals must change layers, a via field should be created and a decoupling capacitor should be added at the end of the via field. Do not route signals in the middle of a via field, this causes noise to be generated on the current return path of these signals and can lead to issues on these signals (see Figure 40). The traces shown are on layer 1 only. The figure shows signals that are changing layer and two signals that are not changing layer. Note that the two signals around the via field create a keepout zone where no signals that do not change layer should be routed.

Figure 40. System Memory Routing Guidelines

Do not route any signal in Add (1) 0.01 uf capacitor the middle of the via field X7R (5) signals that via that do not change layers

Stagger vias in via field to avoid power/ground plane cut off because of the antipad on the internal layers sys-mem-route

Intel® 815E Chipset Platform Design Guide 79

System Memory Design Guidelines

R

6.2 System Memory 2-DIMM Design Guidelines

6.2.1 System Memory 2-DIMM Connectivity

Figure 41. System Memory Connectivity (2 DIMM)

Double-Sided, Unbuffered Pinout without ECC

SCSA[3:2]# SCSA[1:0]#

SCKE[1:0] Notes: SCKE[3:2] Min. (16 Mbit) 8 MB Max. (64 Mbit) 256 MB SCSB[3:2]# Max. (128 Mbit) 512 MB SCSB[1:0]# SRAS# SCAS# 82815 SWE# SBS[1:0] SMAA[12:8,3:0] SMAA[7:4] SMAB[7:4]#

SDQM[7:0] SMD[63:0]

DIMM_CLK[3:0] CK815 DIMM_CLK[7:4]

SMB_CLK ICH SMB_DATA DIMM 0 & 1 sys_mem_conn_2DIMM

80 Intel® 815E Chipset Platform Design Guide

System Memory Design Guidelines

R

6.2.2 System Memory 2-DIMM Layout Guidelines

Figure 42. System Memory 2-DIMM Routing Topologies

82815 DIMM 0 DIMM 1

Topology 1 A B

Topology 2 C

Topology 3 D 10 Ω Topology 4 E F 10 Ω Topology 5 E F

sys_mem_2DIMM_routing_topo

Table 18. System Memory 2-DIMM Solution Space

Signal Top. Trace (mils) Trace Lengths (inches)

A B C D E F

Width Spacing Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

SCS[3:2]# 3 5 10 1 4.5

SCS[1:0]# 2 5 10 1 4.5

SMAA[7:4] 4 10 10 0.4 0.5 2 4

SMAB[7:4]# 5 10 10 0.4 0.5 2 4

SCKE[3:2] 3 10 10 3 4

SCKE[1:0] 2 10 10 3 4

SMD[63:0] 1 5 10 1.75 4 0.4 0.5

SDQM[7:0] 1 10 10 1.5 3.5 0.4 0.5

SCAS#, SRAS#, SWE# 1 5 10 1 4.0 0.4 0.5

SBS[1:0], 1 5 10 1 4.0 0.4 0.5 SMAA[12:8,3:0]

In addition to meeting the spacing requirements outlined in Table 18, system memory signal trace edges must be at least 30 mils from any other non-system memory signal trace edge.

Intel® 815E Chipset Platform Design Guide 81

System Memory Design Guidelines

R

Figure 43. System Memory Routing Example

sys_mem_routing_ex

NOTE: Routing in this figure is for example purposes only. It does not necessarily represent complete and correct routing for this interface.

82 Intel® 815E Chipset Platform Design Guide

System Memory Design Guidelines

R

6.3 System Memory 3-DIMM Design Guidelines

6.3.1 System Memory 3-DIMM Connectivity

Figure 44. System Memory Connectivity (3 DIMM)

Double-Sided, Unbuffered Pinout without ECC

SCSA[5:4]# SCSA[3:2]# SCSA[1:0]#

Notes: Min. (16 Mbit) 8 MB SCKE[1:0] Max. (64 Mbit) 256 MB Max. (128 Mbit) 512 MB SCKE[3:2] SCKE[5:4] SCSB[5:4]# SCSB[3:2]# SCSB[1:0]#

SRAS# SCAS# 82815 SWE# SBS[1:0] SMAA[12:8,3:0] SMAA[7:4] SMAB[7:4]# SMAC[7:4]# SDQM[7:0] SMD[63:0]

DIMM_CLK[3:0] CK815 DIMM_CLK[7:4] DIMM_CLK[11:8]

SMB_CLK ICH SMB_DATA DIMM 0 & 1 & 2 sys_mem_conn_3DIMM

Intel® 815E Chipset Platform Design Guide 83

System Memory Design Guidelines

R

6.3.2 System Memory 3-DIMM Layout Guidelines

Figure 45. System Memory 3-DIMM Routing Topologies

82815 DIMM 0 DIMM 1 DIMM 2

Topology 1 A B B Topology 2 C

Topology 3 D

Topology 4 E

Topology 5 F BB 10 Ω Topology 6 G C 10 Ω Topology 7 G D 10 Ω Topology 8 G E

sys_mem_3DIMM_routing_topo

In addition to meeting the spacing requirements outlined in Table 19, system memory signal trace edges must be at least 30 mils from any other non-system memory signal trace edge.

Table 19. System Memory 3-DIMM Solution Space

Signal Top. Trace (mils) Trace Lengths (inches)

A B C D E F G

Width Spacing Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

SCS[5:4]# 4 5 10 1 4.5

SCS[3:2]# 3 5 10 1 4.5

SCS[1:0]# 2 5 10 1 4.5

SMAA[7:4] 6 10 10 2 4 0.4 0.5

SMAB[7:4]# 7 10 10 2 4 0.4 0.5

SMAC[7:4} 8 10 10 2 4 0.4 0.5

SCKE[5:4] 4 10 10 3 4

SCKE[3:2] 3 10 10 3 4

SCKE[1:0] 2 10 10 3 4

SMD[63:0] 1 5 10 1.75 4 0.4 0.5

SDQM[7:0] 1 10 10 1.5 3.5 0.4 0.5

SCAS#,SRAS#, 5 5 10 0.4 0.5 1 4 SWE#

SBS[1:0], 5 5 10 0.4 0.5 1 4 SMAA[12:8,3:0]

84 Intel® 815E Chipset Platform Design Guide

System Memory Design Guidelines

R

6.4 System Memory Decoupling Guidelines

A minimum of eight 0.1 µF low-ESL ceramic capacitors (e.g., 0603 body type, X7R dielectric) are required and must be as close as possible to the GMCH. They should be placed within at most 70 mils to the edge of the GMCH package edge for VSUS_3.3 decoupling, and they should be evenly distributed around the system memory interface signal field including the side of the GMCH where the system memory interface meets the host interface. There are power and GND balls throughout the system memory ball field of the GMCH that need good local decoupling. Make sure to use at least 14 mil drilled vias and wide traces from the pads of the capacitor to the power or ground plane to create a low inductance path. If possible multiple vias per capacitor pad are recommended to further reduce inductance. To add the decoupling capacitors within 70 mils of the GMCH and/or close to the vias, the trace spacing may be reduced as the traces go around each capacitor. The narrowing of space between traces should be minimal and for as short a distance as possible (500mils max).

To further de-couple the GMCH and provide a solid current return path for the system memory interface signals it is recommended that a parallel plate capacitor be added under the GMCH. Add a topside or bottom side copper flood under center of the GMCH to create a parallel plate capacitor between VCC3.3 and GND (see Figure 46). The dashed lines indicate power plane splits on layer 2 or layer 3 depending on stack-up. The filled region in the middle of the GMCH indicates a ground plate (on layer 1 if the power plane is on layer 2 or on layer 4 if the power layer is on layer 3).

Figure 46. Intel 815 Chipset Platform Decoupling Example

Intel® 815E Chipset Platform Design Guide 85

System Memory Design Guidelines

R

Yellow lines show layer two plane splits. Note that the layer 1 shapes do NOT cross the plane splits. The bottom shape is a VSS fill over VddSDRAM. The left-side shape is a VSS fill over VddAGP. The larger upper-right-side shape is a VSS fill over VddCORE.

Additional decoupling capacitors should be added between the DIMM connectors to provide a current return path for the reference plane discontinuity created by the DIMM connectors themselves. One 0.01 µF X7R capacitor should be added per every ten SDRAM signals. Capacitors should be placed between the DIMM connectors and evenly spread out across the SDRAM interface.

For debug purposes, four or more 0603 capacitor sites should be placed on the backside of the board, evenly distributed under the 815E chipset platform’s system memory interface signal field.

Figure 47. Intel® 815 Chipset Decoupling Example

6.5 Compensation

A system memory compensation resistor (SRCOMP) is used by the GMCH to adjust the buffer characteristics to specific board and operating environment characteristics. Refer to the Intel® 815 Chipset Family: 82815 Graphics and Memory Controller Hub (GMCH) for use with the Universal Socket 370 Datasheet for details on compensation. Tie the SRCOMP pin of the GMCH to a 40 Ω 1% or 2% pull-up resistor to 3.3 Vsus (3.3V standby) via a 10 mil-wide, 0.5 inch trace (targeted for a nominal impedance of 40 Ω).

86 Intel® 815E Chipset Platform Design Guide

AGP/Display Cache Design Guidelines

R

7 AGP/Display Cache Design Guidelines

For the detailed AGP interface functionality (e.g., protocols, rules, signaling mechanisms), refer to the latest AGP Interface Specification, Revision 2.0, which can be obtained from http://www.agpforum.org. This design guide focuses only on specific 815 chipset platform recommendations.

7.1 AGP Interface

A single AGP connector is supported by the GMCH AGP interface. LOCK# and SERR#/PERR# are not supported. See the display cache discussion for a description of display cache/AGP muxing as well as a description of the Graphics Performance Accelerator (GPA).

The AGP buffers operate in one of two selectable modes, to support the AGP universal connector: • 3.3V drive, not 5V safe. This mode is compliant with the AGP 1.0 66 MHz specification • 1.5V drive, not 3.3V safe. This mode is compliant with the AGP 2.0 specification

The AGP 4X must operate at 1.5 V and only use differential clocking mode. The AGP 2X can operate at 3.3 V or 1.5 V. The AGP interface supports up to 4X AGP signaling, though 4X fast writes are not supported. AGP semantic cycles to DRAM are not snooped on the host bus.

The GMCH supports PIPE# or SBA[7:0] AGP address mechanisms, but not both simultaneously. Either the PIPE# or the SBA[7:0] mechanism must be selected during system initialization. The GMCH contains a 32-deep AGP request queue. High-priority accesses are supported. All AGP semantic accesses hitting the graphics aperture pass through an address translation mechanism with a fully-associative, 20-entry TLB.

Accesses between AGP and the hub interface are limited to hub interface-originated memory writes to AGP. Cacheable accesses from the IOQ queue flow through one path, while aperture accesses follow another path. Cacheable AGP (SBA, PIPE#, and FRAME#) reads to DRAM all snoop the cacheable global write buffer (GWB) for system data coherency. Aperture AGP (SBA, PIPE#) reads to DRAM snoop the aperture queue (GCMCRWQ). Aperture AGP (FRAME#) reads and writes to DRAM proceed through a FIFO and there is no RAW capability, so no snoop is required.

The AGP interface is clocked from the 66 MHz clock (3V66). The AGP-to-host/memory interface is synchronous with a clock ratio of 1:1 (66 MHz: 66 MHz), 2:3 (66 MHz: 100 MHz) and 1:2 (66 MHz: 133 MHz).

Intel® 815E Chipset Platform Design Guide 87

AGP/Display Cache Design Guidelines

R

7.1.1 Graphics Performance Accelerator (GPA)

The GMCH multiplexes the AGP signal interface with the integrated graphics’ display cache interface. As a result, for a universal motherboard that supports both integrated graphics and add- in AGP video cards, display cache (for integrated graphics) must be populated on a card in the universal AGP slot. The card is called a Graphics Performance Accelerator (GPA) card. Intel provides a specification for this card in a separate document (Graphics Performance Accelerator Specification).

AGP guidelines are presented in this section for motherboards that support the population of a GPA card in their AGP slot as well as for those that do not, and for AGP “down” implementations in which AGP-compliant devices are implemented directly on motherboards. Where there are distinct guidelines dependent on whether or not a motherboard will support a GPA card, the section detailing standard routing guidelines is divided into subsections, as follows: • The Flexible Motherboard Guidelines subsection is to be complied with if the motherboard supports a GPA card populated in the AGP slot. • The AGP-Only Motherboard Guidelines subsection is to be complied with if the motherboard does not support a GPA card populated in the AGP slot.

7.1.2 AGP Universal Retention Mechanism (RM)

Environmental testing and field reports indicate that AGP cards and Graphics Performance Accelerator (GPA) cards may come unseated during system shipping and handling without proper retention. To avoid disengaged AGP cards and GPA modules, Intel recommends that AGP-based platforms use the AGP retention mechanism (RM).

The AGP RM is a mounting bracket that is used to properly locate the card with respect to the chassis and to assist with card retention. The AGP RM is available in two different handle orientations: left-handed (see Figure 48) and right-handed. Most system boards accommodate the left-handed AGP RM. The manufacturing capacity of the left-handed RM currently exceeds the right-handed capacity, and as a result Intel recommends that customers design their systems to insure they can use the left-handed version of the AGP RM. The right-handed AGP RM is identical to the left-handed AGP RM, except for the position of the actuation handle. This handle is located on the same end as the primary design, but extends from the opposite side (mirrored about the center axis running parallel to the length of the part). Figure 49 contains keepout information for the left hand AGP retention mechanism. Use this information to make sure that the motherboard design leaves adequate space to install the retention mechanism.

The AGP interconnect design requires that the AGP card must be retained to the extent that the card not back out more than 0.99 mm (0.039 in) within the AGP connector. To accomplish this it is recommended that new cards implement an additional notch feature in the mechanical keying tab to allow an anchor point on the AGP card for interfacing with an AGP RM. The retention mechanism’s round peg engages with the AGP or GPA card’s retention tab and prevents the card from disengaging during dynamic loading. The additional notch feature in the mechanical keying tab is required for 1.5Volt AGP cards and is recommended for the new 3.3Volt AGP cards.

88 Intel® 815E Chipset Platform Design Guide

AGP/Display Cache Design Guidelines

R

Figure 48. AGP Left-Handed Retention Mechanism

Figure 49. AGP Left-Handed Retention Mechanism Keepout Information

Engineering Change Request number 48 (ECR #48) of the AGP specification details the AGP RM, which is recommended for all AGP cards. These are approved changes to the Accelerated Graphics Port (AGP) Interface Specification, Revision 2.0. Intel intends to incorporate the AGP RM changes into later revisions of the AGP Interface Specification. In addition, Intel has defined a reference design of a mechanical device to utilize the features defined in ECR #48.

ECR #48 can be viewed off the Intel website at:

http://developer.intel.com/technology/agp/ecr.htm

Intel® 815E Chipset Platform Design Guide 89

AGP/Display Cache Design Guidelines

R

More information regarding this component (AGP RM) is available from the following vendors.

Table 20. Retention Mechanism Vendors

Resin Color Supplier Part “Left Handed” Orientation “Right Handed” Orientation Number (Preferred) (Alternate)

Black AMP P/N 136427-1 136427-2

Foxconn P/N 006-0002-939 006-0001-939

Green Foxconn P/N 009-0004-008 009-0003-008

7.2 AGP 2.0

Rev. 2.0 of the AGP Interface Specification enhances the functionality of the original AGP Interface Specification, Revision 1.0, by allowing 4X data transfers (4 data samples per clock) and 1.5V operation. The 4X operation of the AGP interface provides for “quad-pumping” of the AGP AD (address/data) and SBA (side-band addressing) buses. That is, data is sampled four times during each 66 MHz AGP clock, which means that each data cycle is ¼ of a 15 ns (66 MHz) clock, or 3.75 ns. Note that 3.75 ns is the data cycle time, not the clock cycle time. During 2X operation, data is sampled twice during a 66 MHz clock cycle, so the data cycle time is 7.5 ns. To allow for such high-speed data transfers, the 2X mode of AGP operation uses source-synchronous data strobing. During 4X operation, the AGP interface uses differential source-synchronous strobing.

With data-cycle times as small as 3.75 ns and setup/hold times of 1 ns, propagation delay mismatch is critical. In addition to reducing propagation delay mismatch, it is important to minimize noise. Noise on the data lines causes the settling time to be long. If the mismatch between a data line and the associated strobe is too great or if there is noise on the interface, incorrect data will be sampled. The low-voltage operation on the AGP (1.5 V) requires even more

noise immunity. For example, during 1.5V operation, Vilmax is 570 mV. Without proper isolation, crosstalk could create signal integrity issues.

90 Intel® 815E Chipset Platform Design Guide

AGP/Display Cache Design Guidelines

R

7.2.1 AGP Interface Signal Groups

The signals on the AGP interface are broken into three groups: 1X timing domain signals, 2X/4X timing domain signals, and miscellaneous signals. Each group has different routing requirements. In addition, within the 2X/4X timing domain signals, there are three sets of signals. All signals in the 2X/4X timing domain must meet minimum and maximum trace length requirements as well as trace width and spacing requirements. However, trace length matching requirements only must be satisfied within each set of 2X/4X timing domain signals. The signal groups are listed in Table 21.

Table 21. AGP 2.0 Signal Groups

Groups Signal

1X Timing Domain CLK (3.3 V), RBF#, WBF#, ST[2:0], PIPE#, REQ#, GNT#, PAR, FRAME#, IRDY#, TRDY#, STOP#, DEVSEL#

2X/4X Timing Domain Set #1: AD[15:0], C/BE[1:0]#, AD_STB0, AD_STB0#1 Set #2: AD[31:16], C/BE[3:2]#, AD_STB1, AD_STB1#1 Set #3: SBA[7:0], SB_STB, SB_STB#1

Miscellaneous, async. USB+, USB-, OVRCNT#, PME#, TYPDET#, PERR#, SERR#, INTA#, INTB#

NOTE: These signals are used in 4X AGP mode ONLY.

Table 22. AGP 2.0 Data/Strobe Associations

Data Associated Strobe in 1X Associated Strobe Associated Strobes in in 2X 4X

AD[15:0] and Strobes are not used in 1X AD_STB0 AD_STB0, AD_STB0# C/BE[1:0]# mode. All data is sampled on rising clock edges.

AD[31:16] and Strobes are not used in 1X AD_STB1 AD_STB1, AD_STB1# C/BE[3:2]# mode. All data is sampled on rising clock edges.

SBA[7:0] Strobes are not used in 1X SB_STB SB_STB, SB_STB# mode. All data is sampled on rising clock edges.

Throughout this section the term data refers to AD[31:0], C/BE[3:0]#, and SBA[7:0]. The term strobe refers to AD_STB[1:0], AD_STB[1:0]#, SB_STB, and SB_STB#. When the term data is used, it refers to one of the three sets of data signals, as listed in Table 21. When the term strobe is used, it refers to one of the strobes as it relates to the data in its associated group.

The routing guidelines for each group of signals (1X timing domain signals, 2X/4X timing domain signals, miscellaneous signals) will be addressed separately.

Intel® 815E Chipset Platform Design Guide 91

AGP/Display Cache Design Guidelines

R

7.3 Standard AGP Routing Guidelines

7.3.1 1X Timing Domain Routing Guidelines

7.3.1.1 Flexible Motherboard Guidelines • The AGP 1X timing domain signals (Table 21) have a maximum trace length of 4 inches for motherboards that support a Graphics Performance Accelerator (GPA) card. This maximum applies to ALL signals listed as 1X timing domain signals in Table 21. • AGP 1X signals multiplexed with display cache signals (listed below) should be routed with a 1:3 trace width-to-spacing ratio. All other AGP 1X timing domain signals can be routed with 5 mil minimum trace separation. • There are no trace length matching requirements for 1X timing domain signals.

The following are multiplexed AGP1X signals on flexible motherboards:

• RBF# • FRAME# • ST[2:0] • IRDY# • PIPE# • TRDY# • REQ# • STOP# • GNT# • DEVSEL# • PAR

7.3.1.2 AGP-Only Motherboard Guidelines • AGP 1X timing domain signals (Table 21) have a maximum trace length of 7.5 inches for motherboards that will not support a Graphics Performance Accelerator (GPA) card. This maximum applies to ALL signals listed as 1X timing domain signals in Table 21. • All AGP 1X timing domain signals can be routed with 5 mil minimum trace separation. • There are no trace length matching requirements for 1X timing domain signals.

7.3.2 2X/4X Timing Domain Routing Guidelines

These trace length guidelines apply to ALL signals listed in Table 21 as 2X/4X timing domain signals. These signals should be routed using 5 mil (60 Ω) traces.

The maximum line length and length mismatch requirements depend on the routing rules used on the motherboard. These routing rules were created to provide design freedom by making trade-offs between signal coupling (trace spacing) and line lengths. The maximum length of the AGP interface defines which set of routing guidelines must be used. Guidelines for short AGP interfaces (e.g., < 6 inches) and long AGP interfaces (e.g., > 6 inches and < 7.25 inches) are documented separately. The maximum length allowed for the AGP interface (on AGP-only motherboards) is 7.25 inches.

92 Intel® 815E Chipset Platform Design Guide

AGP/Display Cache Design Guidelines

R

7.3.2.1 Flexible Motherboard Guidelines • For motherboards that support either an AGP card or a GPA card in the AGP slot, the maximum length of AGP 2X/4X timing domain signals is 4 inches. • 1:3 trace width-to-spacing is required for AGP 2X/4X signal traces. • AGP 2X/4X signals must be matched with their associated strobe (as outlined in Table 21), within ± 0.5 inch.

For example, if a set of strobe signals (e.g., AD_STB0 and AD_STB0#) are 3.7 inches long, the data signals associated with those strobe signals (e.g., AD[15:0] and C/BE[2:0]#) can be 3.2 inches to 4 inches long (since there is a 4 inches max. length). Another strobe set (e.g., SB_STB and SB_STB#) could be 3.1 inches long, so that the associated data signals (e.g., SBA[7:0]) can be 2.6 inches to 3.6 inches long.

The strobe signals (AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, and SB_STB#) act as clocks on the source-synchronous AGP interface. Therefore, special care must be taken when routing these signals. Since each strobe pair is truly a differential pair, the pair should be routed together (e.g., AD_STB0 and AD_STB0# should be routed next to each other). The two strobes in a strobe pair should be routed using 5 mil traces with at least 15 mils of space (1:3) between them. This pair should be separated from the rest of the AGP signals (and all other signals) by at least 20 mils (1:4). The strobe pair must be length-matched to less than ± 0.1 inch (i.e., a strobe and its complement must be the same length within 0.1 inch).

Figure 50. AGP 2X/4X Routing Example for Interfaces < 6 inches and GPA/AGP Solutions

5-mil trace 2X/4X signal 15 mils 2X/4X signal 5-mil trace 2X/4X signal

20 mils 2X/4X signal

5-mil trace AGP STB# 15 mils AGP STB# 5-mil trace AGP STB

20 mils AGP STB

5-mil trace 2X/4X signal 15 mils 2X/4X signal

2X/4X signal

2X/4X signal

STB/STB# length Associated AGP 2X/4X data signal length 0.5" 0.5" Min. Max. AGP_2x-4x_routing

Intel® 815E Chipset Platform Design Guide 93

AGP/Display Cache Design Guidelines

R

7.3.2.2 AGP-Only Motherboard Guidelines

For motherboards that will not support a GPA card populated in the AGP slot, the maximum AGP 2X/4X signal trace length is 7.25 inches. However, there are different guidelines for AGP interfaces shorter than 6 inches (e.g., all AGP 2X/4X signals are shorter than 6 inches) and those longer than 6 inches but shorter than the 7.25 inches maximum.

AGP Interfaces Shorter Than 6 Inches The following guidelines are for designs that require less than 6 inches between the AGP connector and the GMCH: • 1:3 trace width-to-spacing is required for AGP 2X/4X timing domain signal traces. • AGP 2X/4X signals must be matched with their associated strobe (as outlined in Table 21), within ± 0.5 inch. For example, if a set of strobe signals (e.g., AD_STB0 and AD_STB0#) are 5.3 inches long, the data signals associated with those strobe signals (e.g., AD[15:0] and C/BE[2:0]#) can be 4.8 inches to 5.8 inches long. Another strobe set (e.g., SB_STB and SB_STB#) could be 4.2 inches long, and the data signals associated with those strobe signals (e.g., SBA[7:0]) could be 3.7 inches to 4.7 inches long.

The strobe signals (AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, and SB_STB#) act as clocks on the source-synchronous AGP interface. Therefore, special care must be taken when routing these signals. Because each strobe pair is truly a differential pair, the pair should be routed together (e.g., AD_STB0 and AD_STB0# should be routed next to each other). The two strobes in a strobe pair should be routed on 5 mil traces with at least 15 mils of space (1:3) between them. This pair should be separated from the rest of the AGP signals (and all other signals) by at least 20 mils (1:4). The strobe pair must be length-matched to less than ± 0.1 inches (i.e., a strobe and its complement must be the same length, within 0.1 inches). Refer to Table 21 for an illustration of these requirements.

AGP Interfaces Longer Than 6 Inches Since longer lines have more crosstalk, they require wider spacing between traces to reduce the skew. The following guidelines are for designs that require more than 6 inches (but less than the 7.25 inches max.) between the AGP connector and the GMCH: • 1:4 trace width-to-spacing is required for AGP 2X/4X timing domain signal traces. • AGP 2X/4X signals must be matched with their associated strobe (as outlined in Table 21), within ± 0.125 inches. For example, if a set of strobe signals (e.g., AD_STB0 and AD_STB0#) are 6.5 inches long, the data signals associated with those strobe signals (e.g., AD[15:0] and C/BE[2:0]#) can be 6.475 inches to 6.625 inches long. Another strobe set (e.g., SB_STB and SB_STB#) could be 6.2 inches long, and the data signals associated with those strobe signals (e.g., SBA[7:0]) could be 6.075 inches to 6.325 inches long.

The strobe signals (AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, and SB_STB#) act as clocks on the source-synchronous AGP interface. Therefore, special care must be taken when routing these signals. Because each strobe pair is truly a differential pair, the pair should be routed together (e.g., AD_STB0 and AD_STB0# should be routed next to each other). The two strobes in a strobe pair should be routed on 5 mil traces with at least 20 mils of space (1:4) between them. This pair should be separated from the rest of the AGP signals (and all other

94 Intel® 815E Chipset Platform Design Guide

AGP/Display Cache Design Guidelines

R

signals) by at least 20 mils (1:4). The strobe pair must be length-matched to less than ±0.1 inch (i.e., a strobe and its complement must be the same length, within 0.1 inch).

7.3.3 AGP Routing Guideline Considerations and Summary

This section applies to all AGP signals in any motherboard support configuration (e.g., “flexible” or “AGP only”): • The 2X/4X timing domain signals can be routed with 5 mil spacing when breaking out of the GMCH. The routing must widen to the documented requirements within 0.3 inches of the GMCH package. • When matching trace lengths for the AGP 4X interface, all traces should be matched from the ball of the GMCH to the pin on the AGP connector. It is not necessary to compensate for the length of the AGP signals on the GMCH package. • Reduce line length mismatch to ensure added margin. The trace length mismatch for all signals within a signal group should be as close as possible to zero, to provide timing margin. • To reduce trace-to-trace coupling (i.e., crosstalk), separate the traces as much as possible. • All signals in a signal group should be routed on the same layer. • The trace length and trace spacing requirements must not be violated by any signal.

Table 23. AGP 2.0 Routing Summary

Signal Maximum Trace Spacing Length Relative To Notes Length (5 Mil Traces) Mismatch

1X Timing 7.5 inches 4 5 mils No N/A None Domain requirement

2X/4X Timing 7.25 inches 4 20 mils ±0.125 inch AD_STB0 AD_STB0 and Domain Set 1 and AD_STB0# must be AD_STB0# the same length.

2X/4X Timing 7.25 inches 4 20 mils ±0.125 inch AD_STB1 AD_STB1 and Domain Set 2 and AD_STB1# must be AD_STB1# the same length.

2X/4X Timing 7.25 inches4 20 mils ±0.125 inch SB_STB SB_STB and Domain Set 3 and SB_STB# must be SB_STB# the same length.

2X/4X Timing 6 inches 3 15 mils1 ±0.5 inch AD_STB0 AD_STB0 and Domain Set 1 and AD_STB0# must be AD_STB0# the same length.

2X/4X Timing 6 inches3 15 mils1 ±0.5 inch AD_STB1 AD_STB1 and Domain Set 2 and AD_STB1# must be AD_STB1# the same length.

2X/4X Timing 6 inches3 15 mils1 ±0.5 inch SB_STB SB_STB and Domain Set 3 and SB_STB# must be SB_STB# the same length.

NOTES: 1. Each strobe pair must be separated from other signals by at least 20 mils. 2. These guidelines apply to board stack-ups with 15% impedance tolerance. 3. 4 inches is the maximum length for flexible motherboards. 4. Solution valid for AGP-only motherboards

Intel® 815E Chipset Platform Design Guide 95

AGP/Display Cache Design Guidelines

R

7.3.4 AGP Clock Routing

The maximum total AGP clock skew, between the GMCH and the graphics component, is 1 ns for all data transfer modes. This 1 ns includes skew and jitter that originates on the motherboard, add- in card, and clock synthesizer. Clock skew must be evaluated not only at a single threshold voltage, but also at all points on a clock edge that falls within in the switching range. The 1 ns skew budget is divided such that the motherboard is allotted 0.9 ns of clock skew. (The motherboard designer must determine how the 0.9 ns is allocated between the board and the synthesizer.)

For the 815E universal platform’s AGP clock routing guidelines, refer to Section 12.3.

7.3.5 AGP Signal Noise Decoupling Guidelines

The following routing guidelines are recommended for an optimal system design. The main focus of these guidelines is to minimize signal integrity problems on the AGP interface of the GMCH. The following guidelines are not intended to replace thorough system validation of products based on the 815E chipset platform: • A minimum of six 0.01 µF capacitors are required and must be as close as possible to the GMCH. These should be placed within 70 mils of the outer row of balls on the GMCH for VDDQ decoupling. The closer the placement, the better. • The designer should evenly distribute the placement of decoupling capacitors within the AGP interface signal field. • It is recommended that the designer use a low-ESL ceramic capacitor (e.g., a 0603 body-type X7R dielectric) • To add the decoupling capacitors within 70 mils of the GMCH and/or close to the vias, the trace spacing may be reduced as the traces go around each capacitor. The narrowing of the space between traces should be minimal and for as short a distance as possible (1 inch max.). • In addition to the minimum decoupling capacitors, the designer should place bypass capacitors at vias that transition the AGP signal from one reference signal plane to another. In a typical four-layer PCB design, the signals transition from one side of the board to the other. One extra 0.01 µF capacitor is required per 10 vias. The capacitor should be placed as close as possible to the center of the via field.

The designer should ensure that the AGP connector is well decoupled, as described in the AGP Design Guide, Revision 1.0, Section 1.5.3.3.

96 Intel® 815E Chipset Platform Design Guide

AGP/Display Cache Design Guidelines

R

Figure 51. AGP Decoupling Capacitor Placement Example

NOTE: This figure is for example purposes only. It does not necessarily represent complete and correct routing for this interface.

7.3.6 AGP Routing Ground Reference

It is strongly recommended that, at a minimum, the following critical signals be referenced to ground from the GMCH to an AGP connector (or to an AGP video controller if implemented as a “down” solution on an AGP-only motherboard), using a minimum number of vias on each net: AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, SB_STB#, G_GTRY#, G_IRDY#, G_GNT#, and ST[2:0].

In addition to the minimum signal set listed previously, it is strongly recommended that half of all AGP signals be reference to ground, depending on board layout. In an ideal design, the entire AGP interface signal field would be referenced to ground. This recommendation is not specific to any particular PCB stack-up, but should be applied to all designs using the 815E chipset platform.

Intel® 815E Chipset Platform Design Guide 97

AGP/Display Cache Design Guidelines

R

7.4 AGP Down Routing Guidelines

The routing guidelines in this section are for AGP down implementations with AGP-compliant devices that are implemented directly on the motherboards, eliminating the need for connectors or add-in cards.

7.4.1 1X AGP Down Option Timing Domain Routing Guidelines

Routing guidelines for an AGP device on the motherboard are very similar to those when the device is implemented with an AGP connector. • AGP 1X timing domain signals (Table 21) have a maximum trace length of 7.5 inches. This maximum applies to ALL signals listed as 1X timing domain signals in Table 24. • All AGP 1X timing domain signals can be routed with 5 mil minimum trace separation • There are no trace length matching requirements for 1X timing domain signals

7.4.2 2X/4X AGP Down Timing Domain Routing Guidelines

These trace length guidelines apply to ALL signals listed in Table 21 as 2X/4X timing domain signals. These signals should be routed using 5 mil (60 Ω) traces. • The maximum AGP 2X/4X signal trace length is 6 inches. • 1:3 trace width-to-spacing is required for AGP 2X/4X timing domain signal traces. • AGP 2X/4X signals must be matched with their associated strobe (as outlined in Table 21), within ±0.5 inch.

For example, if a set of strobe signals (e.g., AD_STB0 and AD_STB0#) is 5.3 inches long, the data signals associated with those strobe signals (e.g., AD[15:0] and C/BE[2:0]#) could be 4.8 inches to 5.8 inches long. Another strobe set (e.g., SB_STB and SB_STB#) could be 4.2 inches long, and the data signals associated with those strobe signals (e.g., SBA[7:0]) could be 3.7 inches to 4.7 inches long.

The strobe signals (AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, and SB_STB#) act as clocks on the source-synchronous AGP interface. Therefore, special care must be taken when routing these signals. Because each strobe pair is truly a differential pair, the pair should be routed together (e.g., AD_STB0 and AD_STB0# should be routed next to each other). The two strobes in a strobe pair should be routed on 5 mil traces with at least 15 mils of space (1:3) between them. This pair should be separated from the rest of the AGP signals and all other signals by at least 20 mils (1:4). The strobe pair must be length-matched to less than ± 0.2 inch (i.e., a strobe and its complement must be the same length, within 0.2 inch).

98 Intel® 815E Chipset Platform Design Guide

AGP/Display Cache Design Guidelines

R

Figure 52. AGP Down 2X/4X Routing Recommendations

Length: 0.5 in. – 6.0 in. Width to Spacing: 1:3 Strobe-to-Data Mismatch: ±0.5 in.

Signals AGP Compliant Graphics GMCH Device

Strobes Length: Dependent on Data Width: 5 mil Spacing: 15 mils Strobe-to-Strobe Mismatch: ±0.2"

AGP_Down_Routing

7.4.3 AGP Routing Guideline Considerations and Summary

This section applies to all AGP signals, as follows: • The 2X/4X timing domain signals can be routed with 5 mil spacing when breaking out of the GMCH. The routing must widen to the documented requirements, within 0.3 inch of the GMCH package. • When matching the trace length for the AGP 4X interface, all traces should be matched from the ball of the GMCH to the ball on the AGP compliant device. It is not necessary to compensate for the lengths of the AGP signals on the GMCH package. • Reduce line length mismatch to ensure added margin. Trace length mismatch for all signals within a signal group should be as close to zero as possible to provide timing margin. • To reduce trace-to-trace coupling (crosstalk), separate the traces as much as possible. • All signals in a signal group should be routed on the same layer. • The trace length and trace spacing requirements must not be violated by any signal.

Intel® 815E Chipset Platform Design Guide 99

AGP/Display Cache Design Guidelines

R

Table 24. AGP 2.0 Down Routing Summary

Signal Max. Trace Spacing Length Relative to Notes Length (5 mil Traces) Mismatch

1X Timing 7.5 5 mils No N/A None Domain inches requirement

2X/4X Timing 6 inches 15 mils1 ±0.5 inch AD_STB0 and AD_STB0, Domain Set 1 AD_STB0# AD_STB0# must be the same length

2X/4X Timing 6 inches 15 mils1 ±0.5 inch AD_STB1 and AD_STB1, Domain Set 2 AD_STB1# AD_STB1# must be the same length

2X/4X Timing 6 inches 15 mils1 ±0.5 inch SB_STB and SB_STB, Domain Set 3 SB_STB# SB_STB# must be the same length

NOTES: 1. Each strobe pair must be separated from other signals by at least 20 mils.

7.4.4 AGP Clock Routing

The maximum total AGP clock skew, between the GMCH and the graphics component, is 1 ns for all data transfer modes. This 1 ns includes skew and jitter that originates on the motherboard, and clock synthesizer. Clock skew must be evaluated not only at a single threshold voltage, but at all points on the clock edge that fall within the switching range. For AGP clock routing guidelines for the 815E chipset platform, refer to Section 12.3.

7.4.5 AGP Signal Noise Decoupling Guidelines

The following routing guidelines are recommended for the optimal system design. The main focus of these guidelines is to minimize signal integrity problems on the AGP interface of the GMCH. The following guidelines are not intended to replace thorough system validation for products based on the 815E chipset platform. • A minimum of six 0.01 µF capacitors are required and must be as close as possible to the GMCH. These should be placed within 70 mils of the outer row of balls on the GMCH for VDDQ decoupling. The closer the placement, the better. • The designer should evenly distribute placement of decoupling capacitors in the AGP interface signal field. • It is recommended that the designer use a low-ESL ceramic capacitor, such as with a 0603 body-type X7R dielectric. • To add the decoupling capacitors within 70 mils of the GMCH and/or close to the vias, the trace spacing may be reduced as the traces go around each capacitor. The narrowing of space between traces should be minimal and for as short a distance as possible (1 inch max.).

100 Intel® 815E Chipset Platform Design Guide

AGP/Display Cache Design Guidelines

R

• In addition to the minimum decoupling capacitors, the designer should place bypass capacitors at vias that transition the AGP signal from one reference signal plane to another. On a typical four-layer PCB design, the signals transition from one side of the board to the other. One extra 0.01 µF capacitor is required per ten vias. The capacitor should be placed as close as possible to the center of the via field.

7.4.6 AGP Routing Ground Reference

It is strongly recommended that at least the following critical signals be referenced to ground from the GMCH to an AGP video controller on an AGP-only motherboard using a minimum number of vias on each net: AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, SB_STB#, G_GTRY#, G_IRDY#, G_GNT#, and ST[2:0].

In addition to this minimum signal set, it is strongly recommended that half of all AGP signals be referenced to ground, depending on the board layout. In an ideal design, the complete AGP interface signal field would be referenced to ground. This recommendation is not specific to any particular PCB stack-up, but should be applied to all 815E chipset platform designs.

7.5 AGP 2.0 Power Delivery Guidelines

7.5.1 VDDQ Generation and TYPEDET#

AGP specifies two separate power planes: VCC and VDDQ. VCC is the core power for the graphics controller. This voltage is always 3.3 V. VDDQ is the interface voltage. In AGP 1.0 implementations, VDDQ also was 3.3 V. For the designer developing an AGP 1.0 motherboard, there is no distinction between VCC and VDDQ, since both are tied to the 3.3V power plane on the motherboard.

AGP 2.0 requires that these power planes be separate. In conjunction with the 4X data rate, the AGP 2.0 Interface Specification provides for low-voltage (1.5V) operation. The AGP 2.0 specification implements a TYPEDET# (type detect) signal on the AGP connector that determines the operating voltage of the AGP 2.0 interface (VDDQ). The motherboard must provide either 1.5 V or 3.3 V to the add-in card, depending on the state of the TYPEDET# signal (see Table 25). 1.5 V low-voltage operation applies only to the AGP interface (VDDQ). VCC is always 3.3 V.

Note: The motherboard provides 3.3V to the VCC pins of the AGP connector. If the graphics controller needs a lower voltage, then the add-in card must regulate the 3.3VCC voltage to the controller’s requirements. The graphics controller may only power AGP I/O buffers with the VDDQ power pins.

The TYPEDET# signal indicates whether the AGP 2.0 interface operates at 1.5 V or 3.3 V. If TYPEDET# is floating (i.e., No Connect) on an AGP add-in card, the interface is 3.3 V. If TYPEDET# is shorted to ground, the interface is 1.5 V.

Intel® 815E Chipset Platform Design Guide 101

AGP/Display Cache Design Guidelines

R

Table 25. TYPDET#/VDDQ Relationship

TYPEDET# (on Add-in Card) VDDQ (Supplied by MB)

GND 1.5 V

N/C 3.3 V

As a result of this requirement, the motherboard must provide a flexible voltage regulator or key the slot to preclude add-in cards with voltage requirements incompatible with the motherboard. This regulator must supply the appropriate voltage to the VDDQ pins on the AGP connector. For specific design recommendations, refer to the schematics in Appendix A. VDDQ generation and AGP VREF generation must be considered together. Before developing VDDQ generation circuitry, refer to Section 7.5.1 and the AGP 2.0 Interface Specification.

Figure 53. AGP VDDQ Generation Example Circuit

+3.3V VDDQ

+12V C2 47 µF

U1 LT1575 1 8 SHDN IPOS 5 2 7 C3 220 µF VIN INEG R2 3 GND GATE 6 R1 2.2 kΩ 1 µF 4 5 C1 FB COMP

10 pF

.001 µF C4 R5

Ω C5 7.5 k - 1%

301 - 1% R3

TYPEDET#

1.21 kΩ - 1% R4

AGP_VDDQ_gen_ex_circ

Figure 53 demonstrates one way to design the VDDQ voltage regulator. This regulator is a linear regulator with an external, low-Rdson FET. The source of the FET is connected to 3.3V. This regulator converts 3.3V to 1.5V or passes 3.3V, depending on the state of TYPEDET#. If a linear regulator is used, it must draw power from 3.3V (not 5V) to control thermals. (i.e., 5V regulated down to 1.5V with a linear regulator will dissipate approximately 7 W at 2 A.) Because it must draw power from 3.3V and, in some situations, must simply pass that 3.3V to VDDQ (when a 3.3V add-in card is placed in the system), the regulator MUST use a low-Rdson FET.

AGP 1.0 ECR #44 modified VDDQ 3.3min to 3.1 V. When an ATX power supply is used, the 3.3 Vmin is 3.168. Therefore, 68 mV of drop is allowed across the FET at 2 A. This corresponds to an FET with an Rdson of 34 mΩ.

102 Intel® 815E Chipset Platform Design Guide

AGP/Display Cache Design Guidelines

R

How does the regulator switch? The feedback resistor divider is set to 1.5 V. When a 1.5 V card is placed in the system, the transistor is off and the regulator regulates to 1.5 V. When a 3.3 V card is placed in the system, the transistor is on, and the feedback will be pulled to ground. When this happens, the regulator will drive the gate of the FET to nearly 12 V. This will turn on the FET and pass 3.3 V – 2 A * Rdson to VDDQ.

7.5.2 VREF Generation for AGP 2.0 (2X and 4X)

VREF generation for AGP 2.0 is different, depending on the AGP card type used. The 3.3 V AGP cards generate VREF locally. That is, they have a resistor divider on the card that divides VDDQ down to VREF (see Figure 54). To account for potential differences between VDDQ and GND at the GMCH and graphics controller, 1.5V cards use source-generated VREF. That is, the VREF signal is generated at the graphics controller and sent to the GMCH, and another VREF is generated at the GMCH and sent to the graphics controller (see Figure 54).

Both the graphics controller and the GMCH must generate VREF and distribute it through the connector (1.5V add-in cards only). The following two pins defined on the AGP 2.0 universal connector allow this VREF passing:

• VREFGC VREF from the graphics controller to the chipset • VREFCG VREF from the chipset to the graphics controller

To preserve the common-mode relationship between the VREF and data signals, the routing of the two VREF signals must be matched in length to the strobe lines, within 0.5 inch on the motherboard and within 0.25 inch on the add-in card.

The voltage divider networks consist of AC and DC elements, as shown in Figure 54.

The VREF divider network should be placed as close as practical to the AGP interface, to get the benefit of the common-mode power supply effects. However, the trace spacing around the VREF signals must be a minimum of 25 mils to reduce crosstalk and maintain signal integrity.

During 3.3V AGP 2.0 operation, VREF must be 0.4 VDDQ. However, during 1.5V AGP 2.0 operation, VREF must be 0.5 VDDQ. This requires a flexible voltage divider for VREF. Various methods of accomplishing this exist, and one such example is shown in Figure 54.

Intel® 815E Chipset Platform Design Guide 103

AGP/Display Cache Design Guidelines

R

Figure 54. AGP 2.0 VREF Generation and Distribution

a) 1.5V AGP Card +12V

R7 (See note 2) 1 KΩ R9 VDDQ 1.5V AGP 300 Ω 1% TYPEDET# Card C8 R2 VrefGC 500 pF 200 Ω 1%

R6 R5 U6 VDDQ 1 KΩ 82 Ω GMCH REF mosfet C9 VDDQ GND R2 R4 0.1 uF Ω AGP REF 1 KΩ 82 Device GND C9 500 pF

VrefCG

Notes: 1. The resistor dividers should be placed near the GMCH. The AGPREF signal must be 5 mils wide and routed 10 mils from adjacent signals. 2. R7 is the same resistor seen in AGP VDDQ generation example circuit figure (R1)

b) 3.3V AGP Card

+12V R7 (See note 2) 1 KΩ R9 Ω 3.3V AGP TYPEDET# 300 VDDQ 1% Card C8 R2 500 pF VrefGC 200 Ω 1%

R6 R5 U6 1 KΩ 82 Ω VDDQ VDDQ AGP REF GMCH Device REF mosfet C10 R2 GND R4 GND 0.1 uF 1 KΩ 82 Ω

C9 500 pF

VrefCG

The resistor dividers should be placed near the GMCH. The AGPREF signal must be 5 mils wide and routed 25 mils from adjacent signals.

agp_2.0ref_gen_dist

The flexible VREF divider shown in Figure 54 uses a FET switch to switch between the locally generated VREF (for 3.3V add-in cards) and the source-generated VREF (for 1.5V add-in cards).

Use of the source-generated VREF at the receiver is optional and is a product implementation issue beyond the scope of this document.

104 Intel® 815E Chipset Platform Design Guide

AGP/Display Cache Design Guidelines

R

7.6 Additional AGP Design Guidelines

7.6.1 Compensation

The GMCH AGP interface supports resistive buffer compensation (RCOMP). Tie the GRCOMP pin to a 40 Ω, 2% (or 39 Ω, 1%) pull-down resistor (to ground) through a 10 mil-wide, very short (<0.5 inch) trace.

7.6.2 AGP Pull-Ups

AGP control signals require pull-up resistors to VDDQ on the motherboard, to ensure that they contain stable values when no agent is actively driving the bus. The pull-up/pull-down resistor value requirements are Rmin = 4 kΩ and Rmax = 16 kΩ. The recommended AGP pull-up/pull- down resistor value is 8.2 kΩ.

1X Timing Domain Signals Requiring Pull-uUp Resistors The following bullets list the 1X timing domain signals that require pull-up resistors.

• FRAME# • PERR# • TRDY# • RBF# • IRDY# • PIPE# • DEVSEL# • REQ# • STOP# • WBF# • SERR# • GNT# • ST[2:0]

Note: It is critical that these signals be pulled up to VDDQ, not 3.3 V.

The trace stub to the pull-up resistor on 1X timing domain signals should be kept shorter than 0.5 inch to avoid signal reflections from the stub.

Note: INTA# and INTB# should be pulled to 3.3 V, not VDDQ.

2X/4X Timing Domain Signals Requiring Pull-Up/Pull-Down Resistors The following bullets list the 2X/4X timing domain signals that require pull-up/pull-down resistors. The strobe signals require pull-up/pull-downs on the motherboard to ensure that they are at a stable level when no agent is driving the bus. • AD_STB[1:0] Pull-Up to VDDQ • SB_STB Pull up to VDDQ • AD_STB[1:0]# Pull Down to Ground • SB_STB# Pull Down to Ground

The trace stub to the pull-up/pull-down resistor on 2X/4X timing domain signals should be kept shorter than 0.1 inch to avoid signal reflections from the stub.

Intel® 815E Chipset Platform Design Guide 105

AGP/Display Cache Design Guidelines

R

7.6.2.1 AGP Signal Voltage Tolerance List

The following signals on the AGP interface are 3.3 V tolerant during 1.5 V operation: • PME# • INTA# • INTB# • GPERR# • GSERR# • CLK • RST

The following signals on the AGP interface are 5 V tolerant (see USB specification): • USB+ • USB- • OVRCNT#

The following signal is a special AGP signal. It is either grounded or left as a no connect on an AGP card. • TYPEDET#

Note: All other signals on the AGP interface are in the VDDQ group. They are not 3.3 V tolerant during 1.5 V AGP operation!

7.7 Motherboard / Add-in Card Interoperability

There are three AGP connectors: 3.3 V AGP connector, 1.5 V AGP connector, and Universal AGP connector. To maximize add-in flexibility, it is highly advisable to implement the universal connector in systems based on the 815E platform. All add-in cards are either 3.3 V or 1.5 V cards. The 4X transfers at 3.3 V are not allowed due to timings.

Table 26. Connector/Add-in Card Interoperability

Card 1.5V Connector 3.3V Connector Universal Connector

1.5V card Yes No Yes

3.3V card No Yes Yes

Table 27. Voltage/Data Rate Interoperability

Voltage 1X 2X 4X

1.5 V VDDQ Yes Yes Yes

3.3 V VDDQ Yes Yes No

106 Intel® 815E Chipset Platform Design Guide

AGP/Display Cache Design Guidelines

R

7.8 AGP / Display Cache Shared Interface

As described earlier, the AGP and display cache interfaces of the 815E chipset platform are multiplexed or shared. In other words, the same component pins (balls) are used for both interfaces, although obviously only one interface can be supported at any given time. As a result, almost all display cache interface signals are mapped onto the new AGP interface. The 815E platform can be configured in either AGP mode or Graphics mode. In the AGP mode, the interface supports a full AGP 4X interface. In the Graphics mode, the interface becomes a display cache interface similar to the Intel® 810E chipset. Note, however, that in the Graphics mode, the display cache is optional. There do not have to be any SDRAM devices connected to the interface. The only dedicated display cache signals are OCLK and RCLK, which need not connect directly to the SDRAM devices. These are not mapped onto existing AGP signals.

7.8.1 GPA Card Considerations

To support the fullest flexibility, the display cache exists on an add-in card (Graphics Performance Accelerator, or GPA) that complies with the AGP connector form factor. If the motherboard designer follows the flexible routing guidelines for the AGP interface detailed in previous sections, the customer can choose to populate the AGP slot in a system based on the 815E chipset with either an AGP graphics card, with a GPA card to enable the highest-possible internal graphics performance, or with nothing to get the lowest-cost internal graphics solution. Some of the GPA/ 815E chipset platform interfacing implications are listed below. For a complete description of the GPA card design, refer to the Graphics Performance Accelerator Card Specification available from Intel. • A strap is required to determine which frequency to select for display cache operation. This is the L_FSEL pin of the GMCH. The GPA card will pull this signal up or down as appropriate to communicate to the 815E chipset platform the appropriate operating frequency. The 815E chipset platform will sample this pin on the deasserting edge of reset. • Since current SDRAM technology is always 3.3 V rather than the 1.5V option also supported by AGP, the GPA card should set the TYPEDET# signal correctly to indicate that it requires a 3.3V power supply. Furthermore, the GPA card should have only the 3.3V key and not the 1.5V key, thereby preventing it from being inserted into a 1.5V-only connector. • The pad buffers on the chip will be the normal AGP buffers and will work for both interfaces. • In internal graphics mode, the AGPREF signal, which is required for the AGP mode, should remain functional as a reference voltage for sampling 3.3V LMD inputs. The voltage level on AGPREF should remain exactly the same as in the AGP mode, as opposed to the VCC/2 used for previous products.

7.8.1.1 AGP and GPA Mechanical Considerations

The GPA card will be designed with a notch on the PCB to go around the AGP universal retention mechanism. To guarantee that the GPA card will meet all shock and vibration requirements of the system, the AGP universal retention mechanism will be required on all AGP sockets that are to support a GPA card.

Intel® 815E Chipset Platform Design Guide 107

AGP/Display Cache Design Guidelines

R

7.8.2 Display Cache Clocking

The display cache is clocked source-synchronously from a clock generated by the GMCH. The display cache clocking scheme uses three clock signals. • LTCLK clocks the SDRAM devices, is muxed with an AGP signal, and should be routed according to the flexible AGP guidelines. • LOCLK and LRCLK clock the input buffers of the universal platform. LOCLK is an output of the GMCH and is a buffered copy of LTCLK. LOCLK should be connected to LRCLK at the GMCH, with a length of PCB trace to create the appropriate clock skew relationship between the clock input (LRCLK) and the SDRAM capacitor clock input(s).

The guidelines are illustrated in Figure 55.

Figure 55. Display Cache Input Clocking

82815

15 Ω , 1% LOCLK 0.5"

LRCLK 1.5"

15 pF, 5% NPO

AGP_Display_Cache_Input_clock_815E_B0

The capacitor should be placed as close as possible to the GMCH LRCLK pin. To minimize skew variation, we recommend a 1% series termination resistor and a 5% NPO capacitor, to stabilize the value across temperatures. In addition to the 15 Ω, 1% resistor and the 15 pF, 5% NPO capacitor. The following combination also can be used: 10 Ω, 1% and 22 pF, 5% NPO.

7.9 Designs That Do Not Use the AGP Port

Intel 815E chipset platform designs that do not use the AGP port should terminate the AGP pins of the GMCH. Except for the GPAR pin (which requires a 100 kΩ pull down resistor to ground), the pull-up or pull-down resistor value should be 8.2 kΩ. Any external graphics implementation not using the AGP port should terminate the GMCH AGP control and strobe signals as recommended in Section 14.3.2.

108 Intel® 815E Chipset Platform Design Guide

Integrated Graphics Display Output

R

8 Integrated Graphics Display Output

8.1 Analog RGB/CRT

8.1.1 RAMDAC/Display Interface

Figure 56 shows the interface of the RAMDAC analog current outputs with the display. Each DAC output is doubly terminated with a 75 Ω resistance. One 75 Ω resistance is from the DAC output to the board ground and the other termination resistance exists within the display. The equivalent DC resistance at the output of each DAC output is 37.5 Ω. The output current of each DAC flows into this equivalent resistive load to produce a video voltage without the need for external buffering. There is also an LC pi-filter that is used to reduce high-frequency glitches and noise and to reduce EMI. To maximize performance, the filter impedance, cable impedance, and load impedance should be the same. The LC pi-filter consists of two 3.3 pF capacitors and a ferrite bead with a 75 Ω impedance at 100 MHz. The LC pi-filter is designed to filter glitches produced by the RAMDAC while maintaining adequate edge rates to support high-end display resolutions.

Intel® 815E Chipset Platform Design Guide 109

Integrated Graphics Display Output

R

Figure 56. Schematic of RAMDAC Video Interface

Graphics Board Termination resistor, R 75 Ω 1% Display PLL power Analog (metal film) connects to this power plane segmented power 1.85 V Lf Diodes D1, D2: Schottky diodes plane 1.85 V board power plane LC filter capacitors, C1, C2: 3.3 pF 1.85 V board LC power plane Cf Filter Ferrite bead, FB: 7 Ω @ 100 MHz (Recommended part: Murata 1.85 V board BLM11B750S) power plane Graphics D1 Chip FB VCCDACA1/ VCCDA Red VCCDACA2 C1 C2 Rt D2

RAMDAC Pi filter Coax Cable 1.85 V board Zo = 75 Ω Display power plane Pixel Red clock D1 (from FB 75 Ω Green DPLL) Video Green connector Blue 75 Ω C1 C2 Rt D2

75 Ω Pi filter 1.85 V board power plane

D1 FB

Blue

C1 C2 Rt D2

IWASTE IREF VSSDACA Pi filter

Rset 1% reference current resistor (metal film)

Ground plane

display_RAMDAC_video_IF

NOTE: Diodes D1, D2 are clamping diodes with low leakage and low capacitive loading. An example is: California Micro Devices PAC DN006 (6 channel ESD protection array).

In addition to the termination resistance and LC pi-filter, there are protection diodes connected to the RAMDAC outputs to help prevent latch-up. The protection diodes must be connected to the same power supply rails as the RAMDAC. An LC filter is recommended for connecting the segmented analog 1.85V power plane of the RAMDAC to the 1.85V board power plane. The LC filter should be designed for a cut-off frequency of 100 kHz.

110 Intel® 815E Chipset Platform Design Guide

Integrated Graphics Display Output

R

8.1.2 Reference Resistor (Rset) Calculation

The full-swing video output is designed to be 0.7 V, according to the VESA video standard. With an equivalent DC resistance of 37.5 Ω (two 75 Ω resistors in parallel; one 75 Ω termination on the board and one 75 Ω termination within the display), the full-scale output current of a RAMDAC channel is 0.7/37.5 Ω = 18.67 mA. Since the RAMDAC is an 8-bit current-steering DAC, this full- scale current is equivalent 255 I, where I is a unit current. Therefore, the unit current or LSB current of the DAC signals equals 73.2 µA. The reference circuitry generates a voltage across this Rset resistor equal to the bandgap voltage divided by three (i.e., 407.6 mV). The RAMDAC reference current generation circuitry is designed to generate a 32-I reference current using the reference voltage and the Rset value. To generate a 32-I reference current for the RAMDAC, the reference current setting resistor, Rset, is calculated from the following equation:

Rset = VREF / 32*I = 0.4076 V / 32 * 73.2 µA = 174 Ω

8.1.3 RAMDAC Board Design Guidelines

Figure 57 shows a general cross section of a typical four-layer board. The recommended RAMDAC routing for a four-layer board is such that the red, green, and blue video outputs are routed on the top (bottom) layer over (under) a solid ground plane to maximize the noise rejection characteristics of the video outputs. It is essential to prevent toggling signals from being routed next to the video output signals to the VGA connector. A 20 mil spacing between any video route and any other route is recommended.

Figure 57. Cross-Sectional View of a Four-Layer Board

Board Cross Section Avoid clock routes or high-frequency routes in Top of board the area of the RAMDAC output signals and Graphics chip Video reference resistor. connector One solid, continuous ground plane Board RAMDAC / PLL circuitry components Analog traces

Ground plane

Low-frequency signal traces

Digital power plane Segmented analog power Bottom of board plane for RAMDAC / PLL

RAMDAC_board_xsec

Matching of the video routes (i.e., red, green, blue) from the RAMDAC to the VGA connector is also essential. The routing for these signals should be as similar as possible (i.e., same routing layer(s), same number of vias, same routing length, same bends, and jogs).

Intel® 815E Chipset Platform Design Guide 111

Integrated Graphics Display Output

R

Figure 58 shows the recommended RAMDAC component placement and routing. The termination resistance can be placed anywhere along the video route from the RAMDAC output to the VGA connector, as long as the trace impedances are designed as indicated in Figure 58. It is advisable to place the pi-filters in close proximity with the VGA connector, to maximize the EMI filtering effectiveness. The LC filter components for the RAMDAC/PLL power plane, the decoupling capacitors, the latch-up protection diodes, and the reference resistor should be placed in close proximity with the respective pins. Figure 59 shows the recommended reference resistor placement and the ground connections.

Figure 58. Recommended RAMDAC Component Placement and Routing

Place LC filter components and high-frequency decoupling Analog capacitors as close as possible power plane to power pins 1.85 V Lf 1.85 V board power plane 1.85 V board LC power plane Cf filter Place pi filter near VGA connector

1.85 V board power plane Graphics 75 Ω routes Chip D1 FB VCCDACA1/ 37.5 Ω route VCCDA Red VCCDACA2 Red route C1 C2 D2 Rt

RAMDAC Pi filter 1.85 V board Pixel power plane clock 75 Ω routes D1 (from FB Ω DPLL) 37.5 route VGA Green Green route C1 C2 D2 Rt

Pi filter 1.85 V board power plane 75 Ω routes D1 FB 37.5 Ω route Blue Blue route C1 C2 D2 Rt

IWASTE IREF VSSDACA Pi filter Place diodes close to RGB pins Avoid routing Rset Place reference toggling signals in resistor near IREF pin this shaded area

- Match the RGB routes - Space between the RGB routes a min. of 20 mils Via straight down to the ground plane RAMDAC_comp_placement_routing

NOTE: Diodes D1, D2 are clamping diodes with low leakage and low capacitive loading. An example is: California Micro Devices PAC DN006 (6 channel ESD protection array).

112 Intel® 815E Chipset Platform Design Guide

Integrated Graphics Display Output

R

Figure 59. Recommended RAMDAC Reference Resistor Placement and Connections

Graphics Chip IREF ball/pin

Position resistor near IREF pin. Short, wide route connecting resistor to IREF pin

No toggling signals should be routed Resistor for setting RAMDAC reference current Rset near Rset resistor. 178 Ω, 1%, 1/16 W, SMT, metal film

Large via or multiple vias straight down to ground plane

RAMDAC_ref_resistor_place_conn

8.1.4 RAMDAC Layout Recommendations

• The primary concern with regard to the RGB signal length is that the RGB routes are matched and routed with the correct impedance. The impedance should be 37.5 Ω, single-ended trace to the 75-ohm, termination resistor. Routing from the 75 Ω resistor to the video PI-filter and to the VGA connector should be 75 Ω impedance. • The trace width for the RGB signal should be selected for a 37.5 Ω impedance (single-ended route) to the 75 Ω termination resistor. The 75 Ω termination resistor should be placed near the VGA connector. • The spacing for each DAC channel routing (i.e., between red & green, green & blue outputs) should be a minimum of 20 mils. • The space between the RGB signal route and other routes should be a minimum of 20 mils for each DAC route. • All RGB signals should be referenced to ground. • The trace width for the HSYNC and VSYNC signal routes should be selected for an approximately 40 Ω impedance. • The spacing between the HSYNC /VSYNC signal routes should be at least 10 mils, preferably 20 mils. • The space between HSYNC/VSYNC signal routes and others routes should be at least 10 mils, preferably 20 mils. • Route the HSYNC and VSYNC over the ground plane, if possible. The HSYNC and VSYNC signals should not route over or near any clock signals or any other high switching routing.

8.1.5 HSYNC/VSYNC Output Guidelines

The Hsync and Vsync output of the GMCH may exhibit up to 1.26V P-P noise when driven high under high traffic system memory conditions. To minimize this, the following is required. • Add External Buffers to Hsync and Vsync.  Examples include: Series 10 Ω resistor with a 74LVC08

Intel® 815E Chipset Platform Design Guide 113

Integrated Graphics Display Output

R

8.2 Digital Video Out

The Digital Video Out (DVO) port is a scaleable, low-voltage interface that ranges from 1.1 V to 1.8 V. This DVO port interfaces with a discrete TV encoder to enable platform support for TV-Out, with a discrete TMDS transmitter to enable platform support for DVI-compliant digital displays, or with an integrated TV encoder and TMDS transmitter.

2 The GMCH DVO port controls the video front-end devices via an I C interface, by means of the LTVDA and LTVCK pins. I2C is a two-wire communications bus/protocol. The protocol and bus are used to collect EDID (extended display identification) from a digital display panel and to detect and configure registers in the TV encoder or TMDS transmitter chips.

8.2.1 DVO Interface Routing Guidelines

Route data signals (LTVDATA[11:0]) with a trace width of 5 mils and a trace spacing of 20 mils. These signals can be routed with a trace width of 5 mils and a trace spacing of 15 mils for navigation around components or mounting holes. To break out of the GMCH, the DVO data signals can be routed with a trace width of 5 mils and a trace spacing of 5 mils. The signals should be separated to a trace width of 5 mils and a trace spacing of 20 mils , within 0.3 inch of the GMCH component. The maximum trace length for the DVO data signals is 7 inches. These signals should each be matched within ±0.1 inch of the LTVCLKOUT[1] and LTVCLKOUT[0] signals.

Route the LTVCLKOUT[1:0] signals 5 mils wide and 20 mils apart. This signal pair should be a minimum of 20 mils from any adjacent signals. The maximum length for LTVCLKOUT[1:0] is 7 inches and the two signals should be the same length.

8.2.2 DVO I2C Interface Considerations

LTVDA and LTVCK should be connected to the TMDS transmitter, TV encoder or integrated TMDS transmitter/TV encoder device, as required by the specifications for those devices. LTVDA and LTVCK also should be connected to the DVI connector as specified by the DVI specification. Pull-up resistors of 4.7 kΩ (or pull-ups with the appropriate value derived from simulation) are required on both LTVDA and LTVCK.

8.2.3 Leaving the DVO Port Unconnected

If the motherboard does not implement any of the possible video devices with the 815E chipset universal platform’s DVO port, the following are recommended on the motherboard: • Pull up LTVDA and LTVCK with 4.7 kΩ resistors at the GMCH. This will prevent the GMCH’s DVO controller from confusing noise on these lines with false I2C cycles. • Route LTVDATA[11:0] and LTVCLKOUT[1:0] out of the BGA to test points for use by automated test equipment (if required). These signals are part of one of the GMCH XOR chains.

114 Intel® 815E Chipset Platform Design Guide

Hub Interface

R

9 Hub Interface

The GMCH ball assignment and ICH2 ball assignment have been optimized to simplify hub interface routing. It is recommended that the hub interface signals be routed directly from the GMCH to the ICH2 on the top signal layer. Refer to Figure 60.

The hub interface is divided into two signal groups: data signals and strobe signals. • Data Signals:  HL[10:0] • Strobe Signals:  HL_STB  HL_STB#

Note: HL_STB/HL_STB# is a differential strobe pair.

No pull-ups or pull-downs are required on the hub interface. HL11 on the ICH2 should be brought out to a test point for NAND Tree testing. Each signal should be routed such that it meets the guidelines documented for its signal group.

Figure 60. Hub Interface Signal Routing Example

NAND tree test point HL_STB HL11 HL_STB# ICH2 GMCH

HL[10:0]

CLK66 GCLK

Clocks

hub_link_sig_routing

Intel® 815E Chipset Platform Design Guide 115

Hub Interface

R

9.1.1 Data Signals

Hub interface data signals should be routed with a trace width of 5 mils and a trace spacing of 20 mils. These signals can be routed with a trace width of 5 mils and a trace spacing of 15 mils for navigation around components or mounting holes. To break out of the GMCH and the ICH2, the hub interface data signals can be routed with a trace width of 5 mils and a trace spacing of 5 mils. The signals should be separated to a trace width of 5 mils and a trace spacing of 20 mils, within 0.3 inch of the GMCH/ICH2 components.

The maximum trace length for the hub interface data signals is 8 inches. These signals should each be matched within ±0.1 inch of the HL_STB and HL_STB# signals.

9.1.2 Strobe Signals

Due to their differential nature, the hub interface strobe signals should be 5 mils wide and routed 20 mils apart. This strobe pair should be a minimum of 20 mils from any adjacent signals. The maximum length for the strobe signals is 8 inches, and the two strobes should be the same length. Additionally, the trace length for each data signal should be matched to the trace length of the strobes, within ±0.1 inch.

9.1.3 HREF Generation/Distribution

HREF, the hub interface reference voltage, is 0.5 * 1.85 V = 0.92 V ± 2%. It can be generated using a single HREF divider or locally generated dividers (as shown Figure 61 and Figure 62). The resistors should be equal in value and rated at 1% tolerance, to maintain 2% tolerance on 0.92 V. The values of these resistors must be chosen to ensure that the reference voltage tolerance is maintained over the entire input leakage specification. The recommended range for the resistor value is from a minimum of 100 Ω to a maximum of 1 kΩ (300 Ω shown in example).

The single HREF divider should not be located more than 4 inches away from either GMCH or ICH2. If the single HREF divider is located more than 4 inches away, then the locally generated hub interface reference dividers should be used instead.

The reference voltage generated by a single HREF divider should be bypassed to ground at each component with a 0.01 µF capacitor located close to the component HREF pin. If the reference voltage is generated locally, the bypass capacitor must be close to the component HREF pin.

116 Intel® 815E Chipset Platform Design Guide

Hub Interface

R

9.1.4 Compensation

Independent hub interface compensation resistors are used by the GMCH and ICH2 to adjust buffer characteristics to specific board characteristics. Refer to the Intel® 815 Chipset Family: 82815 Graphics and Memory Controller Hub (GMCH) for use with the Universal Socket 370 Datasheet and the Intel® 82801BA I/O Controller Hub (ICH2) and Intel® 82801BAM I/O Controller Hub (ICH2-M) Datasheet for details on compensation. The resistive Compensation (RCOMP) guidelines are as follows: • RCOMP: Tie the HLCOMP pin of each component to a 40 Ω, 1% or 2% pull-up resistor (to 1.8 V) via a 10 mil-wide, 0.5 inch trace (targeted at a nominal trace impedance of 40 Ω). The GMCH and ICH2 each require its own RCOMP resistor.

Figure 61. Single Hub Interface Reference Divider Circuit

1.85 V

300 Ω GMCH ICH2

HUBREF HUBREF

0.01 µF 0.01 µF

Ω 300 0.1 µF

hub_IF_ref_div_1_815E_B0

Figure 62. Locally Generated Hub Interface Reference Dividers

1.85 V 1.85 V

Ω Ω GMCH 300 300 ICH2

HUBREF HUBREF

0.1 µF 300 Ω 300 Ω 0.1 µF

hub_IF_ref_div_2_B0

Intel® 815E Chipset Platform Design Guide 117

Hub Interface

R

This page is intentionally left blank.

118 Intel® 815E Chipset Platform Design Guide

I/O Controller Hub 2 (ICH2)

R

10 I/O Controller Hub 2 (ICH2)

10.1 Decoupling

The ICH2 is capable of generating large current swings when switching between logic high and logic low. This condition could cause the component voltage rails to drop below specified limits. To avoid this type of situation, ensure that the appropriate amount of bulk capacitance is added in parallel to the voltage input pins. It is recommended that the developer use the amount of decoupling capacitors specified in Table 28 to ensure that the component maintains stable supply voltages. The capacitors should be placed as close as possible to the package, without exceeding 400 mils (200 mils nominal).

Note: Routing space around the ICH2 is tight. A few decoupling caps may be placed more than 300 mils away from the package. System designers should simulate the board to ensure that the correct amount decoupling is implemented. Refer to Figure 63 for a layout example, with the decoupling capacitors circled with an arrow showing which power plane/trace they are connected to. Intel recommends that, for prototype board designs, the designer include pads for extra power plane decoupling capacitors.

Table 28. Decoupling Capacitor Recommendation

Power Plane/Pins Decoupling Capacitors Capacitor Value

3.3V core 6 0.1 µF

3.3V standby 1 0.1 µF

Processor interface (1.3 ~ 2.5 V) 1 0.1 µF

1.85V core 2 0.1 µF

1.85V standby 1 0.1 µF

5V reference 1 0.1 µF

5V reference standby 1 0.1 µF

Intel® 815E Chipset Platform Design Guide 119

I/O Controller Hub 2 (ICH2)

R

Figure 63. Intel® ICH2 Decoupling Capacitor Layout

3.3V Core 1.85V Core

1.85V Standby

3.3V Standby 1.85V Standby 3.3V Core

5V Ref decouple_cap_layo

10.2 1.85 V/3.3 V Power Sequencing

The ICH2 has two pairs of associated 1.85 V and 3.3 V supplies. These are, {VCC1_85, VCC3_3} and {VCCSus1_85, VCCSus3_3}. These pairs are assumed to power up and power down together. The difference between the two associated supplies must never be greater than 2.0V. The 1.85V supply may come up before the 3.3V supply without violating this rule (though this is generally not practical in a desktop environment, since the 1.85V supply is typically derived from the 3.3V supply by means of a linear regulator).

One serious consequence of violation of the 2V Rule is electrical overstress of oxide layers, resulting in component damage.

The majority of the ICH2 I/O buffers are driven by the 3.3V supplies, but are controlled by logic that is powered by the 1.85V supplies. Thus, another consequence of faulty power sequencing arises if the 3.3V supply comes up first. In this case the I/O buffers will be in an undefined state until the 1.85V logic is powered up. Some signals that are defined as "Input-only" actually have output buffers that are normally disabled, and the ICH2 may unexpectedly drive these signals if the 3.3V supply is active while the 1.85V supply is not.

Figure 64 shows an example power-on sequencing circuit that ensures the 2V Rule is obeyed. This circuit uses a NPN (Q2) and PNP (Q1) transistor to ensure the 1.85V supply tracks the 3.3V supply. The NPN transistor controls the current through PNP from the 3.3V supply into the 1.85V

120 Intel® 815E Chipset Platform Design Guide

I/O Controller Hub 2 (ICH2)

R

power plane by varying the voltage at the base of the PNP transistor. By connecting the emitter of the NPN transistor to the 1.85V plane, current will not flow from the 3.3V supply into 1.85V plane when the 1.85V plane reaches 1.85V.

Figure 64. 1.85V/3.3V Power Sequencing Circuit Example

+3.3V +1.85V

220

Q2 Q1 220 NPN PNP

470

When analyzing systems that may be "marginally compliant" to the 2V Rule, pay close attention to the behavior of the ICH2's RSMRST# and PWROK signals, since these signals control internal isolation logic between the various power planes: • RSMRST# controls isolation between the RTC well and the Resume wells. • PWROK controls isolation between the Resume wells and Main wells

If one of these signals goes high while one of its associated power planes is active and the other is not, a leakage path will exist between the active and inactive power wells. This could result in high, possibly damaging, internal currents.

10.3 Power Sequencing on Wake Events

For systems providing functionality with 0.13 micron socket 370 processors, special handling of wake events is required. When a wake event is triggered, the GMCH and the CK815 must not sample BSEL[1:0] until the signal VTTPWRGD is asserted. This is handled by setting up the following sequence of events: 1. Power is not connected to the CK815-compliant clock driver until schematic signal VTTPWRGD12 is asserted. 2. Clocks to the ICH2 stabilize before the power supply asserts PWROK to the ICH2. There is no guarantee this will occur as the implementation for the previous step relies on the 12V supply. Thus, it is necessary to gate PWROK to the ICH2 from the power supply while the CK815 is given sufficient time for the clocks to become stable. The amount of time required is a minimum 20 ms. 3. ICH2 takes the GMCH out of reset. 4. GMCH samples BSEL[1:0]. (CK815 will have sampled BSEL[1:0] much earlier.)

Refer to Section 4.3 for full implementation details.

Intel® 815E Chipset Platform Design Guide 121

I/O Controller Hub 2 (ICH2)

R

10.4 Power Plane Splits

Figure 65. Power Plane Split Example

pwr_plane_splits

10.5 Power Supply PS_ON Considerations

If a pulse on SLP_S3# or SLP_S5# is short enough (~ 10–100 mS) such that PS_ON is driven active during the exponential decay of the power rails, a few power supplies may not be designed to handle this short pulse condition. In this case, the power supply will not respond to this event and never power back up. These power supplies would need to be unplugged and re-plugged to bring the system back up. Power supplies not designed to handle this condition must have their power rails decay to a certain voltage level before they can properly respond to PS_ON. This level varies with affected power supply.

The ATX spec does not specify a minimum pulse width on PS_ON de-assertion, which means power supplies must be able to handle any pulse width. This issue can affect any power supply (beyond ATX) with similar PS_ON circuitry. Due to variance in the decay of the core power rails per platform, a single board or chipset silicon fix would be non-deterministic (may not solve the issue in all cases).

The platform designer must ensure that the power supply used with the platform is not affected by this issue.

122 Intel® 815E Chipset Platform Design Guide

I/O Subsystem

R

11 I/O Subsystem

This chapter provides guidelines for connecting and routing the IDE, AC ’97, USB, IO-APIC, SMBus, PCI, LPC/FWH, and RTC subsystems.

11.1 IDE Interface

This section contains guidelines for connecting and routing the ICH2 IDE interface. The ICH2 has two independent IDE channels. This section provides guidelines for IDE connector cabling and motherboard design, including component and resistor placement and signal termination for both IDE channels. The ICH2 has integrated the series resistors that typically have been required on the IDE data signals (PDD[15:0] and SDD[15:0]) running to the two ATA connectors. Intel does not anticipate requiring additional series termination, but OEMs should verify the motherboard signal integrity via simulation. Additional external 0 Ω resistors can be incorporated into the design to address possible noise issues on the motherboard. The additional resistor layout increases flexibility by providing future stuffing options.

The IDE interface can be routed with 5 mil traces on 7 mil spaces and must be less than 8 inches long (from ICH2 to IDE connector). Additionally, the shortest IDE signal (on a given IDE channel) must be less than 0.5 inch shorter than the longest IDE signal (on that channel).

11.1.1 Cabling

• Length of cable: Each IDE cable must be equal to or less than 18 inches. • Capacitance: Less than 30 pF • Placement: A maximum of 6 inches between drive connectors on the cable. If a single drive is placed on the cable it should be placed at the end of the cable. If a second drive is placed on the same cable it should be placed on the connector next closest to the end of the cable (6 inches away from the end of the cable). • Grounding: Provide a direct, low-impedance chassis path between the motherboard ground and hard disk drives. • ICH2 Placement: The ICH2 must be placed at most 8 inches from the ATA connector(s).

11.2 Cable Detection for Ultra ATA/66 and Ultra ATA/100

The ICH2 IDE controller supports PIO, multiword (8237-style) DMA, and Ultra DMA modes 0 through 5. The ICH2 must determine the type of cable present, to configure itself for the fastest possible transfer mode that the hardware can support.

An 80-conductor IDE cable is required for Ultra ATA/66 and Ultra ATA/100. This cable uses the same 40-pin connector as the old 40-pin IDE cable. The wires in the cable alternate: ground, signal, ground, signal’ etc. All ground wires are tied together on the cable (and they are tied to the ground on the motherboard through the ground pins in the 40-pin connector). This cable conforms

Intel® 815E Chipset Platform Design Guide 123

I/O Subsystem

R

to the Small Form Factor Specification SFF-8049, which is obtainable from the Small Form Factor Committee.

To determine whether the ATA/66 or ATA/100 mode can be enabled, the ICH2 requires that the system software attempt to determine the type of cable used in the system. If the system software detects an 80-conductor cable, it may use any Ultra DMA mode up to the highest transfer mode supported by both the chipset and the IDE device. If a 40-conductor cable is detected, the system software must not enable modes faster than Ultra DMA Mode 2 (Ultra ATA/33).

Intel recommends that cable detection be performed using a combination host-side/device-side detection mechanism. Note that host-side detection cannot be implemented on an NLX form factor system, since this configuration does not define interconnect pins for the PDIAG#/CBLID# from the riser (containing the ATA connectors) to the motherboard. These systems must rely on the device-side detection mechanism only.

11.2.1 Combination Host-Side/Device-Side Cable Detection

Host-side detection (described in the ATA/ATAPI-4 Standard, Section 5.2.11) requires the use of two GPI pins (one for each IDE channel). The proper way to connect the PDIAG#/CBLID# signal of the IDE connector to the host is shown in Figure 66. All IDE devices have a 10 kΩ pull-up resistor to 5 V on this signal. Not all GPI and GPIO pins on the ICH2 are 5V tolerant. If non 5V tolerant inputs are used, a resistor divider is required to prevent 5 V on the ICH2 or FWH pins. The proper value of the divider resistor is 10 kΩ (as shown in Figure 66).

Figure 66. Combination Host-Side / Device-Side IDE Cable Detection

IDE drive IDE drive 5 V 5 V To secondary Ω IDE connector 10 kΩ 10 k 40-conductor GPIO cable ICH2 PDIAG# PDIAG#/ PDIAG# CBLID# GPIO 10 kΩ

IDE drive Resistor required for IDE drive non-5V-tolerant GPI. 5 V 5 V To secondary IDE connector 10 kΩ 10 kΩ 80-conductor GPIO IDE cable PDIAG# PDIAG# ICH2 PDIAG#/ CBLID# GPIO 10 kΩ Open IDE_combo_cable_det Resistor required for non-5V-tolerant GPI.

This mechanism allows BIOS, after diagnostics, to sample PDIAG#/CBLID#. If the signal is High, then there is 40-conductor cable in the system and ATA modes 3, 4 and 5 must not be enabled.

124 Intel® 815E Chipset Platform Design Guide

I/O Subsystem

R

If PDIAG#/CBLID# is detected Low, then there may be an 80-conductor cable in the system or there may be a 40-conductor cable and a legacy slave device (Device 1) that does not release the PDIAG#/CBLID# signal as required by the ATA/ATAPI-4 standard. In this case, BIOS should check the Identify Device information in a connected device that supports Ultra DMA modes higher than 2. If ID Word 93, bit 13, is set to 1, then an 80-conductor cable is present. If this bit is set to 0, then a legacy slave (Device 1) is preventing proper cable detection, so BIOS should configure the system as though a 40-conductor cable were present and then notify the user of the problem.

11.2.2 Device-Side Cable Detection

For platforms that must implement device-side detection only (e.g., NLX platforms), a 0.047 µF capacitor is required on the motherboard as shown in Figure 67. This capacitor should not be populated when implementing the recommended combination host-side/device-side cable detection mechanism described previously.

Figure 67. Device-Side IDE Cable Detection

IDE drive IDE drive 5 V 5 V Ω 10 kΩ 10 k 40-conductor cable ICH2 PDIAG# PDIAG#/ PDIAG# CBLID#

0.047 µF IDE drive IDE drive 5 V 5 V

10 kΩ 10 kΩ 80-conductor IDE cable PDIAG# PDIAG# ICH2 PDIAG#/ CBLID#

0.047 µF Open IDE_dev_cable_det

This mechanism creates a resistor-capacitor (RC) time constant. The ATA mode 3, 4 or 5 drive will drive PDIAG#/CBLID# Low and then release it (pulled up through a 10 kΩ resistor). The drive will sample the signal after releasing it. In an 80-conductor cable, PDIAG#/CBLID# is not connected through to the host, so the capacitor has no effect. In a 40-conductor cable, the signal is connected to the host, so the signal will rise more slowly as the capacitor charges. The drive can detect the difference in rise times and will report the cable type to the BIOS when it sends the IDENTIFY_DEVICE packet during system boot, as described in the ATA/66 specification.

Intel® 815E Chipset Platform Design Guide 125

I/O Subsystem

R

11.2.3 Primary IDE Connector Requirements

Figure 68. Connection Requirements for Primary IDE Connector

PCIRST_BUF# 22–47 Ω PCIRST# * Reset#

PDD[15:0]

PDA[2:0] PDCS1# PDCS3# PDIOR# PDIOW# PDDREQ 3.3 V 3.3 V

4.7 kΩ Ω 8.2–10 k Primary IDE Connector

PIORDY

IRQ14

PDDACK#

GPIOx PDIAG# / CBLID#

10 kΩ (needed only for CSEL non-5V-tolerant GPI) N.C. Pins 32 & 34 ICH2

* Due to ringing, PCIRST# must be buffered. IDE_primary_conn_require

NOTES: 1. 22 Ω to 47 Ω series resistors are required on RESET#. The correct value should be determined for each unique motherboard design, based on signal quality. 2. An 8.2 kΩ to 10 kΩ pull-up resistor is required on IRQ14 and IRQ15 to VCC3. 3. A 4.7 kΩ pull-up resistor to VCC3 is required on PIORDY and SIORDY. 4. Series resistors can be placed on the control and data lines to improve signal quality. The resistors are placed as close as possible to the connector. Values are determined for each unique motherboard design. 5. The 10 kΩ resistor to ground on the PDIAG#/CBLID# signal is now required on the Primary Connector. This change is to prevent the GPI pin from floating if a device is not present on the IDE interface.

126 Intel® 815E Chipset Platform Design Guide

I/O Subsystem

R

11.2.4 Secondary IDE Connector Requirements

Figure 69. Connection Requirements for Secondary IDE Connector

PCIRST_BUF# 22–47 Ω PCIRST# * Reset#

SDD[15:0]

SDA[2:0] SDCS1# SDCS3# SDIOR# SDIOW# SDDREQ 3.3 V 3.3 V

4.7 kΩ Ω 8.2–10 k Secondary IDE Connector

SIORDY

IRQ15

SDDACK#

GPIOy PDIAG# / CBLID#

10 kΩ (needed only for CSEL non-5V-tolerant GPI) N.C. Pins 32 & 34 ICH2

* Due to ringing, PCIRST# must be buffered. IDE_secondary_conn_require

NOTES: 1. 22 Ω to 47 Ω series resistors are required on RESET#. The correct value should be determined for each unique motherboard design, based on signal quality. 2. An 8.2 kΩ to 10 kΩ pull-up resistor is required on IRQ14 and IRQ15 to VCC3. 3. A 4.7 kΩ pull-up resistor to VCC3 is required on PIORDY and SIORDY 4. Series resistors can be placed on the control and data lines to improve signal quality. The resistors are placed as close as possible to the connector. Values are determined for each unique motherboard design. 5. The 10 kΩ resistor to ground on the PDIAG#/CBLID# signal is now required on the Primary Connector. This change is to prevent the GPI pin from floating if a device is not present on the IDE interface.

Intel® 815E Chipset Platform Design Guide 127

I/O Subsystem

R

11.3 AC ’97

The ICH2 implements an AC ’97 2.1-compliant digital controller. Any codec attached to the ICH2 AC-link must be AC ’97 2.1 compliant, as well. Contact your codec IHV for information on 2.1-compliant products. For information on the AC ’97 2.1 Specification, see Section 1.2, “Reference Documents”.

The AC-link is a bidirectional, serial PCM digital stream. It handles multiple input and output data streams, as well as control register accesses, by employing a time-division-multiplexed (TDM) scheme. The AC-link architecture enables data transfer through individual frames transmitted serially. Each frame is divided into 12 outgoing and 12 incoming data streams, or slots. The architecture of the ICH2 AC-link allows a maximum of two codecs to be connected. Figure 70 shows a two-codec topology of the AC-link for the ICH2.

Figure 70. Intel® ICH2 AC ’97– Codec Connection

Digital AC '97 2.1 controller AC / MC / AMC RESET# SDOUT SYNC AC '97 2.1 BIT_CLK controller section Primary codec of ICH2

SDIN 0 SDIN 1

AC / MC

Secondary codec

ICH2_AC97_codec_conn

Intel has developed an advanced common connector for both AC ’97 as well as networking options. This is known as the Communications and Network Riser (CNR). Refer to Section 11.3.1.

The AC ’97 interface can be routed using 5 mil traces with 5-mil space between the traces. Maximum length between ICH2 to CODEC/CNR is 14 inches in a tee topology. This assumes that a CNR riser card implements its audio solution with a maximum trace length of 4 inches for the

AC’LINK. Trace impedance should be Z0 = 60 Ω ± 15%.

Clocking is provided from the primary codec on the link via BITCLK, and it is derived from a 24.576 MHz crystal or oscillator. Refer to the primary codec vendor for crystal or oscillator requirements. BITCLK is a 12.288 MHz clock driven by the primary codec to the digital

128 Intel® 815E Chipset Platform Design Guide

I/O Subsystem

R

controller (ICH2) and any other codec present. That clock is used as the timebase for latching and driving data.

The ICH2 supports wake-on-ring from S1-S5 via the AC-link. The codec asserts SDATAIN to wake the system. To provide wake capability and/or caller ID, standby power must be provided to the modem codec.

The ICH2 has weak pull-downs/pull-ups that are enabled only when the AC-Link Shut-off bit in the ICH2 is set. This keeps the link from floating when the AC-link is off or when there are no codecs present.

If the Shut-off bit is not set, it means that there is a codec on the link. Therefore, BITCLK and AC_SDOUT will be driven by the codec and ICH2, respectively. However, AC_SDIN0 and AC_SDIN1 may not be driven. If the link is enabled, it may be assumed that there is at least one codec. If there is one or no codec onboard, then the unused AC_SDIN pin(s) should have a weak (10 kΩ) pull-down to keep it from floating.

11.3.1 Communications Network Riser (CNR)

For related documents on the Communication Network Riser, refer to the Communication Network Riser Specification, Revision 1.1 (See Section 1.2, “Reference Documents”). The Communication and Networking Riser (CNR) Specification defines a hardware-scalable Original Equipment Manufacturer (OEM) motherboard riser and interface. This interface supports multi- channel audio, a V.90 analog modem, phone-line based networking, and 10/100 Ethernet based networking. The CNR specification defines the interface that should be configured before system shipment. Standard I/O expansion slots, such as those supported by the PCI bus architecture, are intended to continue serving as the upgrade medium. The CNR mechanically shares a PCI slot. Unlike in the case of the AMR, the system designer will not sacrifice a PCI slot after deciding not to include a CNR in a particular build. It is required that the CNR A0-A2 pins be set to a unique address, so that the CNR EEPROM can be accessed.

The Figure 71 indicates the interface for the CNR connector. The Platform LAN Connection (PLC) can either be an 82562EH or 82562ET component. Refer to the CNR specification for additional information.

Figure 71. CNR Interface

AC '97 I/F LAN I/F Core logic Communication and USB controller networking riser SMBus (up to 2 AC '97 codecs Power and 1 PLC device) Reserved

CNR connector

IO_subsys_CNR_IF

Intel® 815E Chipset Platform Design Guide 129

I/O Subsystem

R

11.3.2 AC ’97 Audio Codec Detect Circuit and Configuration Options

The following provides general circuits to implement a number of different codec configurations. For Intel recommended codec configurations, refer to the Intel® White Paper Recommendations for ICHx/AC ’97 Audio (Motherboard and Communication and Network Riser).

To support more than two channels of audio output, the ICH2 allows for a configuration where two audio codecs work concurrently to provide surround capabilities. To maintain data-on-demand capabilities, the ICH2 AC ’97 controller, when configured for 4 or 6 channels, will wait for all the appropriate slot request bits to be set before sending data in the SDATA_OUT slots. This allows for simple FIFO synchronization of the attached codecs. It is assumed that both codecs will be programmed to the same sample rate, and that the codecs have identical (or at least compatible) FIFO depth requirements. It is recommended that the codecs be provided by the same vendor, upon the certification of their interoperability in an audio channel configuration.

The following circuits (Figure 72, Figure 73, Figure 74, and Figure 75) show the adaptability of a system with the modification of RA and RB combined with some basic glue logic to support multiple codec configurations. This also provides a mechanism to make sure that only two codecs are enabled in a given configuration and allows the configuration of the link to be determined by the BIOS so that the correct PnP IDs can be loaded.

Figure 72. CDC_DN_ENAB# Support Circuitry for a Single Codec on Motherboard

Motherboard CNR Board Codec A

SDATA_IN

RESET#

Codec C

RESET#

From AC '97 AC97_RESET# SDATA_IN Controller

Vcc Codec D

RB RESET# To General CDC_DN_ENAB# 1kohms Purpose Input SDATA_IN RA 10kohms

To AC '97 SDATA_IN0 Digital SDATA_IN1 Controller

CNR Connector

As shown in Figure 72, when a single codec is located on the motherboard, the resistor RA and the circuitry (AND and NOT gates) shown inside the dashed box must be implemented, on the motherboard. This circuitry is required to disable the motherboard codec when a CNR is installed which contains two AC ’97 codecs (or a single AC ’97 codec which must be the primary codec on the AC-Link).

By installing resistor RB (1 kΩ) on the CNR, the codec on the motherboard becomes disabled (held in reset) and the codec(s) on the CNR take control of the AC-Link. One possible example of

130 Intel® 815E Chipset Platform Design Guide

I/O Subsystem

R

using this architecture is a system integrator installing an audio plus modem CNR in a system already containing an audio codec on the motherboard. The audio codec on the motherboard would then be disabled, allowing all of the codecs on the CNR to be used.

The architecture shown in Figure 73 has some unique features. These include the possibility of the CNR being used as an upgrade to the existing audio features of the motherboard (by simply changing the value of resistor RB on the CNR to 100 kΩ). An example of one such upgrade is increasing from two-channel to four or six-channel audio.

Both Figure 73 and Figure 74 show a switch on the CNR board. This is necessary to connect the CNR board codec to the proper SDATA_INn line as to not conflict with the motherboard codec(s).

Figure 73. CDC_DN_ENAB# Support Circuitry for Multi-Channel Audio Upgrade

Motherboard CNR Board Primary Audio Codec SDATA_IN RESET# Audio Codec RESET# SDATA_IN From AC '97 AC97_RESET# ID0# Controller Vcc

RB 100kohms To General CDC_DN_ENAB# Purpose Input RA 10kohms

To AC '97 SDATA_IN0 Digital SDATA_IN1 Controller CNR Connector

NOTE: Figure 74 shows the circuitry required on the motherboard to support a two-codec down configuration. This circuitry disables the codec on a single codec CNR. Notice that in this configuration the resistor, RB, has been changed to 100 kΩ.

Figure 74. CDC_DN_ENAB# Support Circuitry for Two-Codecs on Motherboard / One-Codec on CNR

Motherboard CNR Board Primary Secondary Audio Codec Codec SDATA_IN SDATA_IN RESET# RESET#

Audio Codec RESET# From AC '97 AC97_RESET# SDATA_IN ID0# Controller Vcc

RB 100kohms To General CDC_DN_ENAB# Purpose Input RA 10kohms

To AC '97 SDATA_IN0 Digital SDATA_IN1 Controller CNR Connector

Intel® 815E Chipset Platform Design Guide 131

I/O Subsystem

R

Figure 75 shows the case of two-codecs down and a dual-codec CNR. In this case, both codecs on the motherboard are disabled (while both on CNR are active) by RA being 10 kΩ and RB being 1 kΩ.

Figure 75. CDC_DN_ENAB# Support for Two-Codecs on Motherboard / Two-Codecs on CNR

Motherboard CNR Board Codec A Codec B

SDATA_IN SDATA_IN RESET# RESET#

Codec C

RESET#

From AC '97 AC97_RESET# SDATA_IN Controller Vcc Codec D R B RESET# To General CDC_DN_ENAB# 1kohms Purpose Input SDATA_IN RA 10kohms

To AC '97 SDATA_IN0 Digital SDATA_IN1 Controller CNR Connector

NOTES: 1. While it is possible to disable down codecs, as shown in Figure 72 and Figure 75, it is recommended against for reasons cited in the ICHx/AC '97 White Paper, including avoidance of shipping redundant and/or non-functional audio jacks. 2. All CNR designs include resistor RB. The value of RB is either 1 kΩ or 100 kΩ, depending on the intended functionality of the CNR (whether or not it intends to be the primary/controlling codec). 3. Any CNR with two codecs must implement RB with value 1 kΩ. If there is one codec, use a 100 kΩ pull- up resistor. A CNR with zero codecs must not stuff RB. If implemented, RB must be connected to the same power well as the codec so that it is valid whenever the codec has power. 4. A motherboard with one or more codecs down must implement RA with a value of 10 kΩ. 5. The CDC_DN_ENAB# signal must be run to a GPI so that the BIOS can sense the state of the signal. CDC_DN_ENAB# is required to be connected to a GPI; a connection to a GPIO is strongly recommended for testing purposes.

Table 29. Signal Descriptions

Signal Description

CDC_DN_ENAB# When low, indicates that the codec on the motherboard is enabled and primary on the AC ’97 Interface. When high, indicates that the motherboard codec(s) must be removed from the AC ’97 Interface (held in reset), because the CNR codec(s) will be the primary device(s) on the AC ’97 Interface.

AC97_RESET# Reset signal from the AC ’97 Digital Controller (ICH2).

SDATA_Inn AC ’97 serial data from an AC ’97-compliant codec to an AC ’97-compliant controller (i.e., the ICH2).

132 Intel® 815E Chipset Platform Design Guide

I/O Subsystem

R

11.3.2.1 Valid Codec Configurations

Table 30. Codec Configurations

Valid Codec Configurations Invalid Codec Configurations

AC(Primary) MC(Primary) + X(any other type of codec)

MC(Primary) AMC(Primary) + AMC(Secondary)

AMC(Primary) AMC(Primary) + MC(Secondary)

AC(Primary) + MC(Secondary)

AC(Primary) + AC(Secondary)

AC(Primary) + AMC(Secondary)

11.3.3 SPKR Pin Considerations

The effective impedance of the speaker and codec circuitry on the SPKR signal line must be greater than 50 kΩ. Failure to due so will cause the TCO Timer Reboot function to be erroneously disabled. SPKR is used as both the output signal to the system speaker and as a functional strap. The strap function enables or disables the “TCO Timer Reboot function” based on the state of the SPKR pin on the rising edge of POWEROK. When enabled, the ICH2 sends an SMI# to the processor upon a TCO timer timeout. The status of this strap is readable via the NO_REBOOT bit (bit 1, D31: F0, Offset D4h). The SPKR signal has a weak integrated pull up resistor (the resistor is only enabled during boot/reset). Therefore it’s default state when the pin is a “no connect” is a logical one or enabled. To disable the feature, a jumper can be populated to pull the signal line low (see Figure 76). The value of the pull-down must be such that the voltage divider caused by the pull down and integrated pull up resistors will be read as logic low. When the jumper is not populated, a low can still be read on the signal line if the effective impedance due to the speaker and codec circuit is equal to or lower than the integrated pull up resistor. It is therefore strongly recommended that the effective impedance be greater than 50 kΩ and the pull-down resistor be less than 7.3 kΩ.

Figure 76. Example Speaker Circuit

ICH2 3.3V

Integrated Pull-Up 18-42 KΩ

Stuff Jumper To Effective Impedance Disable Timeout Due To Speaker and Feature. Codec Circuit. Reff > 50 KΩ R < 7.3 KΩ

Spkr_Ckt_815E_B0

Intel® 815E Chipset Platform Design Guide 133

I/O Subsystem

R

11.3.4 AC ’97 Routing

To ensure the maximum performance of the codec, proper component placement and routing techniques are required. These techniques include properly isolating the codec, associated audio circuitry, analog power supplies, and analog ground planes, from the rest of the motherboard. This includes plane splits and proper routing of signals not associated with the audio section. Contact your vendor for device-specific recommendations.

The basic recommendations are as follows: • Special consideration must be given for the ground return paths for the analog signals. • Digital signals routed in the vicinity of the analog audio signals must not cross the power plane split lines. Analog and digital signals should be located as far as possible from each other. • Partition the board with all analog components grouped together in one area and all digital components in another. • Separate analog and digital ground planes should be provided, with the digital components over the digital ground plane, and the analog components, including the analog power regulators, over the analog ground plane. The split between planes must be a minimum of 0.05 inches wide. • Keep digital signal traces, especially the clock, as far as possible from the analog input and voltage reference pins. • Do not completely isolate the analog/audio ground plane from the rest of the board ground plane. There should be a single point (0.25 inches to 0.5 inches wide) where the analog/isolated ground plane connects to the main ground plane. The split between planes must be a minimum of 0.05 inches wide. • Any signals entering or leaving the analog area must cross the ground split in the area where the analog ground is attached to the main motherboard ground. That is, no signal should cross the split/gap between the ground planes, which would cause a ground loop, thereby greatly increasing EMI emissions and degrading the analog and digital signal quality. • Analog power and signal traces should be routed over the analog ground plane. • Digital power and signal traces should be routed over the digital ground plane. • Bypassing and decoupling capacitors should be close to the IC pins, or positioned for the shortest connections to pins, with wide traces to reduce impedance. • All resistors in the signal path or on the voltage reference should be metal film. Carbon resistors can be used for DC voltages and the power supply path, where the voltage coefficient, temperature coefficient, and noise are not factors. • Regions between analog signal traces should be filled with copper, which should be electrically attached to the analog ground plane. Regions between digital signal traces should be filled with copper, which should be electrically attached to the digital ground plane. • Locate the crystal or oscillator close to the codec.

Clocking is provided from the primary codec on the link via BITCLK, and it is derived from a 24.576 MHz crystal or oscillator. Refer to the primary codec vendor for the crystal or oscillator requirements. BITCLK is a 12.288 MHz clock driven by the primary codec to the digital controller (ICH2) and by any other codec present. The clock is used as the time base for latching and driving data.

134 Intel® 815E Chipset Platform Design Guide

I/O Subsystem

R

11.3.5 Motherboard Implementation

The following design considerations are provided for the implementation of an ICH2 platform using AC ’97. These design guidelines have been developed to ensure maximum flexibility for board designers, while reducing the risk of board-related issues. These recommendations are not the only implementation or a complete checklist, but they are based on the ICH2 platform. • Components such as FET switches, buffers or logic states should not be implemented on the AC-link signals, except for AC_RST#. Doing so would potentially interfere with timing margins and signal integrity. • The ICH2 supports wake-on-ring from S1–S4 states via the AC-link. The codec asserts SDATAIN to wake the system. To provide wake capability and/or caller ID, standby power must be provided to the modem codec. If no codec is attached to the link, internal pull-downs will prevent the inputs from floating, so external resistors are not required. The ICH2 does not wake from the S5 state via the AC-link. • PC_BEEP should be routed through the audio codec. Care should be taken to avoid the introduction of a pop when powering the mixer up or down.

11.4 USB

11.4.1 Using Native USB Interface

The general guidelines for the USB interface are as follows: • Unused USB ports should be terminated with 15 kΩ pull-down resistors on both P+/P- data lines. • 15 Ω series resistors should be placed as close as possible to the ICH2 (<1 inch). These series resistors are required for source termination of the reflected signal. • An optional 47 pF cap may be placed as close to the USB connector as possible on the USB data lines (P0+/-, P1+/-, P2+/-, P3+/-). This cap can be used for signal quality (rise/fall time) and to help minimize EMI radiation. • 15 kΩ ± 5% pull-down resistors should be placed on the USB side of the series resistors on the USB data lines (P0± … P3±), and they are REQUIRED for signal termination by the USB specification. The stub should be as short as possible. • The trace impedance for the P0±…P3± signals should be 45 Ω (to ground) for each USB signal P+ or P-. When the stack-up recommended in Section 2.1 is used, the USB requires 9-mil traces. The impedance is 90 Ω between the differential signal pairs P+ and P-, to match the 90 Ω USB twisted-pair cable impedance. Note that the twisted-pair’s characteristic impedance of 90 Ω is the series impedance of both wires, resulting in an individual wire presenting a 45 Ω impedance. The trace impedance can be controlled by carefully selecting the trace width, trace distance from power or ground planes, and physical proximity of nearby traces. • USB data lines must be routed as critical signals. The P+/P- signal pair must be routed together, parallel to each other on the same layer, and not parallel with other non-USB signal traces to minimize crosstalk. Doubling the space from the P+/P- signal pair to adjacent signal traces will help to prevent crosstalk. Do not worry about crosstalk between the two P+/P- signal traces. The P+/P- signal traces must also be the same length. This will minimize the effect of common mode current on EMI. Lastly, do not route over plane splits.

Intel® 815E Chipset Platform Design Guide 135

I/O Subsystem

R

Figure 77 illustrates the recommended USB schematic.

Figure 77. USB Data Signals

Driver Motherboard Trace 15 ohm < 1" P+ 45 ohm

15k Optional 47 pf 90 ohm Driver Motherboard Trace 15 ohm

< 1" USB Connector P- 45 ohm

15k Optional 47 pf

ICH2 Transmission Line USB Twisted Pair Cable

The recommended USB trace characteristics are: • Impedance ‘Z0’ = 45.4 Ω • Line Delay = 160.2 ps • Capacitance = 3.5 pF • Inductance = 7.3 nH • Res @ 20° C = 53.9 mΩ

11.4.2 Disabling the Native USB Interface of Intel® ICH2

The ICH2 native USB interface can be disabled. This can be done when an external PCI based USB controller is being implemented in the platform. To disable the native USB Interface, ensure the differential pairs are pulled down thru 15 kΩ resistors, ensure the OC[3:0]# signals are de- asserted by pulling them up weakly to VCC3SBY, and that both function 2 & 4 are disabled via the D31:F0;FUNC_DIS register. Ensure that the 48 MHz USB clock is connected to the ICH2 and is kept running. This clock must be maintained even though the internal USB functions are disabled.

136 Intel® 815E Chipset Platform Design Guide

I/O Subsystem

R

11.5 IOAPIC Design Recommendation

Systems not using the IOAPIC should comply with the following recommendations: • On the ICH2:  Tie PICCLK directly to ground.  Tie PICD0, PICD1 to ground through a 10 kΩ resistor. • On the processor:  PICCLK requires special implementation for universal motherboard designs. See Section 4.2.9.  Tie PICD0 to 2.5 V through 10 kΩ resistors.  Tie PICD1 to 2.5 V through 10 kΩ resistors.

11.5.1 PIRQ Routing Example

PCI interrupt request signals E-H are new to the ICH2. These signals have been added to lower the latency caused by having multiple devices on one Interrupt line. With these new signals, each PCI slot can have an individual PCI interrupt request line (assuming that the system has four PCI slots). Table 31 shows how the ICH2 uses the PCI IRQ when the I/O APIC is active.

Table 31. I/O APIC Interrupt Inputs 16 thru 23 Usage

No IOAPIC INTIN PIN Function in Intel® ICH2 Using the PCI IRQ in I/O APIC

1 IOAPIC INTIN PIN 16 (PIRQA)

2 IOAPIC INTIN PIN 17 (PIRQB) AC ’97, Modem and SMBUS

3 IOAPIC INTIN PIN 18 (PIRQC)

4 IOAPIC INTIN PIN 19 (PIRQD) USB Controller #1

5 IOAPIC INTIN PIN 20 (PIRQE) Internal LAN Device

6 IOAPIC INTIN PIN 21 (PIRQF)

7 IOAPIC INTIN PIN 22 (PIRQG)

8 IOAPIC INTIN PIN 23 (PIRQH) USB Controller #2 (starting from Intel® ICH2 B0 stepping)

Interrupts B, D, E and H service devices internal to the ICH2. Interrupts A, C, F, and G are unused and can be used by PCI slots. Figure 78 shows an example of IRQ line routing to the PCI slots.

Intel® 815E Chipset Platform Design Guide 137

I/O Subsystem

R

Figure 78. Example PIRQ Routing

INTA INTA INTA INTA

INTB INTB INTB INTB PIRQA# PIRQB# INTC INTC INTC INTC PIRQC# PIRQD# INTD INTD INTD INTD ICH2 PIRQE# PIRQF# PIRQG# PIRQH#

Slot 1 Slot 2 Slot 3 Slot 4 PCI Device 0 PCI Device 5 PCI Device 6 PCI Device C (AD16 to IDSEL) (AD21 to IDSEL) (AD22 to IDSEL) (AD28 to IDSEL)

The PCI IRQ Routing shown in Figure 78 allows the ICH2 internal functions to have a dedicated IRQ (assuming add-in cards are single function devices and use INTA). If a P2P bridge card or a multifunction device uses more than one INTn# pin on the ICH2 PCI Bus, the ICH2 internal functions will start sharing IRQs. It is up to the board designer to route these signals in a way that will prove the most efficient for their particular system. A PCI slot can be routed to share interrupts with any of the ICH2’s internal device/functions.

11.6 SMBus/SMLink Interface

The SMBus interface on the ICH2 is the same as that on the ICH. It uses two signals, SMBCLK and SMBDATA, to send and receive data from components residing on the bus. These signals are used exclusively by the SMBus host controller. The SMBus host controller resides inside the ICH2.

The ICH2 incorporates a new SMLink interface supporting AOL*, AOL2*, and slave functionality. It uses two signals, SMLINK[1:0]. SMLINK[0] corresponds to an SMBus clock signal, and SMLINK[1] corresponds to an SMBus data signal. These signals are part of the SMB slave interface.

For Alert on LAN (AOL) functionality, the ICH2 transmits heartbeat and event messages over the interface. When the 82562EM LAN connect component is used, the ICH2’s integrated LAN controller claims the SMLink heartbeat and event messages and sends them out over the network. An external, AOL2-enabled LAN controller will connect to the SMLink signals, to receive heartbeat and event messages as well to as access the ICH2 SMBus slave interface. The slave interface function allows an external microcontroller to perform various functions. For example, the slave write interface can reset or wake a system, generate SMI# or interrupts, and send a message. The slave read interface can read the system power state, read the watchdog timer status, and read system status bits.

Both the SMBus host controller and the SMBus slave interface obey the SMBus protocol, so the two interfaces can be externally wire-ORed together to allow an external management ASIC to access targets on the SMBus as well as the ICH2 slave interface. This is performed by connecting SMLink[0] to SMBCLK and SMLink[1] to SMBDATA, as shown in Figure 79. Since the SMBus

138 Intel® 815E Chipset Platform Design Guide

I/O Subsystem

R

and SMLINK are pulled up to VCCSUS3_3, system designers must ensure that they implement proper isolation for any devices that may be powered down while VCCSUS3_3 is still active (i.e., thermal sensors).

Figure 79. SMBus/SMLink Interface

Host Controller and SPD Data Slave Interface Network Temperature on Interface Thermal Sensor Card on PCI

SMBus SMBCLK Microcontroller 82801BA SMBDATA

SMLink SMLink0

SMLink1

Wire OR (Optional) 82850 Motherboard LAN Controller smbus-link

Note: Intel does not support external access to the ICH2’s integrated LAN controller via the SMLink interface. Also, Intel does not support access to the ICH2’s SMBus slave interface by the ICH2’s SMBus host controller. Table 32 describes the pull-up requirements for different implementations of the SMBus and SMLink signals.

Table 32. Pull-Up Requirements for SMBus and SMLink

SMBus / SMLink Use Implementation

Alert-on-LAN* signals 4.7 kΩ pull-up resistors to 3.3 VSB are required.

GPIOs Pull-up resistors to 3.3 VSB and the signals must be allowed to change states on power-up. (For example, on power-up the Intel® ICH2 will drive heartbeat messages until the BIOS programs these signals as GPIOs.) The value of the pull-up resistors depends on the loading on the GPIO signal.

Not Used 4.7 kΩ pull-up resistors to 3.3 VSB are required.

11.6.1 SMBus Architecture & Design Considerations

There are several possibilities for designing an SMBus using the ICH2. Designs can be grouped into three major categories based on the power supply source for the SMBus microcontrollers. This includes two unified designs, where all devices are powered by either VCCCORE or VCC_Suspend, and a mixed design where some devices are powered by each of the two supplies.

Primary considerations in choosing a design are based on: • Whether there are there devices that must run in STR? • Amount of VCC_Suspend current available, i.e. minimizing load of VCC_Suspend

Intel® 815E Chipset Platform Design Guide 139

I/O Subsystem

R

11.6.1.1 General Design Issues and Notes

Regardless of the architecture used, there are some general considerations. • The pull-up resistor size for the SMBus data and clock signals is dependent on the number of devices present on the bus. A typical value is 8.2 kΩ. This should prevent the SMBus signals from floating, which could cause leakage in the ICH2 and other devices. • SDRAM DIMMs have their SPD device powered by the same power plane as that used for the DRAM array. Thus, in a system where STR is supported, the SPD device must be powered by VCC_Suspend. In a system not supporting STR, this DIMM can be powered by the core supply. • RIMM memory modules have a separate power source from the RDRAM array for the SPD device. If this SPD device needs to operate in STR, then it should be connected to the VCC_Suspend supply. • The ICH2 does not run SMBus cycles while in STR. • SMBus devices that can operate in STR must be powered by the VCC_Suspend supply.

11.6.1.1.1 The Unified VCC_Suspend Architecture

In this design all SMBus devices are powered by the VCC_Suspend supply. Consideration must be made to provide enough VCC_Suspend current while in STR.

Figure 80. Unified VCC_Suspend Architecture

VCCsus VCCsus

VCCsus SMBus Devices

ICH2 SMBus

vcccore_arch_1

11.6.1.1.2 The Unified VCCCORE Architecture

In this design, all SMBUS devices are powered by the VCCCORE supply. This architecture allows none of the devices to operate in STR, but minimizes the load on VCC_Suspend (VCCsus).

140 Intel® 815E Chipset Platform Design Guide

I/O Subsystem

R

Figure 81. Unified VCCCORE Architecture

VCCCORE VCCCORE

VCCsus SMBus Devices

ICH2 SMBus

vcccore_arch

NOTES: 1. The SMBus device needs to be back-drive safe while its supply (VCCCORE) is off and VCC_Suspend is still powered. 2. In suspended modes where VCCCORE is OFF and VCC_Suspend is on, the VCCCORE node will be very near ground. In this case the input leakage of the ICH will be approximately 10 uA.

11.6.1.1.3 Mixed Architecture

This design allows for SMBus devices to communicate while in STR, yet minimizes VCC_Suspend (VCCsus) leakage by keeping non-essential devices on the core supply. This is accomplished by the use of a “bus switch” to isolate the devices powered by the core and suspend supplies (see Figure 82).

Figure 82. Mixed VCC_Suspend/VCCCORE Architecture

VCCsus VCCsus VCCsus VCCCORE VCCCORE

VCCsus ASICs SMBus CPU Runing VCCsus CLKBF Devices ASIC in STR

Bus ICH2 Switch SMBus SMBus OE# SLP_S3# vcccore_arch_switch

Added Considerations for Mixed Architecture • The bus switch must be powered by VCC_Suspend (VCCsus) • If there are 5V SMBus devices used, then an added level translator must be used to separate those devices driving 5V from those driving 3V signal levels. • Devices that are powered by the VCC_Suspend well must not drive into other devices that are powered off. This is accomplished with the “bus switch”.

Intel® 815E Chipset Platform Design Guide 141

I/O Subsystem

R

11.7 PCI

The ICH2 provides a PCI Bus interface compliant with the PCI Local Bus Specification, Revision 2.2. The implementation is optimized for high-performance data streaming when the ICH2 is acting as either the target or the initiator on the PCI bus. For more information on the PCI Bus interface, refer to the PCI Local Bus Specification, Revision 2.2.

The ICH2 supports six PCI Bus masters (excluding the ICH2), by providing six REQ#/GNT# pairs. In addition, the ICH2 supports two PC/PCI REQ#/GNT# pairs, one of which is multiplexed with a PCI REQ#/GNT# pair.

Figure 83. PCI Bus Layout Example

ICH2

IO_subsys_PCI_layout

11.8 RTC

The ICH2 contains a real-time clock (RTC) with 256 bytes of battery-backed SRAM. The internal RTC module provides two key functions: keeping the date and time and storing system data in its RAM when the system is powered down. This section will present the recommended implementation for the RTC circuit for the ICH2.

11.8.1 RTC Crystal

The ICH2 RTC module requires an external oscillating source of 32.768 kHz connected on the RTCX1 and RTCX2 pins. Figure 84 shows the external circuitry that comprises the oscillator of the ICH2 RTC.

142 Intel® 815E Chipset Platform Design Guide

I/O Subsystem

R

Figure 84. External Circuitry for the Intel® ICH2 RTC

VCC3_3SBY

VCCRTC 2

1.0uF 1kΩ

32768 Hz RTCX2 3 Xtal

R1 10MΩ 1kΩ RTCX1 4 C1 VBAT_RTC R2 0.047uF C3 1 10MΩ

VBIAS 5

C2 1

VSS 6

NOTES: 1. The exact capacitor value must be based on the crystal maker’s recommendation. (The typical values for C2 and C3 are 18 pF with CLOAD = 12.5 pF.) 2. VccRTC: Power for RTC well 3. RTCX2: Crystal input 2 – Connected to the 32.768 kHz crystal. 4. RTCX1: Crystal input 1 – Connected to the 32.768 kHz crystal. 5. VBIAS: RTC BIAS voltage – This pin is used to provide a reference voltage. This DC voltage sets a current that is mirrored throughout the oscillator and buffer circuitry. 6. VSS: Ground

11.8.2 External Capacitors

To maintain RTC accuracy the external capacitor C1 must be 0.047 µF. The external capacitor values for C2 and C3 should be chosen to provide the manufacturer-specified load capacitance (Cload) for the crystal, when combined with the parasitic capacitance of the trace, socket (if used), and package. When the external capacitor values are combined with the capacitance of the trace, socket, and package, the closer the capacitor value can be matched to the actual load capacitance of the crystal used, the more accurate the RTC.

The following equation can be used to choose the external capacitance values (C2 and C3):

Cload = (C2 * C3) / (C2 + C3) + Cparasitic

C3 can be chosen such that C3 > C2. Then C2 can be trimmed to obtain 32.768 kHz.

11.8.3 RTC Layout Considerations

• Keep the RTC lead lengths as short as possible. Approximately 0.25 inch is sufficient. • Minimize the capacitance between Xin and Xout in the routing. • Put a ground plane under the XTAL components. • Do not route switching signals under the external components (unless on the other side of the board). • The oscillator VCC should be clean. Use a filter, such as an RC low-pass or a ferrite inductor.

Intel® 815E Chipset Platform Design Guide 143

I/O Subsystem

R

11.8.4 RTC External Battery Connection

The RTC requires an external battery connection to maintain its functionality and its RAM while the ICH2 is not powered by the system.

Example batteries include the Duracell* 2032, 2025 or 2016 (or equivalent), which give many years of operation. Batteries are rated by storage capacity. The battery life can be calculated by dividing the capacity by the average current required. For example, if the battery storage capacity is 170 mAh (assumed usable) and the average current required is 3 µA, the battery life will be at least:

170,000 µAh / 3 µA = 56,666 h = 6.4 years

The voltage of the battery can affect the RTC accuracy. In general, when the battery voltage decays, the RTC accuracy also decreases. High accuracy can be obtained when the RTC voltage is within the range 3.0 V to 3.3 V.

The battery must be connected to the ICH2 via an isolation Schottky diode circuit. The Schottky diode circuit allows the ICH2 RTC well to be powered by the battery when system power is unavailable, but by system power when it is available. So, the diodes are set to be reverse-biased when system power is unavailable. Figure 85 shows an example of the used diode circuitry.

Figure 85. Diode Circuit to Connect RTC External Battery

VCC3_3SBY

1 kΩ VccRTC

1.0 µF

+ -

RTC_ext_batt_diode_circ

A standby power supply should be used in a desktop system, to provide continuous power to the RTC when available, which will significantly increase the RTC battery life and, thereby, the RTC accuracy.

144 Intel® 815E Chipset Platform Design Guide

I/O Subsystem

R

11.8.5 RTC External RTCRST Circuit

The ICH2 RTC requires some additional external circuitry. The RTCRST# signal is used to reset the RTC well. The external capacitor and the external resistor between RTCRST# and the RTC battery (Vbat) were selected to create an RC time delay, such that RTCRST# will go High some time after the battery voltage is valid. The RC time delay should be within the range of 10–20 ms. When RTCRST# is asserted, bit 2 (RTC_PWR_STS) in the GEN_PMCON_3 (General PM Configuration 3) register is set to 1 and remains set until cleared by software. As a result, when the system boots, the BIOS knows that the RTC battery has been removed.

Figure 86. RTCRST External Circuit for Intel® ICH2 RTC

VCC3_3SBY

Diode / battery circuit 1 kΩ Vcc RTC 1.0 µF

8.2 kΩ RTCRST#

2.2 µF RTCRST circuit

RTC_RTCRESET_ext_circ

This RTCRST# circuit is combined with the diode circuit (see Figure 86), which allows the RTC well to be powered by the battery when system power is unavailable. Figure 86shows an example of this circuitry when used in conjunction with the external diode circuit.

11.8.6 Power-Well Isolation Control

All RTC-well inputs (RSMRST#, RTCRST#, INTRUDER#) must be either pulled up to VCCRTC or pulled down to ground while in G3 state. RTCRST# when configured as shown in Figure 86 meets this requirement. RSMRST# should have a weak external pull-down to ground and INTRUDER# should have a weak external pull-up to VCCRTC. This will prevent these nodes from floating in G3, and correspondingly will prevent ICCRTC leakage that can cause excessive coin-cell drain. The PWROK input signal should also be configured with an external weak pull- down.

Intel® 815E Chipset Platform Design Guide 145

I/O Subsystem

R

The circuit shown in the figure below should be implemented to control well isolation between the 3.3V resume and RTC power-wells. Failure to implement this circuit may result in excessive droop on the VCCRTC node during Sx-to-G3 power state transitions (removal of AC power).

Figure 87. RTC – Power-well Isolation Control

empty

MMBT3906 RSMRST# iP/N 101421-602 from Glue Chip RSMRST# or other source ICH2

10k BAV99 iP/N 305901-001

BAV99 iP/N 305901-001

2.2k

empty

11.8.7 RTC Routing Guidelines

• All RTC OSC signals (RTCX1, RTCX2, VBIAS) should all be routed with trace lengths less than 1 inch. The shorter, the better. • Minimize the capacitance between RTCX1 and RTCX2 in the routing. (Optimally, there would be a ground line between them.) • Put a ground plane under all external RTC circuitry. • Do not route any switching signals under the external components (unless on the other side of the ground plane).

11.8.8 VBIAS DC Voltage and Noise Measurements

• All RTC OSC signals (RTCX1, RTCX2, VBIAS) should all be routed with trace lengths less than 1 inch. The shorter, the better. • Steady-state VBIAS is a DC voltage of about 0.38 V ± .06 V.

146 Intel® 815E Chipset Platform Design Guide

I/O Subsystem

R

• When the battery is inserted, VBIAS will be “kicked” to about 0.7–1.0 V, but it will return to its DC value within a few ms. • Noise on VBIAS must be kept to a minimum (200 mV or less). • VBIAS is very sensitive and cannot be directly probed, but it can be probed through a .01 µF capacitor. • Excessive noise on VBIAS can cause the ICH2 internal oscillator to misbehave or even stop completely. • To minimize VBIAS noise, it is necessary to implement the routing guidelines described previously as well as the required external RTC circuitry, as described in the Intel® 82801BA I/O Controller Hub (ICH2) and Intel® 82801BAM I/O Controller Hub (ICH2-M) Datasheet.

11.9 LAN Layout Guidelines

The ICH2 provides several options for integrated LAN capability. The platform supports several components, depending on the target market. These guidelines use the 82562ET to refer to both the 82562ET and 82562EM. The 82562EM is specified in those cases where there is a difference.

Table 33. LAN Connect

LAN Connect Component Connection Features

Intel® 82562EM Advanced 10/100 Ethernet AOL* & Ethernet 10/100 connection

Intel® 82562ET 10/100 Ethernet Ethernet 10/100 connection

Intel® 82562EH 1 Mb HomePNA* LAN 1 Mb HomePNA connection

Intel developed a dual footprint for 82562ET and 82562EH, to minimize the required number of board builds. A single layout with the specified dual footprint allows the OEM to install the appropriate LAN connect component to satisfy market demand. Design guidelines are provided for each required interface and connection. Refer Figure 88 and table for the corresponding section of the design guide.

Intel® 815E Chipset Platform Design Guide 147

I/O Subsystem

R

Figure 88. Intel® ICH2 / LAN Connect Section

B C

Magnetics ICH2 82562EH/82562ET Connector Module

Dual Footprint Refer to 82562EH/82562ET Section

A D

ich2-lan_conn

11.9.1 Intel® ICH2 – LAN Interconnect Guidelines

This section contains the guidelines for the design of motherboards and riser cards that comply with LAN connect. It should not be considered a specification, and the system designer must ensure through simulations or other techniques that the system meets the specified timings. Special care must be taken to match the LAN_CLK traces with those of the other signals, as follows. The following guidelines are for the ICH2-to-LAN component interface. The following signal lines are used on this interface: • LAN_CLK • LAN_RSTSYNC • LAN_RXD[2:0] • LAN_TXD[2:0]

This interface supports both 82562EH and 82562ET/82562EM components. Both components share signal lines LAN_CLK, LAN_RSTSYNC, LAN_RXD[0], and LAN_TXD[0]. Signal lines LAN_RXD[2:1] and LAN_TXD[2:1] are not connected when 82562EH is installed. The AC characteristics for this interface are found in the Intel® 82801BA I/O Controller Hub (ICH2) and Intel® 82801BAM I/O Controller Hub (ICH2-M) Datasheet (document number: 290687). Dual footprint guidelines are found in Section 11.9.6.

148 Intel® 815E Chipset Platform Design Guide

I/O Subsystem

R

11.9.1.1 Bus Topologies

The LAN connect interface can be configured in several topologies: • Direct point-to-point connection between the ICH2 and the LAN component • Dual footprint • LOM/CNR implementation

11.9.1.2 Point-to-Point Interconnect

The following guidelines are for a single-solution motherboard. Either 82562EH, 82562ET or CNR is installed.

Figure 89. Single-Solution Interconnect

L LAN_CLK LAN_RSTSYNC Platform LAN ICH2 LAN_RXD[2:0] Connect (PLC) LAN_TXD[2:0]

lan_p2p

Table 34. Single-Solution Interconnect Length Requirements (See Figure 89)

Configuration L Comment

Intel® 82562EH 4.5” to 10” Signal lines LAN_RXD[2:1] and LAN_TXD[2:1] are not connected.

Intel® 82562ET 3.5” to 10”

Intel® 82562EM 4.5” to 8.5”

CNR 3” to 9” The trace length from the connector to LOM should be 0.5” to 3.0”

Intel® 815E Chipset Platform Design Guide 149

I/O Subsystem

R

11.9.1.3 LOM/CNR Interconnect

The following guidelines allow for an all-inclusive motherboard solution. This layout combines the LOM, dual-footprint, and CNR solutions. The resistor pack ensures that either a CNR option or a LAN on Motherboard option can be implemented at one time, as shown in Figure 90, which shows the recommended trace routing lengths.

Figure 90. LOM/CNR Interconnect

B

PLC A Res. ICH2 Pack C D

CNR PLC Card

lom-cnr_conn

Table 35. LOM/CNR Length Requirements (See Figure 90)

Configuration A B C D

Intel® 82562EH 0.5” to 6.0” 4.0” to (10.0” – A)

Intel® 82562ET 0.5” to 7.0” 3.0” to (10.0” – A)

Dual footprint 0.5” to 6.5” 3.5” to (10.0” – A)

Intel® 82562ET/EH 0.5” to 6.5” 2.5” to (9” – A) 0.5” to 3.0” card*

NOTE: The total trace length should not exceed 13 inches.

Additional guidelines for this configuration are as follows: • Stubs due to the resistor pack should not be present on the interface. • The resistor pack value can be 0 Ω or 22 Ω. • LAN on Motherboard PLC can be a dual-footprint configuration.

11.9.1.4 Signal Routing and Layout

LAN connect signals must be carefully routed on the motherboard to meet the timing and signal quality requirements of this interface specification. Following are general guidelines that should be followed. It is recommended that the board designer simulate the board routing, to verify that the specifications are met for flight times and skews due to trace mismatch and crosstalk. On the motherboard, the length of each data trace is either equal in length to the LAN_CLK trace or up to 0.5 inch shorter than the LAN_CLK trace. (LAN_CLK should always be the longest motherboard trace in each group.) The trace spacing, unless specified otherwise, is 5:10.

150 Intel® 815E Chipset Platform Design Guide

I/O Subsystem

R

Figure 91. LAN_CLK Routing Example

LAN_CLK

LAN_RXD0

11.9.1.5 Crosstalk Consideration

Noise due to crosstalk must be carefully minimized. Crosstalk is the main cause of timing skews

and is the largest part of the tRMATCH skew parameter.

11.9.1.6 Impedances

Motherboard impedances should be controlled to minimize the impact of any mismatch between the motherboard and the add-in card. An impedance of 60 Ω ± 15% is strongly recommended. Otherwise, signal integrity requirements may be violated.

11.9.1.7 Line Termination

Line termination mechanisms are not specified for the LAN connect interface. Slew-rate- controlled output buffers achieve acceptable signal integrity by controlling signal reflection, over/undershoot, and ringback. A 33 Ω series resistor can be installed at the driver side of the interface, if the developer has concerns about over/undershoot. Note that the receiver must allow for any drive strength and board impedance characteristic within the specified ranges.

Intel® 815E Chipset Platform Design Guide 151

I/O Subsystem

R

11.9.2 General LAN Routing Guidelines and Considerations

11.9.2.1 General Trace Routing Considerations

Trace routing considerations are important to minimize the effects of crosstalk and propagation delays on sections of the board where high-speed signals exist. Signal traces should be kept as short as possible to decrease interference from other signals, including those propagated through power and ground planes.

Observe the following suggestions to help optimize board performance: • The maximum mismatch between the clock trace length and the length of any data trace is 0.5 inch. • Maintain constant symmetry and spacing between the traces within a differential pair. • Keep the signal trace lengths of a differential pair equal to each other. • Keep the total length of each differential pair under 4 inches. (Many customer designs with differential traces longer than 5 inches have had one or more of the following issues: IEEE phy conformance failures, excessive EMI, and/or degraded receive BER.) • Do not route the transmit differential traces closer than 100 mils to the receive differential traces. • Do not route any other signal traces both parallel to the differential traces, and closer than 100 mils to the differential traces (300 mils recommended). • Keep to 7 mils the maximum separation between differential pairs. • For high-speed signals, the number of corners and vias should be kept to a minimum. If a 90° bend is required, it is recommended to use two 45° bends instead. Refer to Figure 92. • Traces should be routed away from board edges by a distance greater than the trace height above the ground plane. This allows the field around the trace to couple more easily to the ground plane rather than to adjacent wires or boards. • Do not route traces and vias under crystals or oscillators. This will prevent coupling to or from the clock. And as a general rule, place traces from clocks and drives at a minimum distance from apertures, by a distance exceeding the largest aperture dimension.

152 Intel® 815E Chipset Platform Design Guide

I/O Subsystem

R

Figure 92. Trace Routing

45 degrees

45 degrees Trace

11.9.2.1.1 Trace Geometry and Length

The key factors in controlling trace EMI radiation are the trace length and the ratio of trace width to trace height above the ground plane. To minimize trace inductance, high-speed signals and signal layers close to a ground or power plane should be as short and wide as practical. Ideally, this ratio of trace width to height above the ground plane is between 1:1 and 3:1. To maintain trace impedance, the width of the trace should be modified when changing from one board layer to another, if the two layers are not equidistant from the power or ground plane. Differential trace impedances should be controlled to ~100 Ω. It is necessary to compensate for trace-to-trace edge coupling, which can lower the differential impedance by 10 Ω, when the traces within a pair are closer than 0.030 inch (edge to edge).

Traces between decoupling and I/O filter capacitors should be as short and wide as practical. Long-and-thin traces are more inductive and would reduce the intended effect of the decoupling capacitors. For similar reasons, traces to I/O signals and signal terminations should be as short as possible. Vias to the decoupling capacitors should have diameters sufficiently large to decrease series inductance. Additionally, the PLC should not be closer than one inch to the connector/magnetics/edge of the board.

11.9.2.1.2 Signal Isolation

Comply with the following rules for signal isolation: • Separate and group signals by function on separate layers if possible. Maintain a gap of 100 mils between all differential pairs (Phoneline and Ethernet) and other nets, but group associated differential pairs together.

Note: Over the length of the trace run, each differential pair should be at least 0.3 inch away from any parallel signal trace.

Intel® 815E Chipset Platform Design Guide 153

I/O Subsystem

R

• Physically group together all components associated with one clock trace, to reduce trace length and radiation. • Isolate I/O signals from high-speed signals to minimize crosstalk, which can increase EMI emission and susceptibility to EMI from other signals. • Avoid routing high-speed LAN or Phoneline traces near other high-frequency signals associated with a video controller, cache controller, processor or other similar device.

11.9.2.2 Power and Ground Connections

Comply with the following rules and guidelines for power and ground connections: • All VCC pins should be connected to the same power supply. • All VSS pins should be connected to the same ground plane. • Four to six decoupling capacitors, including two 4.7 µF capacitors are recommended. • Place decoupling as close as possible to power pins.

11.9.2.2.1 General Power and Ground Plane Considerations

To properly implement the common-mode choke functionality of the magnetics module, the chassis or output ground (secondary side of transformer) should be physically separated from the digital or input ground (primary side) by at least 100 mils.

Figure 93. Ground Plane Separation

0.01" minimum separation

Magnetics Module

SeparateSeparate Chassis Chassis Ground Plane Plane Ground plane

GND_Plane_Separ

Good grounding requires minimizing inductance levels in the interconnections. Keeping ground returns short, signal loop areas small, and power inputs bypassed to signal return significantly reduces EMI radiation.

Comply with the following rules to help reduce circuit inductance in both backplanes and motherboards: • Route traces over a continuous plane with no interruptions (i.e., do not route over a split plane). If there are vacant areas on a ground or power plane, avoid routing signals over the vacant area. This will increase inductance and EMI radiation levels. • To reduce coupling, separate noisy digital grounds from analog grounds. • Noisy digital grounds may affect sensitive DC subsystems.

154 Intel® 815E Chipset Platform Design Guide

I/O Subsystem

R

• All ground vias should be connected to every ground plane, and every power via should be connected to all power planes at equal potential. This helps reduce circuit inductance. • Physically locate grounds between a signal path and its return. This minimizes the loop area. • Avoid fast rise/fall times as much as possible. Signals with fast rise and fall times contain many high-frequency harmonics, which can radiate EMI. • The ground plane beneath the filter/transformer module should be split. The RJ45 and/or RJ11 connector side of the transformer module should have chassis ground beneath it. Splitting the ground planes beneath the transformer minimizes noise coupling between the primary and secondary sides of the transformer and between adjacent coils in the transformer. There should not be a power plane under the magnetics module. • Create a spark gap between pins 2 through 5 of the Phoneline connector(s) and shield ground of 1.6mm (59.0 mil). This is a critical requirement needed to past FCC part 68 testing for Phoneline connection. Note that for worldwide certification a trench of 2.5 mm is required. In North America, the spacing requirement is 1.6mm. However, home networking can be used in other parts of the world, including Europe, where some Nordic countries require the 2.5 mm spacing.

11.9.2.3 A 4-Layer Board Design

Top-Layer Routing

Sensitive analog signals are routed completely on the top layer without the use of vias. This allows tight control of signal integrity and removes any impedance inconsistencies due to layer changes.

Ground Plane

A layout split (100 mils) of the ground plane under the magnetics module between the primary and secondary side of the module is recommended. It is also recommended to minimize the digital noise injected into the 82562 common ground plane. Suggestions include optimizing decoupling on neighboring noisy digital components, isolating the 82562 digital ground using a ground cutout, etc.

Power Plane

Physically separate digital and analog power planes must be provided to prevent digital switching noise from being coupled into the analog power supply planes VDD_A. Analog power may be a metal fill “island,” separated from digital power, and better filtered than digital power.

Bottom-Layer Routing

Digital high-speed signals, which include all LAN interconnect interface signals, are routed on the bottom layer.

Intel® 815E Chipset Platform Design Guide 155

I/O Subsystem

R

11.9.2.4 Common Physical Layout Issues

Common physical layer design and layout mistakes in LAN On Motherboard designs are as follows: 1. Unequal length of the two traces within a differential pair. Inequalities create common-mode noise and distort the transmit or receive waveforms. 2. Lack of symmetry between the two traces within a differential pair. (For each component and/or via that one trace encounters, the other trace must encounter the same component or a via at the same distance from the PLC.) Asymmetry can create common-mode noise, and distort the waveforms. 3. Excessive distance between the PLC and the magnetics or between the magnetics and the RJ-45/11 connector. Beyond a total distance of about 4 inches, it can become extremely difficult to design a spec-compliant LAN product. Long traces on FR4 (fiberglass epoxy substrate) will attenuate the analog signals. Also any impedance mismatch in the traces will be aggravated if they are longer (see #9 below). The magnetics should be as close to the connector as possible (<= 1 inch). 4. Routing any other trace parallel to and close to one of the differential traces. Crosstalk on the receive channel will induce degraded long-cable BER. When crosstalk gets onto the transmit channel, it can cause excessive emissions (below the FCC standard) and can cause poor transmit BER on long cables. Other signals should be kept at least 0.3 inch from the differential traces. 5. Routing the transmit differential traces next to the receive differential traces. The transmit trace closest to one of the receive traces will put more crosstalk onto the closest receive trace, which can greatly degrade the receiver's BER over long cables. After exiting the PLC, the transmit traces should be kept 0.3 inch or more away from the nearest receive trace. In the vicinities where the traces enter or exit the magnetics, the RJ-45/11 and the PLC are the only possible exceptions. 6. Use of an inferior magnetics module. The magnetics modules used by Intel have been fully tested for IEEE PLC conformance, long-cable BER problems, and emissions and immunity. (Inferior magnetics modules often have less common-mode rejection and/or no auto- transformer in the transmit channel.) 7. Another common mistake is using an 82555 or 82558 physical layer schematic in a PLC design. The transmit terminations and decoupling are different, and there also are differences in the receive circuit. Use the appropriate reference schematic or application notes. 8. Not using (or incorrectly using) the termination circuits for the unused pins at the RJ-45/11 and for the wire-side center-taps of the magnetics modules. These unused RJ pins and wire- side center-taps must be correctly referenced to chassis ground via the proper value resistor and capacitor or termination plane. If these are not terminated properly, there can be emission (FCC) problems, IEEE conformance issues, and long-cable noise (BER) problems. The application notes contain schematics that illustrate the proper termination for these unused RJ pins and the magnetics center-taps. 9. Incorrect differential trace impedances. It is important to have ~100 Ω impedance between the two traces within a differential pair. This becomes even more important as the differential traces become longer. It is very common to see customer designs that have differential trace impedances between 75 Ω and 85 Ω, even when the designers think they have designed for 100 Ω. (To calculate the differential impedance, many impedance calculators only multiply the single-ended impedance by two. This does not take into account edge-to-edge capacitive coupling between the two traces. When the two traces within a differential pair are kept close (see Note) to each other, the edge coupling can lower the effective differential impedance by

156 Intel® 815E Chipset Platform Design Guide

I/O Subsystem

R

5 Ω to 20 Ω. A 10 Ω to 15 Ω drop in impedance is common.) Short traces will have fewer problems if the differential impedance is a little off. 10. Another common problem is to use a too-large capacitor between the transmit traces and/or too much capacitance from the magnetic’s transmit center-tap (on the 82562ET side of the magnetics) to ground. Using capacitors with capacitances exceeding a few pF in either of these locations can slow the 100 Mbps rise and fall times so much that they fail the IEEE rise time and fall time specs, which will cause the return loss to fail at higher frequencies and will degrade the transmit BER performance. Caution should be exercised if a cap is put in either of these locations. If a cap is used, it should almost certainly be less than 22 pF. (Reasonably good success has been achieved by using 6 pF to 12 pF values in past designs.) Unless there is some overshoot in the 100 Mbps mode, these caps are not necessary.

Note: It is important to keep the two traces within a differential pair close to each other. Keeping them close helps to make them more immune to crosstalk and other sources of common-mode noise. This also means lower emissions (i.e., FCC compliance) from the transmit traces, and better receive BER for the receive traces. Close should be considered to be less than 0.030 inch between the two traces within a differential pair. 0.007 inch trace-to-trace spacing is recommended.

11.9.3 Intel® 82562EH Home/PNA* Guidelines

For correct LAN performance, designers must follow the general guidelines outlined in Section 11.9.2. Additional guidelines for implementing an 82562EH Home/PNA* LAN connect component are as follows are provided in the following subsections.

11.9.3.1 Power and Ground Connections

Obey the following rule for power and ground connections: • For best performance, place decoupling capacitors on the backside of the PCB, directly under the 82562EH, with equal distance from both pins of the capacitor to power/ground.

The analog power supply pins for 82562EH (VCCA, VSSA) should be isolated from the digital VCC and VSS through the use of ferrite beads. In addition, adequate filtering and decoupling capacitors should be provided between VCC and VSS as well as the VCCA and VSSA power supplies.

11.9.3.2 Guidelines for Intel® 82562EH Component Placement

Component placement can affect the signal quality, emissions, and temperature of a board design. This section discusses guidelines for component placement.

Careful component placement can: • Decrease potential problems directly related to electromagnetic interference (EMI), which could result in failure to meet FCC specifications. • Simplify the task of routing traces. To some extent, component orientation will affect the complexity of trace routing. The overall objective is to minimize turns and crossovers between traces.

Note: It is important to minimize the space needed for the HomePNA LAN interface, because all other interfaces will compete for physical space on a motherboard near the connector edge. As with

Intel® 815E Chipset Platform Design Guide 157

I/O Subsystem

R

most subsystems, the HomePNA LAN circuits must be as close as possible to the connector. Thus, it is imperative that all designs be optimized to fit in a very small space.

11.9.3.3 Crystals and Oscillators

To minimize the effects of EMI, clock sources should not be placed near I/O ports or board edges. Radiation from these devices may be coupled onto the I/O ports or out of the system chassis. Crystals should also be kept away from the HomePNA magnetics module to prevent communication interference. If they exist, the crystal’s retaining straps should be grounded to prevent the possibility of radiation from the crystal case, and the crystal should lie flat against the PC board to provide better coupling of the electromagnetic fields to the board.

For noise-free and stable operation, place the crystal and associated discrete components as close as possible to the 82562EH. Minimize the length and do not route any noisy signals in this area.

11.9.3.4 Phoneline HPNA Termination

The transmit/receive differential signal pair is terminated with a pair of 51.1 Ω (1%) resistors. This parallel termination should be placed close to the 82562EH. The center, common point between the 51.1 Ω resistors is connected to a voltage-divider network. The opposite end of one 806 Ω resistor is tied to VCCA (3.3V), and the opposite end of the other 806 ohm resistor and the cap are connected to ground. The termination is shown in Figure 94.

Figure 94. Intel® 82562EH Termination

A+3.3 V

806 Ω

0.022 µF 806 Ω 7 51.1 Ω 1 T Tab 1 10 Tip 2 rx_tx_p 3 2 9 Ring 4 51.1 Ω 3 5 6

rx_tx_n Tab 0 B6008 Line 8

7

6.8 µH 6.8 µH 1 Tab 2 1500 pF 1500 pF 3 4 5 6.8 µH 6.8 µH 6 Tab

Phone / modem 8

Shield ground

LAN_82562EH_term

The filter and magnetics component T1 integrates the required filter network, high-voltage impulse protection, and transformer to support the HomePNA LAN interface.

158 Intel® 815E Chipset Platform Design Guide

I/O Subsystem

R

One RJ-11 jack (labeled “LINE” in Figure 94) allows the node to be connected to the Phoneline, and the second jack (labeled “PHONE” in the previous figure) allows other down-line devices to be connected at the same time. This second connector is not required by the HomePNA. However, typical PCI adapters and PC motherboard implementations are likely to include it for user convenience.

A low-pass filter, setup in-line with the second RJ-11 jack, also is recommended by the HomePNA to minimize interference between the HomeRun connection and a POTs voice or modem connection on the second jack. This restricts of the type of devices connected to the second jack as the pass-band of this filter is set approximately at 1.1 MHz. Refer to the HomePNA website (www.homepna.org) for up-to-date information and recommendations regarding the use of this low-pass filter to meet HomePNA certifications.

11.9.3.5 Critical Dimensions

There are three dimensions to consider during layout. Distance ‘B’ from the line RJ11 connector to the magnetics module, distance ‘C’ from the phone RJ11 to the LPF (if implemented), and distance ‘A’ from 82562EH to the magnetics module (see Figure 95).

Figure 95. Critical Dimensions for Component Placement

B A C

Magnetics Line ICH2 82562ET Module RJ11

Phone LPF RJ11 EEPROM

Critical_place

Table 36. Critical Dimensions for Component Placement (Refer to Figure 95)

Distance Priority Guideline

B 1 < 1 inch

A 2 < 1 inch

C 3 < 1 inch

Intel® 815E Chipset Platform Design Guide 159

I/O Subsystem

R

11.9.3.5.1 Distance from Magnetics Module to Line RJ11 (Distance B)

This distance ‘B’ should be given highest priority and should be less then 1 inch. Regarding trace symmetry, route differential pairs with consistent separation and with exactly the same lengths and physical dimensions.

Asymmetrical and unequally long differential pairs contribute to common-mode noise. This can degrade the receive circuit performance and contribute to emissions radiated from the transmit side.

11.9.3.5.2 Distance from Intel® 82562EH to Magnetics Module (Distance A)

Due to the high speed of signals present, distance ‘A’ between the 82562EH and the magnetics should also be less than 1 inch, but should be second priority relative to distance from connects to the magnetics module.

Generally speaking, any section of trace intended for use with high-speed signals should be subject to proper termination practices. Proper signal termination can reduce reflections caused by impedance mismatches between the device and traces route. The reflections of a signal may have a high-frequency component that may contribute more EMI than the original signal itself.

11.9.3.5.3 Distance from LPF to Phone RJ11 (Distance C)

This distance ‘C’ should be less then 1 inch. Regarding trace symmetry, route differential pairs with consistent separation and with exactly the same lengths and physical dimensions.

Asymmetrical and unequally long differential pairs contribute to common-mode noise. This can degrade the receive circuit performance and contribute to emissions radiated from the transmit side.

11.9.4 Intel® 82562ET / Intel® 82562EM Guidelines

For correct LAN performance, designers must follow the general guidelines outlined in Section 11.9.2. Additional guidelines for implementing an 82562ET or 82562EM LAN connect component are provided in the following subsections. For related documents, see Section 1.2, “Reference Documents”.

11.9.4.1 Guidelines for Intel® 82562ET / Intel® 82562EM Component Placement

Component placement can affect the signal quality, emissions, and temperature of a board design. This section provides guidelines for component placement.

Careful component placement can: • Decrease potential problems directly related to electromagnetic interference (EMI), which could result in failure to meet FCC and IEEE test specifications. • Simplify the task of routing traces. To some extent, component orientation will affect the complexity of trace routing. The overall objective is to minimize turns and crossovers between traces.

160 Intel® 815E Chipset Platform Design Guide

I/O Subsystem

R

It is important to minimize the space needed for the Ethernet LAN interface, because all other interfaces will compete for physical space on a motherboard near the connector edge. As with most subsystems, the Ethernet LAN circuits must be as close as possible to the connector. Thus, it is imperative that all designs be optimized to fit in a very small space. In addition, the 82562ET or 82562EM should be placed more than 1.5 inches away from any board edge to minimize the potential for EMI radiation problems.

11.9.4.2 Crystals and Oscillators

To minimize the effects of EMI, clock sources should not be placed near I/O ports or board edges. Radiation from these devices may be coupled onto the I/O ports or out of the system chassis. Crystals should also be kept away from the Ethernet magnetics module to prevent interference with communication. If they exist, the retaining straps of the crystal should be grounded to prevent possible radiation from the crystal case. Also, the crystal should lie flat against the PC board to provide better coupling of the electromagnetic fields to the board.

For noise-free and stable operation, place the crystal and associated discrete components as close as possible to the 82562ET or 82562EM. Keep the trace length as short as possible and do not route any noisy signals in this area.

11.9.4.3 Intel® 82562ET / Intel® 82562EM Termination Resistors

The 100 Ω 1% resistor used to terminate the differential transmit pairs (TDP/TDN) and the 120 Ω 1% receive differential pairs (RDP/RDN) should be placed as close as possible to the LAN connect component (82562ET or 82562EM). This is due to the fact that these resistors terminate the entire impedance seen at the termination source (i.e., 82562ET), including the wire impedance reflected through the transformer.

Figure 96. Intel® 82562ET/Intel® 82562EM Termination

LAN Connet Interface Magnetics 82562ET RJ45 Module

Place termination resistors as close to 82562ET as possible.

xxET-xxEM_Term

Intel® 815E Chipset Platform Design Guide 161

I/O Subsystem

R

11.9.4.4 Critical Dimensions

There are two dimensions to consider during layout. Distance ‘B’ from the line RJ45 connector to the magnetics module and distance ‘A’ from the 82562ET or 82562EM to the magnetics module. The combined total distances A and B must not exceed 4 inches (preferably, less than 2 inches) (see Figure 97).

Figure 97. Critical Dimensions for Component Placement

B A

Magnetics Line ICH2 82562ET Module RJ45

EEPROM

LAN_crit_dim_comp_place2

Table 37. Critical Dimensions for Component Placement (see Figure 97)

Distance Priority Guideline

A 1 < 1 inch

B 2 < 1 inch

11.9.4.4.1 Distance from Magnetics Module to RJ45

The distance A in Figure 97 should be given the highest priority in board layout. The separation between the magnetics module and the RJ45 connector should be kept less than 1 inch. The following trace characteristics are important and should be observed: • Differential impedance: The differential impedance should be 100 Ω. The single-ended trace impedance will be approximately 50 Ω. However, the differential impedance can also be affected by the spacing between the traces. • Trace Symmetry: Differential pairs (e.g., TDP and TDN) should be routed with consistent separation and with exactly the same lengths and physical dimensions (e.g., width).

Caution: Asymmetric and unequal length traces in the differential pairs contribute to common-mode noise. This can degrade the receive circuit’s performance and contribute to emissions radiated from the transmit circuit. If the 82562ET must be placed farther than a couple of inches from the RJ45 connector, distance B can be sacrificed. It should be a priority to keep the total distance between the 82562ET and RJ-45 as short as possible.

162 Intel® 815E Chipset Platform Design Guide

I/O Subsystem

R

Note: The measured trace impedance for layout designs targeting 100 Ω often result in lower actual impedance. OEMs should verify actual trace impedance and adjust their layouts accordingly. If the actual impedance is consistently low, a target of 105–110 Ω should compensate for second-order effects.

11.9.4.4.2 Distance from Intel® 82562ET to Magnetics Module

Distance B should also be designed to be less than 1 inch between devices. The high-speed nature of the signals propagating through these traces requires that the distance between these components be closely observed. In general, any section of traces intended for use with high-speed signals should be subject to proper termination practices. Proper termination of signals can reduce reflections caused by impedance mismatches between device and traces. The reflections of a signal may have a high-frequency component that contributes more EMI than the original signal itself. For this reason, these traces should be designed to a 100 Ω differential value. These traces should also be symmetric and of equal length within each differential pair.

11.9.4.5 Reducing Circuit Inductance

The following guidelines show how to reduce circuit inductance in both backplanes and motherboards. Traces should be routed over a continuous ground plane with no interruptions. If there are vacant areas on a ground or power plane, the signal conductors should not cross the vacant area. This increases inductance and associated radiated noise levels. Noisy logic grounds should be separated from analog signal grounds to reduce coupling. Noisy logic grounds can sometimes affect sensitive DC subsystems, such as analog-to-digital conversion, operational amplifiers, etc. All ground vias should be connected to every ground plane. Similarly, every power via should be connected to all power planes at equal potential. This helps reduce circuit inductance. Another recommendation is to physically locate grounds so as to minimize the loop area between a signal path and its return path. Rise and fall times should be as slow as possible. Because signals with fast rise and fall times contain many high-frequency harmonics, that can radiate significantly. The most sensitive signal returns closest to the chassis ground should be connected together. This results in a smaller loop area and reduces the likelihood of crosstalk. The effect of different configurations on the amount of crosstalk can be studied using electronics modeling software.

Terminating Unused Connections

In Ethernet designs, it is common practice to terminate to ground both unused connections on the RJ-45 connector and the magnetics module. Depending on the overall shielding and grounding design, this may be done to the chassis ground, signal ground or a termination plane. Care must be taken when using various grounding methods to ensure that emission requirements are met. The method most often implemented is called the “Bob Smith” termination. In this method, a floating termination plane is cut out of a power plane layer. This floating plane acts as a plate of a capacitor with an adjacent ground plane. The signals can be routed through 75 Ω resistors to the plane. Stray energy on unused pins is then carried to the plane.

Intel® 815E Chipset Platform Design Guide 163

I/O Subsystem

R

Termination Plane Capacitance

The recommended minimum termination plane capacitance is 1500 pF. This helps reduce the amount of crosstalk on the differential pairs (TDP/TDN and RDP/RDN) from the unused pairs of the RJ45. Pads may be placed for an additional capacitance to chassis ground, which may be required if the termplane capacitance is not large enough to pass EFT (electrical fast transient) testing. If a discrete capacitor is used, it should be rated for at least 1000 Vac, to satisfy the EFT requirements.

Figure 98. Termination Plane

TDP N/C TDN RDP RJ-45

RDN

Magnetics Module

Termination Plane

Additional capacitance that may need to be added for EFT testing term_plane

11.9.5 Intel® 82562ET/82562EM Disable Guidelines

To disable the 82562ET/ 82562EM, the device must be isolated (disabled) prior to reset (RSM_PWROK) being asserted. Using a GPIO, such as GPO28 to be LAN_Enable (enabled high), LAN will default to enabled on initial power-up and after an AC power loss. The circuit shown in Figure 99 allows this behavior. BIOS can disable the LAN microcontroller by controlling the GPIO.

164 Intel® 815E Chipset Platform Design Guide

I/O Subsystem

R

Figure 99. Intel® 82562ET/82562EM Disable Circuit

V_3P3_STBY

RSM_PWROK MMBT3906 10 KΩ GPIO_LAN_ENABLE

8256ET/EM_Disable

10 KΩ

Lan_Disable2_815E_B0

There are 4 pins that are used to put the 82562ET controller in different operating states: Test_En, Isol_Tck, Isol_Ti, and Isol_Tex. Table 38 describes the operational/disable features for this design.

The four control signals shown in the Table 38 should be configured as follows: Test_En should be pulled-down thru a 100 Ω resistor. The remaining three control signals should each be connected thru 100 Ω series resistors to the common node “82562ET_Disable” of the disable circuit.

Table 38. Intel® 82562ET Operating States

Test_En Isol_Tck Isol_Ti Isol_Tex State

0 0 0 0 Enabled

0 1 1 1 Disabled with Clock (low power)

1 1 1 1 Disabled without Clock (lowest power)

11.9.6 Intel® 82562ET / Intel® 82562EH Dual Footprint Guidelines

These guidelines characterize the proper layout for a dual-footprint solution. This configuration enables the developer to install either the 82562EH or the 82562ET/82562EM components, while using only one motherboard design. The following guidelines are for the 82562ET/ 82562EH dual-footprint option. The guidelines called out in Sections 11.9.1 through 11.9.4 apply to this configuration. The dual footprint for this particular solution uses a SSOP footprint for 82562ET and a TQFP footprint for 82562EH. The combined footprint for this configuration is shown in Figure 100 and Figure 101.

Intel® 815E Chipset Platform Design Guide 165

I/O Subsystem

R

Figure 100. Dual-Footprint LAN Connect Interface

L

8 2 S LAN_CLK 5 S 6 LAN_RSTSYNC 82562EH O 2 ICH2 TQFP P LAN_RXD[2:0] E LAN_TXD[2:0] T

Stub dual_ft_lan_conn

Figure 101. Dual-Footprint Analog Interface

82562EH/82562ET

Tip TDP 82562EH Ring RJ11 TDN Config. Magnetics Module RDP TXP 82562ET RJ45 RDN TXN Config.

dual_ft_AN_conn

The following are additional guidelines for this configuration: • L = 3.5 inches to 10 inches • Stub < 0.5 inch • Either 82562EH or 82562ET/82562EM can be installed, but not both. • Intel 82562ET pins 28,29, and 30 overlap with 82562EH pins 17,18, and 19. • Overlapping pins are tied to ground. • No other signal pads should overlap or touch. • Signal lines LAN_CLK, LAN_RSTSYNC, LAN_RXD[0], LAN_TXD[0], RDP, RDN, RXP/Ring, and RXN/Tip are shared by the 82562EH and 82562ET configurations. • No stubs should be present when 82562ET is installed. • Packages used for the dual footprint are TQFP for 82562EH and SSOP for 82562ET. • A 22 Ω resistor can be placed at the driving side of the signal line to improve signal quality on the LAN connect interface. • Resistor should be placed as close as possible to the component. • Use components that can satisfy both the 82562ET and 82562EH configurations (i.e., magnetics module).

166 Intel® 815E Chipset Platform Design Guide

I/O Subsystem

R

• Install components for either the 82562ET or the 82562EH configuration. Only one configuration can be installed at a time. • Route shared signal lines such that stubs are not present or are kept to a minimum. • Stubs may occur on shared signal lines (i.e., RDP and RDN). These stubs are due to traces routed to an uninstalled component. • Use 0 Ω resistors to connect and disconnect circuitry not shared by both configurations. Place resistor pads along the signal line to reduce stub lengths. • Traces from magnetics to connector must be shared and not stubbed. An RJ-11 connector that fits into the RJ-45 slot is available. Any amount of stubbing will destroy both HomePNA* and Ethernet performance. • Place at least bulk capacitor (4.7 µF or greater) on each side of the component. • Place decoupling capacitors (0.1 µF) as close to the component as possible.

11.10 LPC/FWH

The following subsections provide general guidelines for compatibility and design recommendations for supporting the FWH device. The majority of the changes will be incorporated in the BIOS.

11.10.1 In-Circuit FWH Programming

All cycles destined for the FWH will appear on the PCI. The ICH2 hub interface-to-PCI Bridge puts all processor boot cycles out on the PCI (before sending them out on the FWH interface). If the ICH2 is set for subtractive decode, these boot cycles can be accepted by a positive decode agent on PCI. This enables booting from a PCI card that positively decodes these memory cycles. To boot from a PCI card, it is necessary to keep the ICH2 in the subtractive decode mode. If a PCI boot card is inserted and the ICH2 is programmed for positive decode, two devices will positively decode the same cycle. In systems with the Intel® 82380AB (ISA bridge), it is also necessary to keep the NOGO signal asserted when booting from a PCI ROM. Note that it is not possible to boot from a ROM behind the 82380AB. Once you have booted from the PCI card, you potentially could program the FWH in circuit and program the ICH2 CMOS.

11.10.2 FWH VPP Design Guidelines

The VPP pin on the FWH is used for programming the flash cells. The FWH supports a VPP of 3.3 V or 12 V. If VPP is 12 V, the flash cells will program about 50% faster than at 3.3 V. However, the FWH only supports 12 V VPP for 80 hours. The 12 V VPP would be useful in a programmer environment that is typically an event that occurs very infrequently (much less than 80 hours). The VPP pin must be tied to 3.3 V on the motherboard.

In some instances, it is desirable to program the FWH during assembly with the device soldered down on the board. To decrease programming time it becomes necessary to apply 12 V to the VPP pin. The following circuit will allow testers to put 12 V on the VPP pin while keeping this voltage separated from the 3.3 V plane to which the rest of the power pins are connected. This circuit also allows the board to operate with 3.3 V on this pin during normal operation.

Intel® 815E Chipset Platform Design Guide 167

I/O Subsystem

R

Figure 102. FWH VPP Isolation Circuitry

3.3V 12V

1K

FET VPP

11.10.3 FWH Decoupling

A 0.1 µF capacitor should be placed between the VCC supply pins and the VSS ground pins to decouple high frequency noise, which may affect the programmability of the device. Additionally, a 4.7 µF capacitor should be placed between the VCC supply pins and the VSS ground pin to decouple low frequency noise. The capacitors should be placed no further than 390 mils from the VCC supply pins.

168 Intel® 815E Chipset Platform Design Guide

Clocking

R

12 Clocking

For an 815E universal platform, there are two clock specifications. One is for a 2-DIMM solution, and the other is for a 3-DIMM solution. In both specifications only single-ended clocking is supported. Intel 815E universal socket 370 platforms using a 0.13 micron socket 370 processor cannot implement differential clocking.

12.1 2-DIMM Clocking

Table 39 shows the characteristics of the clock generator for a 2-DIMM solution.

Table 39. Intel® CK815 (2-DIMM) Clocks

Number Clock Frequency

3 processor clocks 66/100/133 MHz

9 SDRAM clocks 100/133 MHz

7 PCI clocks 33 MHz

2 APIC clocks 16.67/33 MHz

2 48 MHz clocks 48 MHz

3 3V, 66 MHz clocks 66 MHz

1 REF clock 14.31818 MHz

The following bullets list the features of the CK815 clock generator in a 2-DIMM solution: • Nine copies of 100/133 MHz SDRAM clocks (3.3 V) [SDRAM0…7, DClk] • Seven copies of PCI clock (33 MHz ) (3.3 V) • Two copies of APIC clock at 33 MHz, synchronous to processor clock (2.5 V) • One copy of 48 MHz USB clock (3.3 V) (non-SSC) (type 3 buffer) • One copy of 48 MHz DOT clock (3.3 V) (non-SSC) (see DOT details) • Three copies of 3V, 66 MHz clock (3.3 V) • One copy of REF clock at 14.31818 MHz (3.3 V) • Ref. 14.31818 MHz xtal oscillator input • Power-down pin • Spread-spectrum support • I2C support for turning off unused clocks

Intel® 815E Chipset Platform Design Guide 169

Clocking

R

Figure 103 shows the 815E chipset platform clock architecture for a 2-DIMM solution.

Figure 103. Platform Clock Architecture for a 2-DIMM Solution

ITP Processor

CPU 2_ITP 52 55 APIC 0 2.5 V 50 CPU 1 49 CPU 0

Clock Synthesizer AGP

32 Host unit PWRDWN# 29 SEL1 28 SEL0

SData 30 31 SClk Data Main 46 SDRAM(0) Memory Address Memory SDRAM(1) 45 Graphics 43 2 DIMMs GMCH unit SDRAM(2) 42 SDRAM(3) Control 40 SDRAM(4) 39 SDRAM(5) 37 SDRAM(6) 36 SDRAM(7)

34 DCLK Hub I/F 3.3 V

7 3V66 0 26 Dot clock DOT

14.318 MHz

8 3V66 1

1 REF

11 PCI 0 / ICH I/O Controller Hub 32.768 kHz 25 USB

54 APIC 1 2.5 V

12 PCI 1 SIO

3.3 V 13 PCI 2 15 PCI 3 PCI total of 6 16 PCI 4 18 devices (µATX) PCI 5 19 5 slots + 1 down PCI 6 20 PCI 7

clk_arch_2DIMM

170 Intel® 815E Chipset Platform Design Guide

Clocking

R

12.2 3-DIMM Clocking

Table 40 shows the characteristics of the clock generator for a 3-DIMM solution.

Table 40. Intel® CK815 (3-DIMM) Clocks

Number Clock Frequency

2 processor clocks 66/100/133 MHz

13 SDRAM clocks 100/133 MHz

2 PCI clocks 33 MHz

1 APIC clocks 33 MHz

2 48 MHz clocks 48 MHz

3 3V, 66 MHz clocks 66 MHz

1 REF clock 14.31818 MHz

The following bullets list the features of the CK815 clock generator in a 3-DIMM solution: • Thirteen copies of SDRAM clocks • Two copies of PCI clock • One copy of APIC clock • One copy of 48 MHz USB clock (3.3 V) (non-SSC) (type 3 buffer) • One copy of 48 MHz DOT clock (3.3 V) (non-SSC) (see DOT details) • Three copies of 3V, 66 MHz clock (3.3 V) • One copy of ref. clock at 14.31818 MHz (3.3 V) • Ref. 14.31818 MHz xtal oscillator input • Spread-spectrum support • I2C support for turning off unused clocks

Intel® 815E Chipset Platform Design Guide 171

Clocking

R

Figure 104 shows the 815E chipset platform clock architecture for a 3-DIMM solution.

Figure 104. Platform Clock Architecture for a 3-DIMM Solution

Processor

APIC 1 2.5 V 53 CPU 1 54 CPU 0

CK 815 3D Host I/F

12 AGP / 3V66 AGP local memory AGIP / local memory

SDRAM(0) 51 SDRAM(1) 50 SDRAM(2) 47 GFX SDRAM(3) 46 GMCH Dot 45 CLK SDRAM(4) 42 SDRAM(5) Main Memory 41 SDRAM(6) 3 DIMMs SDRAM(7) 38 System SDRAM(8) 37 memory SDRAM(9) 36 33 SDRAM(10) 32 SDRAM(11) Hub I/F 66/266 SDRAM(12) 29

10 3V66 0 11 3V66 1 DOT 27

USB 26

4 REF 0 14.3 MHz I/O Controller Hub

PCI 0 / ICH 15 PCI 1 16

SIO

PCI 1 to zero delay PCI slots / down

clk_arch_3DIMM

172 Intel® 815E Chipset Platform Design Guide

Clocking

R

12.3 Clock Routing Guidelines

This section presents the generic clock routing guidelines for both 2-DIMM and 3-DIMM boards. For 3-DIMM boards, additional analysis must be performed by the motherboard designer to ensure that the clocks generated by the external PCI clock buffer meet the PCI specifications for clock skew at the receiver, when compared with the PCI clock at the ICH2.

Figure 105. Clock Routing Topologies

Layout 1 33 Ω CK815 Section 1 Section 2 Connector

Layout 2 22 Ω CK815 Section 1 Section 2 Section 3 10 pF 22 pF

Layout 3 33 Ω CK815 Section 1 Section 2 Processor

Section 0

33 Ω CK815 Section 1 Section 3 GMCH

Layout 4 33 Ω CK815 Section 1 Section 2

Layout 5 10 Ω CK815 Section 1 Section 2 Connector 22 pF

clk_routing_topo

Intel® 815E Chipset Platform Design Guide 173

Clocking

R

Table 41. Simulated Clock Routing Solution Space

Destination Topology from Section 0 Section 1 Section 2 Section 3 Previous Figure Length Length Length Length

SDRAM MCLK Layout 5 N/A < 0.5” A1 N/A

GMCH SCLK3 Layout 2 N/A < 0.5”=L1 A + 3.5” – L1 0.5”

Processor BCLK Layout 3 < 0.1” < 0.5” A + 5.2” A + 8”

GMCH HCLK <0.5”

GMCH HUBCLK Layout 4 N/A <0.5” A + 8” N/A

ICH2 HUBCLK Layout 4 N/A <0.5” A + 8” N/A

ICH2 PCICLK Layout 4 N/A <0.5” A + 8” N/A

AGP CLK Layout 4 N/A <0.5” A + 3" N/A to A + 4"

PCI down2 Layout 4 N/A <0.5” A + 8.5” N/A to A + 14”

PCI slot2 Layout 1 N/A <0.5” A + 5” to A + 11”

NOTES: 1. Length “A” has been simulated up to 6 inches. The length must be matched between SDRAM MCLK lines by ±100 mils. 2. All PCI clocks must be within 6 inches of the ICH2 PCICLK route length. Routing on PCI add-in cards must be included in this length. In the presented solution space, ICH2 PCICLK was considered to be the shortest in the 6 inches trace routing range, and other clocks were adjusted from there. The system designer may choose to alter the relationship of PCI device and slot clocks, as long as all PCI clock lengths are within 6 inches. Note that the ICH2 PCICLK length is fixed to meet the skew requirements of ICH2 PCICLK to ICH2 HUBCLK. 3. 22 pF Load cap should be placed 0.5 inch from GMCH Pin.

General Clock Layout Guidelines • All clocks should be routed 5 mils wide with 15 mil spacing to any other signals. • It is recommended to place capacitor sites within 0.5 inch of the receiver of all clocks. They are useful in system debug and AC tuning. • Series resistor for clock guidelines: 22 Ω for GMCH SCLK and SDRAM clocks. All other clocks use 33 Ω. • Each DIMM clock should be matched within ±10 mils.

174 Intel® 815E Chipset Platform Design Guide

Clocking

R

Clock Decoupling

Several general layout guidelines should be followed when laying out the power planes for the CK815 clock generator, as follows: • Isolate power planes to the each of the clock groups. • Place local decoupling as close as possible to power pins, and connect with short, wide traces and copper. • Connect pins to appropriate power plane with power vias (larger than signal vias). • Bulk decoupling should be connected to a plane with 2 or more power vias. • Minimize clock signal routing over plane splits. • Do not route any signals underneath the clock generator on the component side of the board. • An example signal via is a 14 mil finished hole with a 24 mil to 26 mil path. An example power via is an 18 mil finished hole with a 33 mil to 38 mil path. For large decoupling or power planes with large current transients, a larger power via is recommended.

12.4 Clock Driver Frequency Strapping

A CK815-compliant clock driver device uses two of its pins to determine whether processor clock outputs should run at 133 MHz, 100 MHz or 66 MHz. The pin names are SEL0 and REF0. In addition, a third strapping pin is defined (SEL1), which must be pulled High for normal clock driver operation.

SEL0 and REF0 are driven by either the processor, which depends on the processor populated in the 370-pin socket, or pull-up resistors on the motherboard. While SEL0 is a pure input to a CK815-compliant clock driver, REF0 is also the 14 MHz output that drives the ICH2 and other devices on the platform. In addition to sampling BSEL[1:0] at reset, CK815-compliant clock drivers are configured by the BIOS via a two-wire interface to drive SDRAM clock outputs at either 100 MHz (default) or 133 MHz (if all system requirements are met).

Intel® 815E Chipset Platform Design Guide 175

Clocking

R

12.5 Clock Skew Assumptions

The clock skew assumptions in are used in the system clock simulations.

Table 42. Simulated Clock Skew Assumptions

Skew Relationships Target Tolerance (±) Notes

HCLK @ GMCH to HCLK @ processor 0 ns 150 ps Assumes ganged clock outputs will allow max of 50 ps skew

HCLK @ GMCH to SCLK @ GMCH 0 ns 600 ps 500 ps pin-to-pin skew 100 ps board/package skew

SCLK @ GMCH to SCLK @ SDRAM 0 ns 630 ps 250 ps pin-to-pin skew 380 ps board + DIMM variation

HLCLK @ GMCH to SCLK @ GMCH 0 ns 900 ps • 500 ps pin-to-pin skew • 400 ps board/package skew

HLCLK @ GMCH to HCLK @ GMCH 0 ns 700 ps • 500 ps pin-to-pin skew • 200 ps board/package skew

HLCLK @ GMCH to HLCLK @ ICH 0 ns 375 ps • 175 ps pin-to-pin skew • 200 ps board/package skew

HLCLK @ ICH to PCICLK @ ICH 0 ns 900 ps • 500ps pin-to-pin skew • 400 ps board/package skew

PCICLK @ ICH to PCICLK @ other PCI 0 ns 2.0-ns window • 500 ps pin-to-pin skew devices • 1.5 ns board/add-in skew

HLCLK @ GMCH to AGPCLK @ connector • Total electrical length of AGP connector + add-in card is 750 ps (according to AGP2.0 spec and AGP design guide 1.0). • Motherboard clock routing must account for this additional electrical length. Therefore, AGPCLK routed to the connector must be shorter than HLCLK to the GMCH, to account for this additional 750 ps.

176 Intel® 815E Chipset Platform Design Guide

Clocking

R

12.6 Intel® CK815 Power Gating on Wake Events

For systems providing functionality with the 0.13 micron socket 370 processors, special handling of wake events is required. When a wake event is triggered, the GMCH and the CK815 must not sample BSEL[1:0] until the signal VTTPWRGD is asserted. This is handled by setting up the following sequence of events: 1. Power is not connected to the CK815-compliant clock driver until schematic signal VTTPWRGD12 is asserted. 2. Clocks to the ICH2 stabilize before the power supply asserts PWROK to the ICH2. There is no guarantee this will occur as the implementation for the previous step relies on the 12V supply. Thus it is necessary to gate PWROK to the ICH2 from the power supply while the CK815 is given sufficient time for the clocks to become stable. The amount of time required is a minimum 20 ms. 3. ICH2 takes the GMCH out of reset. 4. GMCH samples BSEL[1:0]. CK815 will have sampled BSEL[1:0] much earlier.

Refer to Section 4.3 for full implementation details.

Intel® 815E Chipset Platform Design Guide 177

Clocking

R

This page is intentionally left blank.

178 Intel® 815E Chipset Platform Design Guide

Power Delivery

R

13 Power Delivery

This chapter contains power delivery guidelines. Table 43 provides definitions fro power delivery terms used in this chapter.

Table 43. Power Delivery Definitions

Term Description

Suspend-To-RAM In the STR state, the system state is stored in main memory and all (STR): unnecessary system logic is turned off. Only main memory and logic required to wake the system remain powered. This state is used in the Customer Reference Board (CRB) to satisfy the S3 ACPI power management state.

Full-power operation: During full-power operation, all components on the motherboard remain powered. Note that full-power operation includes both the full-on operating state and the S1 (processor stop-grant state) state.

Suspend operation: During suspend operation, power is removed from some components on the motherboard. The CRB supports two suspend states: Suspend-to-RAM (S3) and Soft-off (S5).

Power rails: An ATX power supply has 6 power rails: +5V, –5V, +12V, –12V, +3.3V, 5VSB. In addition to these power rails, several other power rails are created with voltage regulators on the CRB.

Core power rail: A power rail that is only on during full-power operation. These power rails are on when the PSON signal is asserted to the ATX power supply. The core power rails that are distributed directly from the ATX power supply are: ±5V, ±12V and +3.3V.

Standby power rail: A power rail that in on during suspend operation (these rails are also on during full-power operation). These rails are on at all times (when the power supply is plugged into AC power). The only standby power rail that is distributed directly from the ATX power supply is: 5VSB (5V Standby). There are other standby rails that are created with voltage regulators on the motherboard.

Derived power rail: A derived power rail is any power rail that is generated from another power rail. For example, 3.3VSB is usually derived (on the motherboard) from 5VSB using a voltage regulator (on the CRB, 3.3VSB is derived from 5V_DUAL).

Dual power rail: A dual power rail is derived from different rails at different times (depending on the power state of the system). Usually, a dual power rail is derived from a standby supply during suspend operation and derived from a core supply during full-power operation. Note that the voltage on a dual power rail may be misleading.

Figure 106 shows the power delivery architecture for an example system based on the 815E platform. This power delivery architecture supports the “Instantly Available PC Design Guidelines” via the suspend-to-RAM (STR) state. During STR, only the necessary devices are powered. These devices include: main memory, the ICH2 resume well, PCI wake devices (via 3.3 Vaux), AC ’97, and optionally USB. (USB can be powered only if sufficient standby power is available.) To ensure that enough power is available during STR, a thorough power budget should be completed. The power requirements should include each device’s power requirements, both in suspend and in full-power. The power requirements should be compared with the power budget

Intel® 815E Chipset Platform Design Guide 179

Power Delivery

R

supplied by the power supply. Due to the requirements of main memory and the PCI 3.3 Vaux (and possibly other devices in the system), it is necessary to create a dual power rail.

The solutions in this design guide are only examples. Many power distribution methods achieve the similar results. When deviating from these examples, it is critical to consider the effect of a change.

Figure 106. Power Delivery Map

Fan Processor

Intel® 815B Chipset Core: VCC_VID: 1.5 V 1 VRM 8.5 28.5 A S0, S1 Platform Power Map Serial ports Core:Core: VCC_VID: VCC_VID: 1.75 2.0V V1 15.6A S0, S1 ATX P/S 22.6 A S0, S1 Serial xceivers-12: 12 V ± 1.2 V with 720 mA 1 22 mA S0, S1 VTT regulator VTT: 1.25 V 2.7 A S0, S1 5 VSB 5 V 3.3 V 12 V -12 V Serial xceivers-N12: -12 V ± 1.2 V ± 5% ± 5% ± 5% ± 5% ± 10% VTT: 1.5 V1 28 mA S0, S1 2.7 A S0, S1 Serial xceivers-5: 5 V ± 0.25 V -12 V VCC 3.3 V: 3.3 V ± 0.165 V 30 mA S0, S1 15 mA S0, S1

3.3 VSB regulator Display cache: 3.3 V ± 0.3 V 960 mA S0, S1 CLK 3 V dual switch Super I/O CK815-2.5: 2.5 V ± 0.125 V 2.5 V regulator 100 mA S0, S1 LPC super I/O: 3.3V ±0.3V 50 mA S0, S1 CK815-3.3: 3.3 V ± 0.165 V 280 mA S0, S1 PS/2 keyboard/mouse 5 V ± 0.5 V

3V_DUAL 1 A S0, S1

GMCH VDDQ VDDQ regulator 5 V dual 2.3 A S0, S1 switch GMCH core: 1.8 V ± 3% Intel® 815B chipset 1.8 V regulator 1.40 A S0, S1

GMCH: 3.3 V ± 0.165 V 1.40 A S0, S1 1.5 V regulator GMCH: 3.3 VSB ± 0.165 V 110 mA S3, S5

1.8 VSB regulator ICH2 hub I/O: 1.8 V ± 0.09 V AC'97 55 mA S0, S1 5V_DUAL AC'97 12V: 12 V ± 0.6 V ICH2 core: 3.3 V ± 0.3 V 500 mA S0, S1 300 mA S0, S1

AC'97 -12 V: -12 V ± 1.2 V ICH2 CMOS: 1.5 V ± 0.15 V 100 mA S0, S1 250 mA S0, S1 AC'97 5 V: 5 V ± 0.25 V 1.00 A S0, S1 ICH2 resume: 3.3 VSB ± 0.3 V AC'97 5 VSB: 5 VSB ± 0.25 V 1.5 mA S0, S1; 300 µA S3, S5 500 mA S0, S1, S3, S5 ICH2 resume: 1.8 VSB +0.1V/-0.2V 3 DIMM slots: 3.3 VSB ± 0.3 V AC'97 3.3 V: 3.3 V ± 0.165 V 5 mA S0; 2mA S1; 1.8mA S3, S4, S5 1.00 A S0,S1 7.2 A S0, S1; 96 mA S3 AC'97 3.3 VSB: 3.3 VSB ± 0.165 V ICH2 RTC: 3.3 VSB ± 0.3 V 5 µA S0, S1, S3, S5 1.0A S0, S1; 375 mA S3, S5 PCI

FWH core: 3.3 V ± 0.3 V 82559 LAN down 3.3 VSB ± 0.3 V 67 mA S0, S1 195 mA S0,S1; 120 mA S3, S5 USB cable power: 5 V ± 0.25 V 2 A S0, S1; 1 mA S3, S5 (3) PCI 3.3 Vaux: 3.3 VSB ± 0.3 V 1.125 A S0, S1; 60 mA S3, S5

pwr_del_map

1 Refer to Processor Datasheet for Voltage Tolerance Notes: Specifications. Shaded regulators / components are ON in S3 and S5. KB / mouse will not support STR. Total max. power dissipation for GMCH = 4 W. Total max. power dissipation for AC'97 = 15 W.

In addition to the power planes provided by the ATX power supply, an instantly available 815 universal platform (using Suspend-to-RAM) requires 6 power planes to be generated on the board. The requirements for each power plane are documented in this section. In addition to on-board voltage regulators, the CRB will have a 5V Dual Switch.

180 Intel® 815E Chipset Platform Design Guide

Power Delivery

R

5V Dual Switch

This switch will power the 5V Dual plane from the 5V core ATX supply during full-power operation. During Suspend-to-RAM, the 5V Dual plane will be powered from the 5V Standby power supply. Note: the voltage on the 5V Dual plane is not 5V! There is a resistive drop through the 5V Dual Switch that must be considered. Therefore, NO COMPONENTS should be connected directly to the 5V Dual plane. On the CRB, the only devices connected to the 5V Dual plane are voltage regulators (to regulate to lower voltages).

Note: This switch is not required in an 815 universal platform that does not support Suspend-to-RAM (STR).

VTT

This power plane is used to power the AGTL/AGTL+ termination resistors. Refer to the latest revisions of: • Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh) datasheets

Note: This regulator is required in ALL designs.

1.85V

The 1.85V plane powers the GMCH core and the ICH2 hub interface I/O buffers. This power plane has a total power requirement of approximately 1.7A. The 1.85V plane should be decoupled with a 0.1 µF and a 0.01 µF chip capacitor at each corner of the GMCH, and with a single 1 µF and 0.1 µF capacitor at the ICH2.

Note: Note: This regulator is required in ALL designs.

VDDQ

The VDDQ plane is used to power the GMCH AGP interface and the graphics component AGP interface. Refer to the AGP Interface Specification Revision 2.0 (http://www.agpforum.org) and ECR#43 and ECR#44 for specific VDDQ delivery requirements.

For the consideration of component long-term reliability, the following power sequence is strongly recommended while the AGP interface of GMCH is running at 3.3V. If the AGP interface is running at 1.5V, the following power sequence recommendation is no longer applicable. The power sequence recommendations are: • During the power-up sequence, the 1.85V must ramp up to 1.0V BEFORE 3.3V ramps up to 2.2V • During the power-down sequence, the 1.85V CAN NOT ramp below 1.0V BEFORE 3.3V ramps below 2.2V • The same power sequence recommendation also applies to the entrance and exit of S3 state, since MCH power is compete off during the S3 state.

Refer to Section 13.3.2 for more information on the power ramp sequence requirement between 3.3V and 1.85V. System designers need to be aware of this requirement while designing the

Intel® 815E Chipset Platform Design Guide 181

Power Delivery

R

voltage regulators and selecting the power supply. For further details on the voltage sequencing requirements, refer to the Intel® 815 Chipset Family: 82815 Graphics and Memory Controller Hub (GMCH) for use with the Universal Socket 370 Datasheet.

Note: This regulator is required in all designs (unless the design does not support 1.5V AGP, and therefore does not support 4X AGP).

3.3VSB

The 3.3VSB plane powers the I/O buffers in the resume well of the ICH2 and the PCI 3.3Vaux suspend power pins. The 3.3Vaux requirement state that during suspend, the system must deliver 375 mA to each wake-enabled card and 20 mA to each non wake-enabled card. During full-power operation, the system must be able to supply 375 mA to EACH card. Therefore, the total current requirement is: • Full-power Operation: 375 mA * number of PCI slots • Suspend Operation: 375+20 mA* (number of PCI slots – 1)

In addition to the PCI 3.3Vaux, the ICH2 suspend well power requirements must be considered as shown in Figure 106.

Note: This regulator is required in all designs.

1.85VSB

The 1.85VSB plane powers the logic to the resume well of the ICH2. This should not be used for VCMOS.

VCMOS

The VCMOS plane is used to power the processor CMOS signals. In non-universal socket 370 platforms, the 1.5V plane used by VTT also provided VCMOS. Given that VTT can be either 1.25V or 1.5V in a universal socket 370 platform, it is necessary to provide VCMOS as its own separate plane.

13.1 Thermal Design Power

The Thermal Design power (TDP) is defined as the estimated maximum possible expected power generated in a component by a realistic application. It is based on extrapolations in both hardware and software technology over the life of the product. It does not represent the expected power generated by a power virus.

The TDP of the GMCH component is 5.1W.

The TDP of the ICH2 is 1.5 W ±15%.

182 Intel® 815E Chipset Platform Design Guide

Power Delivery

R

13.1.1 Pull-Up and Pull-Down Resistor Values

The pull-up and pull-down values are system dependent. The appropriate value for a system can be determined from an AC/DC analysis of the pull-up voltage used, the current drive capability of the output driver, the input leakage currents of all devices on the signal net, the pull-up voltage tolerance, the pull-up/pull-down resistor tolerance, the input high-voltage/low-voltage specifications, the input timing specifications (RC rise time), etc. Analysis should be performed to determine the minimum/maximum values usable on an individual signal. Engineering judgment should be used to determine the optimal value. This determination can include cost concerns, commonality considerations, manufacturing issues, specifications, and other considerations.

A simplistic DC calculation for a pull-up value is:

RMAX = (VCCPU MIN - VIH MIN) / ILEAKAGE MAX

RMIN = (VCCPU MAX - VIL MAX) / IOL MAX

Since ILEAKAGE MAX is normally very small, RMAX may not be meaningful. RMAX also is determined by the maximum allowable rise time. The following calculation allows for t, the maximum allowable rise time, and C, the total load capacitance in the circuit, including the input capacitance of the devices to be driven, the output capacitance of the driver, and the line capacitance. This calculation yields the largest pull-up resistor allowable to meet the rise time t.

RMAX = -t / (C * In(1-(VIH MIN / VCCPU MIN) ) )

Figure 107. Pull-Up Resistor Example

Vccpu min. Vccpu max.

R max R min

ILeakage max. VIH min. IOL max. VIL max.

PWR_Pullup_Res_815E_B0

13.2 ATX Power Supply PWRGOOD Requirements

The PWROK signal must be glitch free for proper power management operation. The ICH2 sets the PWROK_FLR bit (ICH2 GEN_PMCON_2, General PM Configuration 2 Register, PM-dev31: function 0, bit 0, at offset A2h). If this bit is set upon resume from S3 power-down, the system will reboot and control of the system will not be given to the program running when entering the S3 state. System designers should insure that PWROK signal designs are glitch free.

Intel® 815E Chipset Platform Design Guide 183

Power Delivery

R

13.3 Power Management Signals

• A power button is required by the ACPI specification. • PWRBTN# is connected to the front panel on/off power button. The ICH2 integrates 16 ms debouncing logic on this pin. • AC power loss circuitry has been integrated into the ICH2 to detect power failure. • It is recommended that the ATXPWROK signal from the power supply connector be routed through a Schmitt trigger to square-off and maintain its signal integrity. It should not be connected directly to logic on the board. • PWROK logic from the power supply connector can be powered from the core voltage supply. • RSMRST# logic should be powered by a standby supply, while making sure that the input to the ICH2 is at the 3V level. The RSMST# signal requires a minimum time delay of 1 ms from the rising edge of the standby power supply voltage. A Schmitt trigger circuit is recommended to drive the RSMRST# signal. To provide the required rise time, the 1 ms delay should be placed before the Schmitt trigger circuit. The reference design implements a 20 ms delay at the input of the Schmitt trigger to ensure that the Schmitt trigger inverters have sufficiently powered up before switching the input. Also ensure that voltage on RSMRST# does not exceed VCC(RTC). • It is recommended that 3.3V logic be used to drive RSMRST# to alleviate rise time problems when using a resistor divider from VCC5. • The PWROK signal to the chipset is a 3V signal. • The core well power valid to PWROK asserted at the chipset is a minimum of 1 ms. • PWROK to the chipset must be deasserted after RSMRST#. • PWRGOOD signal to processor is driven with an open-collector buffer pulled up to 2.5 V, using a 330 Ω resistor. It also has a 1.8 KΩ pull-down to ground. • RI# can be connected to the serial port if this feature is used. To implement ring indicate as a wake event, the RS232 transceiver driving the RI# signal must be powered when the ICH2 suspend well is powered. This can be achieved with a serial port transceiver powered from the standby well that implements a shutdown feature. • SLP_S3# from the ICH2 must be inverted and then connected to PSON of the power supply connector to control the state of the core well during sleep states. • For an ATX power supply, when PSON is Low, the core wells are turned on. When PSON is high, the core wells from the power supply are turned off.

184 Intel® 815E Chipset Platform Design Guide

Power Delivery

R

13.3.1 Power Button Implementation

The following items should be considered when implementing a power management model for a desktop system. The power states are as follows: • S1 – Stop Grant – (processor context not lost) • S3 - STR (Suspend to RAM) • S4 - STD (Suspend to Disk) • S5 - Soft-off

Note the following: 1. Wake: Pressing the power button wakes the computer from S1–S5. 2. Sleep: Pressing the power button signals software/firmware in the following manner: a. If SCI is enabled, the power button will generate an SCI to the OS. 1. The OS will implement the power button policy to allow orderly shutdowns. 2. Do not override this with additional hardware. b. If SCI is not enabled: 1. Enable the power button to generate an SMI and go directly to soft-off or a supported sleep state. 2. Poll the power button status bit during POST while SMIs are not loaded and go directly to soft-off if it gets set. 3. Always install an SMI handler for the power button that operates until ACPI is enabled. 3. Emergency Override: Pressing the power button for 4 seconds goes directly to S5. a. This is only to be used in EMERGENCIES when system is not responding. b. This will cause the user data to be lost in most cases. 4. Do not promote pressing the power button for 4 seconds as the normal mechanism to power the machine off. This violates ACPI. 5. To be compliant with the latest PC9x specification, machines must appear to the user to be off when in the S1–S4 sleeping states. This includes: a. All lights, except a power state light, must be off. b. The system must be inaudible: silent or stopped fan, drives off.

Note: Contact Microsoft for the latest information concerning PC9x and Microsoft Logo programs.

Intel® 815E Chipset Platform Design Guide 185

Power Delivery

R

13.3.2 1.85 V/3.3 V Power Sequencing

The ICH2 has two pairs of associated 1.85V and 3.3V supplies. These are {VCC1_85, VCC3_3} and {VCCSus1_85, VCCSus3_3}. These pairs are assumed to power up and power down together. The difference between the two associated supplies must never be greater than 2.0V. The 1.85V supply may come up before the 3.3V supply without violating this rule (though this is generally not practical in a desktop environment, since the 1.85V supply is typically derived from the 3.3V supply by means of a linear regulator).

One serious consequence of violation of the 2V Rule is electrical overstress of oxide layers, resulting in component damage.

The majority of the ICH2 I/O buffers are driven by the 3.3V supplies, but are controlled by logic that is powered by the 1.85V supplies. Thus, another consequence of faulty power sequencing arises if the 3.3V supply comes up first. In this case the I/O buffers will be in an undefined state until the 1.85V logic is powered up. Some signals that are defined as "Input-only" actually have output buffers that are normally disabled, and the ICH2 may unexpectedly drive these signals if the 3.3V supply is active while the 1.85V supply is not.

Figure 108 shows an example power-on sequencing circuit that ensures the 2V Rule is obeyed. This circuit uses a NPN (Q2) and PNP (Q1) transistor to ensure the 1.85V supply tracks the 3.3V supply. The NPN transistor controls the current through PNP from the 3.3V supply into the 1.85V power plane by varying the voltage at the base of the PNP transistor. By connecting the emitter of the NPN transistor to the 1.85V plane, current will not flow from the 3.3V supply into 1.85V plane when the 1.85V plane reaches 1.85V.

Figure 108. Example 1.85 V/3.3 V Power Sequencing Circuit

+3.3V +1.85V

220

Q2 Q1 220 NPN PNP

470

When analyzing systems that may be "marginally compliant" to the 2V Rule, pay close attention to the behavior of the ICH2's RSMRST# and PWROK signals, since these signals control internal isolation logic between the various power planes: • RSMRST# controls isolation between the RTC well and the Resume wells. • PWROK controls isolation between the Resume wells and Main wells

186 Intel® 815E Chipset Platform Design Guide

Power Delivery

R

If one of these signals goes high while one of its associated power planes is active and the other is not, a leakage path will exist between the active and inactive power wells. This could result in high, possibly damaging, internal currents.

13.3.3 3.3V/V5REF Sequencing

V5REF is the reference voltage for 5V tolerance on inputs to the ICH2. V5REF must be powered up before Vcc3_3, or after Vcc3_3 within 0.7V. Also, V5REF must power down after Vcc3_3, or before Vcc3_3 within 0 .7V. The rule must be followed in order to ensure the safety of the ICH2. If the rule is violated, internal diodes will attempt to draw power sufficient to damage the diodes from the Vcc3_3 rail. Figure 109 shows a sample implementation of how to satisfy the V5REF/3.3V sequencing rule.

This rule also applies to the stand-by rails. However, in most platforms the VccSus3_3 rail is derived from the VccSus5 and therefore, the VccSus3_3 rail will always come up after the VccSus5 rail. As a result, V5REF_Sus will always be powered up before VccSus3_3. In platforms that do not derive the VccSus3_3 rail from the VccSus5 rail, this rule must be comprehended in the platform design.

As an additional consideration, during suspend the only signals that are 5V tolerant are USB pins (both over-current and data lines). If USB is not implemented in the system then V5REF_SUS can be connected to the VccSus3_3 rail. Otherwise when USB is supported, V5REF_SUS must be connected to 5V_AUX, which remains powered during S5.

Figure 109. 3.3V/V5REF Sequencing Circuitry

Vcc Supply (3.3 V) 5V Supply

1 KΩ

1 µ F

To System VREF To System

3.3V_5V_Seq_Ckt_815E_B0

Intel® 815E Chipset Platform Design Guide 187

Power Delivery

R

13.4 Power Plane Splits

Figure 110. Power Plane Split Example

pwr_plane_splits

188 Intel® 815E Chipset Platform Design Guide

Power Delivery

R

13.5 Glue Chip 3 (Intel® ICH2 Glue Chip)

To reduce the component count and BOM cost of the ICH2 platform, Intel has developed an ASIC component that integrates miscellaneous platform logic into a single chip. The Glue Chip 3 is designed to integrate some or all of the following functions into a single device. By integrating much of the required glue logic into a single device, overall board cost can be reduced.

Features • PWROK signal generation • Control circuitry for Suspend To RAM • Power Supply power up circuitry • RSMRST# generation • Backfeed cutoff circuit for suspend to RAM • 5V reference generation • Flash FLUSH# / INIT# circuit • HD single color LED driver • IDE reset signal generation/PCIRST# buffers • Voltage translation for Audio MIDI signal • Audio-disable circuit • Voltage translation for DDC to monitor • Tri-state buffers for test

More information regarding this component is available from the following vendors.

Vendor Contact Contact Information

Fujitsu Customer Response Center 3545 North 1st Street, M/S 104 Microelectronics San Jose, CA 95134-1804 phone: 1-800-866-8600 fax: 1-408-922-9179 email: [email protected]

Mitel Semiconductor Greg Kizik 1735 Technology Drive Regional Business Manager Suite 240 San Jose, CA 95110 phone: 408-451-4723 fax: 408-451-4710 e-mail: [email protected] http://www.mitelsemi.com

Intel® 815E Chipset Platform Design Guide 189

Power Delivery

R

This page is intentionally left blank.

190 Intel® 815E Chipset Platform Design Guide

System Design Checklist

R

14 System Design Checklist

14.1 Design Review Checklist

This checklist highlights design considerations that should be reviewed prior to manufacturing a motherboard that implements an 815E chipset platform for use with the universal socket 370 platform. This is not a complete list and does not guarantee that a design will function properly.

The following set of tables provides design considerations for the various portions of a design. Each table describes one of those portions and is titled accordingly. Contact your Intel Field Representative in the event of questions or issues regarding the interpretation of the information in these tables.

14.2 Processor Checklist

14.2.1 GTL Checklist

Checklist Items Recommendations

A[35:3]# 1 • Connect A[31:3]# to GMCH. Leave A[35:32]# as No Connect (not supported by chipset).

BNR#, BPRI#, DBSY#, • Connect to GMCH. DEFER#, DRDY#, D[63:0]#, HIT#, HITM#, LOCK#, REQ[4:0]#, RS[2:0]#, TRDY#

ADS# • Resistor site for 56 Ω pull-up to VTT placed within 150 mils of GMCH for debug purpose. Connect to GMCH.

BREQ[0]# (BR0#) • 33 Ω pull-down resistor to ground

RESET# (AH4) • Terminate to VTT through 86 Ω resistor, decoupled through 22 Ω resistor in series with 10 pF capacitor to ground. Connect to GMCH. For ITP, also connect to ITP pin 2 (RESET#) with 240 Ω series resistor.

RESET2# (X4) • 1 kΩ series resistor to RESET#.

Intel® 815E Chipset Platform Design Guide 191

System Design Checklist

R

14.2.2 CMOS Checklist

Checklist Items Recommendations

IERR# • 150 Ω pull-up resistor to VCCCMOS if tied to custom logic, or leave as No Connect (not used by chipset)

PREQ# • 200–300 Ω pull-up resistor to VCCCMOS / Connect to ITP or else leave as No Connect.

THERMTRIP# • See Section 5.3.1.

A20M#, IGNNE#, • Connect to Intel® ICH2. External pull-ups are not needed. INIT#, INTR, NMI, SLP#, SMI#, STPCLK#

FERR# • Requires 150 Ω pull-up to VCCCMOS/Connect to ICH2.

FLUSH# • Requires 150 Ω pull-up to VCCCMOS. (Not used by chipset.) PWRGOOD • 330 Ω pull-up to VCC2_5 /1.8 kΩ pull-down resistor to ground /Connect to POWERGOOD logic.

14.2.3 TAP Checklist for 370-Pin Socket Processors

Checklist Items Recommendations

TCK • 39 Ω pull-down resistor to ground / Connect to ITP.

TMS • 39 Ω pull-up resistor to VCMOS / Connect to ITP

TDI • 200–330 Ω pull-up resistor to VCMOS / Connect to ITP.

TDO • 150 Ω pull-up resistor to VCMOS / Connect to ITP.

TRST# • 500-680 Ω pull-down resistor to ground / Connect to ITP.

PRDY# • Pull-up resistor that matches GTL characteristic impedance to VTT / 240 Ω series resistor to ITP.

Note: Resistors need to be placed within 1inch of the TAP connector.

192 Intel® 815E Chipset Platform Design Guide

System Design Checklist

R

14.2.4 Miscellaneous Checklist for 370-Pin Socket Processors

Checklist Items Recommendations

BCLK • Connect to clock generator. / 22–33 Ω series resistor (though OEM needs to simulate based on driver characteristics). To reduce pin-to-pin skew, tie host clock outputs together at the clock driver then route to the GMCH and processor.

BSEL0 • Case 1 (66/100/133 MHz support): 1 kΩ pull-up resistor to 3.3 V. Connect to CK815 SEL0 input. Connect to GMCH LMD29 pin via 10 kΩ series resistor. • Case 2 (100/133 MHz support): 1 kΩ pull-up resistor to 3.3 V. Connect to PWRGOOD logic such that a logic Low on BSEL0 negates PWRGOOD.

BSEL1 • 1 kΩ pull-up resistor to 3.3 V. Connect to CK815 REF pin via 10 kΩ series resistor. Connect to GMCH LMD13 pin via 10 kΩ series resistor.

CLKREF • Connect to divider on VCC2.5 or VCC3.3 to create 1.25V reference with a 4.7 µF decoupling capacitor. Resistor divider must be created from 1% tolerance resistors. Do not use VTT as source voltage for this reference!

CPUPRES# • Tie to ground. Leave as No Connect or connect to PWRGOOD logic to gate system from powering on if no processor is present. If used, 1 kΩ to 10 kΩ pull-up resistor to VCCCMOS. DYN_OE • 1 kΩ pull-up resistor to VTT.

PICCLK • See Section 11.5.

PICD[1:0] • 150 Ω pull-up resistor to VCCCMOS/Connect to ICH2.

PLL1, PLL2 • Low-pass filter on VCCCORE provided on motherboard. Typically a 4.7 µH inductor in series with VCCCORE is connected to PLL1, and then through a series 33 µF capacitor to PLL2.

RTTCTRL (S35) • 56 Ω ± 1% pull-down resistor to ground.

SLEWCTRL (E27) • 110 Ω ± 1% pull-down resistor to ground.

STPCLK# (AG35) • Connect to ICH2.

THERMDN, • No Connect if not used. Otherwise, connect to thermal sensor using vendor THERMDP guidelines.

VCC2.5 • No connect for Intel® Pentium® III processors

GTL_REF/ • Connect to a 1.0V voltage divider derived from VCCCMOS. See Section 4.2.7. CMOSREF (AK22)

VCCCORE • 16 ea. (min.) 4.7 µF in 1206 package all placed within the PGA370 socket cavity. • 8 ea. (min.) 1 µF in 0612 package placed in the PGA370 socket cavity.

VID[25mV, 3:0] • Connect to on-board VR or VRM. 25mV should connect to VID25mV. For on- board VR, 10 kΩ pull-up resistor to power solution-compatible voltage is required (usually pulled up to input voltage of the VR). Some of these solutions have internal pull-ups. Optional override (jumpers, ASIC, etc.) could be used. May also connect to system monitoring device.

VTTPWRGD • Pull up to VTT through 1 kΩ resistor and connect to VTTPWRGD circuitry.

Intel® 815E Chipset Platform Design Guide 193

System Design Checklist

R

Checklist Items Recommendations

VREF[6:0] • Connect to VREF voltage divider made up of 75 Ω and 150 Ω 1% resistors connected to VTT. Processor VREF must be able to be separate from chipset VREF. • Decoupling Guidelines: • 4 ea. (min.) 0.1 µF in 0603 package placed within 500 mils of VREF pins

VTT • Connect AH20, AK16, AL13, AL21, AN11, AN15, G35, G37, AD36, AB36, X34, AA33, AA35, AN21, E23, S33, S37, U35, and U37 to VRM regulators compliant with Intel® VRM guidelines for 0.13 micron processors.. Provide high- and low-frequency decoupling. • Decoupling Guidelines: • 20 ea (min.) 0.1 µF in 0603 package placed as near the VTT processor pins as possible. • 4 ea (min.) 0.47 µF in 0612 package

NO CONNECTS • The following pins must be left as no-connects: A29, A31, A33, AC37, AK24, AK30, AL1, AL11, AM2, AN13, AN23, B36, C29, C31, C33, C35, E21, E29, E31, E35, E37, F10, G33, L33, N33, N35, Q33, Q35, Q37, R2, V4, W35, X2, Y1, Z36.

AJ3 • See Chapter 4.

EDGCTRL (AG1) • See Section 4.2.4.

DETECT (AF36) • See Section 4.2.4.

NCHCTRL (N37) • 14 Ω pull-up resistor to VTT.

14.3 GMCH Checklist

14.3.1 AGP Interface 1X Mode Checklist

Checklist Items Recommendations

RBF#, WBF#, PIPE#, • Pull up to VDDQ through 8.2 kΩ GREQ#, GGNT#, GPAR, GFRAME#, GIRDY#, GTRDY#, GSTOP#, GDEVSEL#, GPERR#, GSERR#, ADSTB0, ADSTB1, SBSTB

ADSTB0#, ADSTB1#, • Pull down to ground through 8.2 kΩ SBSTB#

PME# • Connect to PCI connector 0 device Ah. / Connect to PCI connector 1 device Bh. / Connect to Intel 82559 LAN (if implemented).

TYPEDET# • Connect to AGP voltage regulator circuitry / AGP reference circuitry.

PIRQ#A, PIRQ#B • Pull up to 5 V through 2.7 kΩ. / Follow ref. schematics (other device connections).

194 Intel® 815E Chipset Platform Design Guide

System Design Checklist

R

14.3.2 Designs That Do Not Use the AGP Port

Any external graphics implementation not using the AGP port should terminate the GMCH AGP control and strobe signals in the following way:

Table 44. Recommendations for Unused AGP Port

Signal Pull up / Pull Down

FRAME# Pull-up to +VDDQ

TRDY# Pull-up to +VDDQ

IRDY# Pull-up to +VDDQ

DEVSEL# Pull-up to +VDDQ

STOP# Pull-up to +VDDQ

SERR# Pull-up to +VDDQ

PERR# Pull-up to +VDDQ

RBF# Pull-up to +VDDQ

WBF# Pull-up to +VDDQ

INTA# Pull-up to +VDDQ

INTB# Pull-up to +VDDQ

PIPE# Pull-up to +VDDQ

REQ# Pull-up to +VDDQ

GNT# Pull-up to +VDDQ

GPAR Pull-down to Ground using a 100 kΩ resistor

AD_STB[1:0] Pull-up to +VDDQ

SB_STB Pull-up to +VDDQ

AD_STB[1:0]# Pull-down to Ground

SB_STB# Pull-down to Ground

ST[2:0] Pull-up to +VDDQ

14.3.3 System Memory Interface Checklist

Checklist Items Recommendations

SMAA12 • Connect GMCH through 10 kΩ resistor to transistor junction as per Chapter 4 for systems supporting the universal PGA370 design.

SMAA9 • Connect 10 kΩ to ground.

Intel® 815E Chipset Platform Design Guide 195

System Design Checklist

R

14.3.4 Hub Interface Checklist

Checklist Items Recommendations

HUBREF • Connect to HUBREF generation circuitry.

HL_COMP • Pull up to VCC1.85 through 40 Ω (both GMCH and Intel® ICH2 side).

14.3.5 Digital Video Output Port Checklist

Checklist Items Recommendations

DVI Input Reference • See reference schematics in the documentation of the third party vendor of Circuit the device of choice in your design. The Third-Party Vendor information is a part of this design guide and its associated design guide updates.

14.4 Intel® ICH2 Checklist

14.4.1 PCI Interface

Checklist Items Recommendations

All • All inputs to the Intel® ICH2 must not be left floating. Many GPIO signals are fixed inputs that must be pulled up to different sources. See Section 0 for recommendations.

PERR#, SERR# • These signals require a pull-up resistor. Recommend an 8.2 kΩ pull-up PLOCK#, STOP# resistor to VCC3.3 or a 2.7 kΩ ohm pull-up resistor to VCC5. See PCI 2.2 DEVSEL#, TRDY# Component Specification for pull-up recommendations for VCC3.3 and IRDY#, FRAME# VCC5. REQ[4:0] #, GPIO[1:0], THRM#

PCIRST# • The PCIRST# signal should be buffered to form the IDERST# signal. • 33 Ω series resistor to IDE connectors.

PCIGNT# • No external pull-up resistors are required on PCI GNT signals. However, if external pull-up resistors are implemented they must be pulled up to VCC3.3.

PME# • No extra pull-up resistors This signal has an integrated pull-up resistor of 24 kΩ.

SERIRQ • External weak (8.2 kΩ) pull-up resistor to VCC3.3 is recommended.

GNT[A]#, /GPIO[16], • No extra pull-up needed. These signals have integrated pull-ups of 24 kΩ. GNT[B]/ GNT[5]#/ • GNT[A] has an added strap function of “top block swap”. The signal is GPIO[17] sampled on the rising edge of PWROK. Default value is high or disabled due to pull-up. A Jumper to a pull-down resistor can be added to manually enable the function.

196 Intel® 815E Chipset Platform Design Guide

System Design Checklist

R

14.4.2 Hub Interface

Checklist Items Recommendations

HL11 • No pull-up resistor required. Use a no-stuff or a test point to put the Intel® ICH2 into NAND chain mode testing

HL_COMP • Tie the COMP pin to a 40Ω 1% or 2% (or 39 Ω 1%) pull-up resistor (to VCC1.85) via a 10 mil wide, very short (~0.5 inch) trace. ZCOMP No longer supported.

14.4.3 LAN Interface

Checklist Items Recommendations

LAN_CLK • Connect to LAN_CLK on Platform LAN Connect Device.

LAN_RXD[2:0] • Connect to LAN_RXD on Platform LAN Connect Device. Intel® ICH2 contains integrated 9 kΩ pull-up resistors on interface.

LAN_TXD[2:0] • Connect to LAN_TXD on Platform LAN Connect Device. LAN_RSTSYNC

NOTES: 1. LAN connect interface can be left NC if not used. Input buffers internally terminated. 2. In the event of EMI problems during emissions testing (FCC Classifications) you may need to place a decoupling cap (~470 pF) on each of the 4 LED pins. Reduces emissions attributed to LAN subsystem.

14.4.4 EEPROM Interface

Checklist Items Recommendations

EE_DOUT • Prototype Boards should include a placeholder for a pull-down resistor on this signal line, but do not populate the resistor. Connect to EE_DIN of EEPROM or CNR Connector. • Connected to EEPROM data input signal (input from EEPROM perspective and output from Intel® ICH2 perspective).

EE_DIN • No extra circuitry required. Connect to EE_DOUT of EEPROM or CNR Connector. ICH2 contains an integrated pull-up resistor for this signal. • Connected to EEPROM data output signal (output from EEPROM perspective and input from ICH2 perspective).

14.4.5 FWH/LPC Interface

Checklist Items Recommendations

FWH[3:0]/ LAD[3:0] • No extra pull-ups required. Intel® ICH2 Integrates 24 kΩ pull-up resistors on these signal lines. LDRQ[1:0]

Intel® 815E Chipset Platform Design Guide 197

System Design Checklist

R

14.4.6 Interrupt Interface

Checklist Items Recommendations

PIRQ#[D:A] • These signals require a pull-up resistor. The recommendation is a 2.7 kΩ pull-up resistor to VCC5 or 8.2 kΩ to VCC3.3. • In Non-APIC Mode the PIRQx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the Intel® ICH2 datasheet. Each PIRQx# line has a separate Route Control Register. • In APIC mode, these signals are connected to the internal I/O APIC in the following fashion: PIRQ[A]# is connected to IRQ16, PIRQ[B]# to IRQ17, PIRQ[C]# to IRQ18, and PIRQ[D]# to IRQ19.

PIRQ#[G:F]/ GPIO[4:3] • These signals require a pull-up resistor. Recommend a 2.7 kΩ pull-up resistor to VCC5 or 8.2 kΩ to VCC3.3. • In Non-APIC Mode the PIRQx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the ICH2 datasheet. Each PIRQx# line has a separate Route Control Register. • In APIC mode, these signals are connected to the internal I/O APIC in the following fashion: PIRQ[E]# is connected to IRQ20, PIRQ[F]# to IRQ21, PIRQ[G]# to IRQ22, and PIRQ[H]# to IRQ23.

PIRQ#[H] • These signals require a pull-up resistor. Recommend a 2.7 kΩ pull-up resistor to VCC5 or 8.2 kΩ to VCC3.3. PIRQ#[E] • Since PIRQ[H]# and PIRQ[E]# are used internally for LAN and USB controllers, they cannot be used as GPIO(s) pin.

APIC • If the APIC is used:  150 Ω pull-up resistors on APICD[0:1]  Connect APICCLK to CK133 with a 20–33 Ω series termination resistor. • If the APIC is not used on UP systems:  The APICCLK can either be tied to GND or connected to CK133, but not left floating.  Pull APICD[0:1] to GND through 10 kΩ pull-down resistors.  Use pull-downs for each APIC signal. Do not share resistor to pull signals up.

198 Intel® 815E Chipset Platform Design Guide

System Design Checklist

R

14.4.7 GPIO Checklist

Checklist Items Recommendations

All • Ensure ALL unconnected signals are OUTPUTS ONLY!

GPIO[7:0] • These pins are in the Main Power Well. Pull-ups must use the VCC3.3 plane. Unused core well inputs must either be pulled up to VCC3.3 or be pulled down. Inputs must not be allowed to float. These signals are 5V tolerant. • GPIO[1:0] can be used as REQ[A:B]#. GPIO[1] can also be used as PCI REQ[5]#.

GPIO[8], [13:11]- • These pins are in the Resume Power Well. Pull-ups must use the VCCSUS3.3 plane. These are the only GPI signals in the resume well with associated status bits in the GPE1_STS register. Unused resume well inputs must be pulled up to VCCSUS3.3. These signals are not 5V tolerant. • These are the only GPIs that can be used as ACPI compliant wake events.

GPIO[23:16] • Fixed as output only. Can be left NC. In Main Power Well. GPIO22 is open drain.

GPIO[24,25,27,28] • These I/O pins can be NC. These pins are in the resume power well.

14.4.8 USB

Checklist Items Recommendations

USBP[3:0]P • See Figure 111 for circuitry needed on each differential Pair. USBP[3:0]N

VCC USB (Cable power) • It should be powered from the 5V core instead of the 5V standby, unless adequate standby power is available.

Voltage drop • The resistive component of the fuses, ferrite beads and traces must be considerations considered when choosing components, and power and GND trace widths. Minimize the resistance between the VCC5 power supply and the USB ports to prevent voltage drop. • Sufficient bypass capacitance should be located near the USB receptacles to minimize the voltage drop that occurs during the hot plugging a new device. For more information, see the USB specification.

Fuse • A fuse larger than 1A can be chosen to minimize the voltage drop.

Intel® 815E Chipset Platform Design Guide 199

System Design Checklist

R

Figure 111. USB Data Line Schematic

Motherboard trace Driver 15 Ω < 1" P+ 45 Ω

Ω 15 k Optional 47 pf 90 Ω Motherboard trace Driver 15 Ω < 1" connector USB P- 45 Ω

15 kΩ Optional 47 pf

ICH2 Transmission line USB twisted-pair cable

usb_data_line_schem

14.4.9 Power Management

Checklist Items Recommendations

THRM# • Connect to temperature Sensor. Pull-up if not used.

SLP_S3# • No pull-up/down resistors needed. Signals driven by Intel® ICH2. SLP_S5#

PWROK • This signal should be connected to power monitoring logic, and should go high no sooner than 10 ms after both VCC3_3 and VCC1_8 have reached their nominal voltages. For systems implementing the universal PGA370 design, this signal must be connected to the gating circuit found in Section 4.

PWRBTN# • No extra pull-up resistors. This signal has an integrated pull-up of 24 kΩ.

RI# • RI# does not have an internal pull-up. Recommend an 8.2 kΩ pull-up resistor to Resume well • If this signal is enabled as a wake event, it is important to keep this signal powered during the power loss event. If this signal goes low (active), when power returns the RI_STS bit will be set and the system will interpret that as a wake event.

RSMRST# • Connect to power monitoring logic, and should go high no sooner than 10 ms after both VccSUS3_3 and VccSus1_8 have reached their nominal voltages. Requires weak pull-down. Also requires well isolation control as directed in Section 11.8.6

200 Intel® 815E Chipset Platform Design Guide

System Design Checklist

R

14.4.10 Processor Signals

Checklist Items Recommendations

A20M#, CPUSLP#, • Internal circuitry has been added to the Intel® ICH2, external pull-up resistors IGNNE#, INIT#, are not needed. INTR, NMI, SMI#, STPCLK#

FERR# • Requires Weak external pull-up resistor to VCCCMOS. RCIN# • Pull-up signals to VCC3.3 through a 10 kΩ resistor. A20GATE

CPUPWRGD • Connect to the processor’s CPUPWRGD input. Requires weak external pull-up resistor.

14.4.11 System Management

Checklist Items Recommendations

SMBDATA • Requires external pull-up resistors. See SMBus Architecture and Design Consideration section to determine the appropriate power well to use to tie the SMBCLK pull-up resistors. (Core well, suspend well, or a combination.) • Value of pull-up resistors determined by line load. Typical value used is 8.2 kΩ.

SMBALERT#/ • See GPIO section if SMBALERT# not implemented GPIO[11]

SMLINK[1:0] • Requires external pull-up resistors. See SMBus Architecture and Design Consideration section to determine the appropriate power well to use to tie the pull-up resistors. (Core well, suspend well, or a combination.) • Value of pull-up resistors determined by line load. Typical value used is 8.2 kΩ.

INTRUDER# • Pull signal to VCCRTC (VBAT), if not needed.

14.4.12 RTC

Checklist Items Recommendations

VBIAS • The VBIAS pin of the Intel® ICH2 is connected to a .047 µF capacitor. See Figure 112

RTCX1 • Connect a 32.768 kHz crystal oscillator across these pins with a 10 MΩ resistor and use 18 pF decoupling capacitors (assuming crystal with CLOAD = 12.5 pF) at RTCX2 each signal. • The ICH2 implements a new internal oscillator circuit as compared with the PIIX4 to reduce power consumption. The external circuitry shown in Figure 112 below will be required to maintain the accuracy of the RTC. • The circuitry is required since the new RTC oscillator is sensitive to step voltage changes in VCCRTC and VBIAS. A negative step on power supply of more than 100 mV will temporarily shut off the oscillator for hundreds of milliseconds. • RTCX1 may optionally be driven by an external oscillator instead of a crystal. These signals are 1.85V only, and must not be driven by a 3.3V source.

RTCRST# • Ensure 10 ms–20 ms RC delay (8.2 K and 2.2 µF) See Figure 85

SUSCLK • To assist in RTC circuit debug, route SUSCLK to a test point if it is unused.

Intel® 815E Chipset Platform Design Guide 201

System Design Checklist

R

Figure 112. Intel® ICH2 Oscillator Circuitry

VCC3_3SBY

VCCRTC 2

1.0uF 1kΩ

32768 Hz RTCX2 3 Xtal

R1 10MΩ 1kΩ RTCX1 4 C1 VBAT_RTC R2 0.047uF C3 1 10MΩ

VBIAS 5

C2 1

VSS 6

NOTE: Capacitors C2 and C3 are crystal dependent

14.4.13 AC ’97

Checklist Items Recommendations

AC_BITCLK • No extra pull-down resistors required. • When nothing is connected to the link, BIOS must set a shut off bit for the internal keeper resistors to be enabled. At that point, you do not need pull- ups/pull-downs on any of the link signals.

AC_SYNC • No extra pull-down resistors required. Some implementations add termination for signal integrity. Platform specific.

AC_SDOUT • Requires a jumper to 8.2 kΩ pull-up resistor. Should not be stuffed for default operation. • This pin has a weak internal pull-down. To properly detect a safe_mode condition a strong pull-up will be required to over-ride this internal pull-down.

AC_SDIN[1], • Requires pads for weak 10 kΩ pull-downs. Stuff resistor for unused AC_SDIN AC_SDIN[0] signal or AC_SDIN signal going to the CNR connector. • AC_SDIN[1:0] are inputs to an internal OR gate. If a pin is left floating, the output of the OR gate will be erroneous. • If there is no codec on the system board, then both AC_SDIN[1:0] should be pull-down externally with resisters to ground.

CDC_DN_ENAB# • If the primary codec is down on the motherboard, this signal must be low to indicate the motherboard codec is active and controlling the AC ’97 interface.

202 Intel® 815E Chipset Platform Design Guide

System Design Checklist

R

14.4.14 Miscellaneous Signals

Checklist Items Recommendations

SPKR • No extra pull-up resistors. Has integrated pull-up of between 18 kΩ and 42 kΩ. The integrated pull-up is only enabled at boot/reset for strapping functions; at all other times, the pull-up is disabled. • A low effective impedance may cause the TCO Timer Reboot function to be erroneously disabled. • Effective Impedance due Speaker and Codec circuitry must be greater than 50 kΩ or a means to isolate the resistive load from the signal while PWROK is low be found. See Figure 113.

TP[0] • Requires external pull-up resistor to VCCSUS3.3

FS[0] • Rout to a test point. Intel® ICH2 contains an integrated pull-up for this signal. Test point used for manufacturing appears in XOR tree.

Figure 113. SPKR Circuitry

ICH2 3.3V

Integrated Pull-Up 18-42 KΩ

Stuff Jumper To Effective Impedance Disable Timeout Due To Speaker and Feature. Codec Circuit. Reff > 50 KΩ R < 7.3 KΩ

Spkr_Ckt_815E_B0

Intel® 815E Chipset Platform Design Guide 203

System Design Checklist

R

14.4.15 Power

Checklist Items Recommendations

V_CPU_IO[1:0] • The power pins should be connected to the proper power plane for the processor's CMOS Compatibility Signals. Use one 0.1 µF decoupling capacitor.

VCCRTC • No clear CMOS jumper on VCCRTC. Use a jumper on RTCRST# or a GPI, or use a safemode strapping for Clear CMOS

VCC3.3 • Requires six 0.1 µF decoupling capacitor

VCCSus3.3 • Requires one 0.1 µF decoupling capacitor.

VCC1.85 • Requires two 0.1 µF decoupling capacitor s.

VCCSus1.85 • Requires one 0.1 µF decoupling capacitor.

V5_REF SUS • Requires one 0.1 µF decoupling capacitor. • V5REF_SUS affects 5V-tolerance for all USB pins and can be connected to VccSUS3_3 if Intel® ICH2 USB is not supported in the platform. If USB is supported, V5REF_SUS must be connected to 5V_AUX, which remains powered during S5.

V5_REF • V5REF is the reference voltage for 5V tolerant inputs in the ICH2. Tie to pins VREF[2:1]. V5REF must power up before or simultaneous to VCC3_3. It must power down after or simultaneous to VCC3_3. Refer to Figure 114 for an example circuit schematic that may be used to ensure the proper V5REF sequencing.

VCMOS • VCMOS power source must supply 1.5 V and be generated by circuitry on the motherboard. Do not connect to VTT. See Appendix A: Customer Reference Board CRB).

Figure 114. V5REF Circuitry

Vcc Supply (3.3 V) 5V Supply

1 KΩ

1 µ F

To System VREF To System

3.3V_5V_Seq_Ckt_815E_B0

204 Intel® 815E Chipset Platform Design Guide

System Design Checklist

R

14.4.16 IDE Checklist

Checklist Items Recommendations

PDD[15:0], • No extra series termination resistors or other pull-ups/pull-downs are required. SDD[15:0] These signals have integrated series resistors. Note that simulation data indicates that the integrated series termination resistors can range from 31 Ω to 43 Ω. • PDD7/SDD7 does not require a 10 kΩ pull-down resistor. Refer to ATA ATAPI-4 specification.

PDIOW#, PDIOR#, • No extra series termination resistors. Pads for series resistors can be PDDACK#, PDA[2:0], implemented should the system designer have signal integrity concerns. These PDCS1#, PDCS3#, signals have integrated series resistors. Note that simulation data indicates SDIOW#, SDIOR#, that the integrated series termination resistors can range from 31 Ω to 43 Ω. SDDACK#, SDA[2:0], SDCS1#, SDCS3#

PDREQ • No extra series termination resistors. No pull-down resistors needed. SDREQ • These signals have integrated series resistors in the Intel® ICH2. These signals have integrated pull-down resistors in the ICH2.

PIORDY • No extra series termination resistors. These signals have integrated series resistors in the ICH2. Pull-up to VCC3.3 via a 4.7 kΩ resistor. SIORDY

IRQ14, IRQ15 • Recommend 8.2 kΩ—10 kΩ pull-up resistors to VCC3.3. • No extra series termination resistors.

IDERST# • The PCIRST# signal should be buffered to form the IDERST# signal. A 33 Ω series termination resistor is recommended on this signal.

Cable Detect: • Host Side/Device Side Detection:  Connect IDE pin PDIAG/CBLID to an ICH2 GPIO pin. Connect a 10 kΩ resistor to GND on the signal line. The 10 kΩ resistor to GND prevents GPI from floating if no devices are present on either IDE interface. Allows use of 3.3V and 5V tolerant GPIOs. • Device Side Detection:  Connect a 0.047 µF capacitor from IDE pin PDIAG/CBLID to GND. No ICH2 connection. Note that all ATA66/ATA100 drives will have the capability to detect cables

NOTE: The maximum trace length from the ICH2 to the ATA connector is 8 inches.

Intel® 815E Chipset Platform Design Guide 205

System Design Checklist

R

Figure 115. Host/Device Side Detection Circuitry

IDE drive IDE drive 5 V 5 V To secondary Ω IDE connector 10 kΩ 10 k 40-conductor GPIO cable ICH2 PDIAG# PDIAG#/ PDIAG# CBLID# GPIO 10 kΩ

IDE drive IDE drive 5 V 5 V To secondary IDE connector 10 kΩ 10 kΩ 80-conductor GPIO IDE cable PDIAG# PDIAG# ICH2 PDIAG#/ CBLID# GPIO 10 kΩ Open IDE_combo_cable_det

Figure 116. Device Side Only Cable Detection

IDE drive IDE drive 5 V 5 V Ω 10 kΩ 10 k 40-conductor cable ICH2 PDIAG# PDIAG#/ PDIAG# CBLID#

0.047 µF IDE drive IDE drive 5 V 5 V

10 kΩ 10 kΩ 80-conductor IDE cable PDIAG# PDIAG# ICH2 PDIAG#/ CBLID#

0.047 µF Open IDE_dev_cable_det

206 Intel® 815E Chipset Platform Design Guide

System Design Checklist

R

14.5 LPC Checklist

Checklist Items Recommendations

RCIN#/KBRST# • Pull up through 8.2 kΩ resistor to VCC3_3.

LPC_PME# • Pull up through 8.2 kΩ resistor to VCC3_3. Do not connect LPC PME# to PCI PME#. If the design requires the Super I/O to support wake from any suspend state, connect Super I/O LPC_PME# to a resume well GPI on the Intel® ICH2.

J1BUTTON1, • Connect through 1 kΩ series resistor / decouple through 1000 pF capacitor J2BUTTON2, to GND, followed by 4.7 kΩ pull-up to VCC5 / decouple through 470 pF J2BUTTON1, capacitor to GND. J2BUTTON2

JOY1X, JOY2X, • Connect through 1 kΩ series resistor / decouple through 22 pF capacitor to JOY1Y, JOY2Y GND, followed by 4.7 kΩ pull-up to VCC5 / decouple through 470 pF capacitor to GND.

A20GATE • Pull up through 8.2 kΩ resistor to VCC3_3.

CASEOPEN# • Pull up through 10 MΩ resistor to VCCRTC / connect to switch to GND.

KEYLOCK# • Pull up through 10 kΩ resistor to VCC5.

MCLK, MDAT, KCLK, • Pull up through 4.7 kΩ resistor to VCC5_Dual. KDAT

MIDI_IN, MIDI_OUT • Pull up through 4.7 kΩ resistor to VCC5, followed by 47 Ω series resistor / decouple through a 470 pF capacitor to GND.

RI#1, CTS#0, RXD1, • Decoupled using 100 pF capacitor to GND. RXD0, RI#0, DCD#1, DSR#1, DSR#0, DTR#1, DTR#0, DCD#0, RTS#1, RTS#0, CTS#1, TXD1, TXD0

SERIRQ Pull up through 8.2 kΩ resistor to VCC3_3.

LFRAME# No required pull-up resistor

LDRQ#0 No required pull-up resistor

Intel® 815E Chipset Platform Design Guide 207

System Design Checklist

R

14.6 System Checklist

Checklist Items Recommendations

KEYLOCK# • Pull up through 10 kΩ resistor to VCC3_3.

PBTN_IN • Connects to PBSwitch and PBin.

PWRLED • Pull up through a 220 Ω resistor to VCC5.

R_IRTX • Signal IRTX after it is pulled down through 4.7 kΩ resistor to GND and passes through 82 Ω resistor.

IRRX • Pull up to 100 kΩ resistor to VCC3_3. • When signal is input for SI/O decouple through 470 pF capacitor to GND

IRTX • Pull down through 4.7 kΩ to GND. • Signal passes through 82 Ω resistor. • When signal is input to SI/O decouple through 470 pF capacitor to GND

FP_PD • Decouple through a 470 pF capacitor To GND. • Pull up 470 Ω to VCC5.

PWM1, PWM2 • Pull up through a 4.7 kΩ resistor to VCC3_3.

14.7 FWH Checklist

Checklist Items Recommendations

No floating inputs • Unused FGPI pins must be tied to a valid logic level.

WP#, TBL# • Connect to Intel® ICH2.

VPP • Pulled up to VCC3_3 and decoupled with a 0.1 µF capacitor to GND.

FGPI0, FGPI1, FGPI2, • Pull down through a 8.2 kΩ resistor to GND. FPGI3, FPGI4, IC

INIT# • FWH INIT# must be connected to processor INIT#.

RST# • FWH RST# must be connected to PCIRST#.

ID[3:0] • For a system with only one FWH device, tie ID[3:0] to ground.

NOTE: These recommendations are only valid for the Intel® Firmware Hub.

208 Intel® 815E Chipset Platform Design Guide

System Design Checklist

R

14.8 Clock Synthesizer Checklist

Checklist Items Recommendations

REFCLK • Connects to R-RefCLK, USB_CLK, SIO_CLK14, and ICHCLK14. ICH_3V66/3V66_0, • Passes through 33 Ω resistor. DOTCLK • When signal is input for Intel® ICH, it is pulled down through a 18 pF capacitor to GND. DCLK/DCLK_WR • Passes through 33 Ω resistor. • When signal is input for GMCH, it is pulled down through a 22 pF capacitor to GND. CPUHCLK/CPU_0_1 • Passes through 33 Ω resistor. • When signal is input for 370PGA, decouple through a 18 pF capacitor to GND. R_REFCLK • REFCLK passed through 10 kΩ resistor. • When signal is input for 370PGA, pull up through 1 kΩ resistor to VCC3_3 and pass through 10 kΩ resistor. USB_CLK, ICH_CLK14 • REFCLK passed through 10 Ω resistor. XTAL_IN, XTAL_OUT • Passes through 14.318 MHz oscillator. • Pulled down through 18 pF capacitor to GND. SEL1_PU • Pulled up via MEMV3 circuitry through 8.2 kΩ resistor. FREQSEL • Connected to clock frequency selection circuitry through 10 kΩ resistor. (See CRB schematic, page 4.) L_VCC2_5 • Connects to VDD2_5[0…1] through ferrite bead to VCC2_5. GMCHHCLK/CPU_1, • Passes through 33 Ω resistor. ITPCLK/CPU_2, PCI_0/PCLK_OICH, PCI_1/PCLK_1, PCI_2/PCLK_2, PCI_3/PCLK_3, PCI_4/PCLK_4, PCI_5/PCLK_5, PCI_6/PCLK_6, APICCLK_CPU/APIC_0, APICCLK)ICH/APIC_1, USBCLK/USB_0, GMCH_3V66/3V66_1, AGPCLK_CONN MEMCLK0/DRAM_0, Pass through 10 Ω resistor. MEMCLK1/DRAM_1, MEMCLK2/DRAM_2, MEMCLK3/DRAM_3, MEMCLK4/DRAM_4, MEMCLK5/DRAM_5, MEMCLK6/DRAM_6, MEMCLK7/DRAM_7 SCLK Pass through 22 Ω resistor. VCC3.3 Connected to VTTPWRGD gating circuit according to information in Section 4.3.1 for systems supporting the universal PGA370 design.

Intel® 815E Chipset Platform Design Guide 209

System Design Checklist

R

14.9 System Memory Checklist

Checklist Items Recommendations

SM_CSA#[0:3, • Connect from GMCH to DIMM0, DIMM1. SM_CSB#[3:0, SMAA[11:8,3:0], SM_MD[0:63], SM_CKE[0:3], S_DQM[0:7]

SM_MAA[7:4], • Connect from GMCH to DIMM0, DIMM1 through 10 Ω resistors. SM_MAB[7:4]#

SM_CAS# • Connected to R_REFCLK through 10 kΩ resistor.

SM_RAS# • Jumpered to GND through 10 kΩ resistor.

SM_WE# • Connected to R_BSEL0# through 10 kΩ resistor.

CKE[5…0] (For 3-DIMM • When implementing a 3-DIMM configuration, all six CKE signals on the implementation) GMCH are used. (0,1 for DIMM0; 2, 3 for DIMM1; 4,5 for DIMM2)

REGE • Connect to GND (since this Intel® 815E chipset platform does not support registered DIMMs).

WP (Pin 81 on the • Add a 4.7 kΩ pull-up resistor to 3.3 V. This recommendation write-protects DIMMS) the DIMMs EEPROM.

SRCOMP • Needs a 40 Ω resistor pulled up to 3.3 V standby.

14.10 Power Delivery Checklist

Checklist Items Recommendations

All voltage regulator components meet • Consider all loads on a regulator, including other maximum current requirements. regulators.

All regulator components meet thermal • Ensure the voltage regulator components and dissipate requirements. the required amount of heat.

VCC1_8 pins • These power pins must be supplied by a 1.85 V source and be between (1.795 V to 1.905 V).

If devices are powered directly from a dual • “Dual” voltage rails may not be at the expected voltage. rail (i.e., not behind a power regulator), then the RDSon of the FETs used to create the dual rail must be analyzed to ensure there is not too much voltage drop across the FET.

Dropout voltage • The minimum dropout for all voltage regulators must be considered. Take into account that the voltage on a dual rail may not be the expected voltage.

Voltage tolerance requirements are met. • See the individual component specifications for each voltage tolerance.

210 Intel® 815E Chipset Platform Design Guide

Third-Party Vendor Information

R

15 Third-Party Vendor Information

This design guide has been compiled to give an overview of important design considerations while providing sources for additional information. This chapter includes information regarding various third-party vendors who provide products to support the 815E chipset platform. The list of vendors can be used as a starting point for the designer. Intel does not endorse any one vendor, nor guarantee the availability or functionality of outside components. Contact the manufacturer for specific information regarding performance, availability, pricing and compatibility.

Super I/O (Vendors Contact Phone) • SMSC Dave Jenoff (909) 244-4937 • National Semiconductor Robert Reneau (408) 721-2981 • ITE Don Gardenhire (512)388-7880 • Winbond James Chen (02) 27190505 - Taipei office

Clock Generation (Vendors Contact Phone) • Cypress Semiconductor John Wunner 206-821-9202 x325 • ICS Raju Shah 408-925-9493 • IMI Elie Ayache 408-263-6300, x235 • PERICOM Ken Buntaran 408-435-1000

Memory Vendors

http://developer.intel.com/design/motherbd/se/se_mem.htm

Voltage Regulator Vendors (Vendors Contact Phone)

Analog Devices Richard Carlson (408) 382-3258

On Semiconductor Tod Shift (503) 203-7920

Semtech Jason Bowles (408) 566-8729

Interisel Gary Wiggins (360) 921-4421

Fairchild Semiconductor Ron Lenk (408) 822-2546

Firmware Hub Vendors (Vendors Contact Phone) • Silicon Storage Technology TBD • STMicroelectronics TBD

Intel® 815E Chipset Platform Design Guide 211

Third-Party Vendor Information

R

GPA (a.k.a. AIMM) Card (Vendors Contact Phone) • Kingston [email protected] [email protected] • Smart Modular [email protected] [email protected] • Micron Semiconductor TBD

TMDS Transmitters

Silicon Images John Nelson (408) 873-3111

Texas Instrument Greg Davis [[email protected]] (214) 480-3662

Chrontel Chi Tai Hong [[email protected]] (408) 544-2150

TV Encoders

Chrontel Chi Tai Hong [[email protected]] (408)544-2150

Conexant Eileen Carlson [[email protected]] (858) 713-3203

Focus Bill Schillhammer [[email protected]] (978) 661-0146

Philips Marcus Rosin [[email protected]]

Texas Instrument Greg Davis[[email protected]] (214) 480-3662

Combo TMDS Transmitters/TV Encoders

Chrontel Chi Tai Hong [[email protected]] (408) 544-2150

Texas Instrument Greg Davis[[email protected]] (214) 480-3662

LVDS Transmitter

National Semiconductor 387R Jason Lu [[email protected]] (408) 721-7540

212 Intel® 815E Chipset Platform Design Guide

Appendix A: Customer Reference Board CRB)

R

Appendix A: Customer Reference Board CRB)

This appendix provides a set of Customer Reference Board (CRB) schematics for the 815E chipset platform for use with universal socket 370.

Intel® 815E Chipset Platform Design Guide 213

A B C D E Intel(R) Pentium(R) III and FC-PGA Celeron(tm) Processor / 815E Chipset Universal Socket 370 Platform Customer Reference Board Schematics 4 4 Revision 1.05 - Fab C

TITLE PAGE COVER SHEET 1 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or BLOCK DIAGRAM 2 otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating PGA370 PART 1 & 2 3,4 to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, AGTL TERMINATION 5 or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, CLOCK GENERATOR 6 life saving, or life sustaining applications. GMCH PART 1 & 2 7,8 Intel may make changes to specifications and product descriptions at any time, without notice. DIMM 1 & 2 9 Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." DIMM 3 10 Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising 3 3 AGP 11 from future changes to them. ICH PART 1 & 2 12,13 The Intel® 815E chipset may contain design defects or errors known as errata which may cause the product to deviate from PCI 1 & 2 14 published specifications. Current characterized errata are available on request. PCI 3 15 Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product VIDEO BUS & CONNECTOR 16 order. FWH & UDMA100 IDE 1-2 17 USB 0-3 18 I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was AC97 CODEC 19 developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. AUDIO I/O 20 LPC I/O CONTROLLER & FDCL 21 Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM. WOR, WOL & 2S1P 22 Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be KB, MS, GAME & IR 23 2 obtained by calling 2 24 FRONT PANEL & CNR 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. ATX POWER & H/W MONITOR 25 VREGS: VDDQ, VCC1_8, AND VTT 26 Intel®, Pentium®, Pentium® III, Celeron™, are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. VREGS: VCCVID, V1_8SB 27 VREGS: DUALS, 3.3SB, 2.5, VCMOS 28 *Other brands and names may be claimed as the property of others. SYSTEM CONFIGURATION 29 PU/PDR & UNUSED GATES 30 Copyright© 2001, Intel Corporation DECOUPLING CAPACITORS 31 INTERNAL DEBUG HEADERS 32 **PLEASE NOTE THESE SCHEMATICS ARE SUBJECT TO CHANGE THERMTRIP 33

1 Document: Intel(R) 815E Chipset Universal Socket 370 CRB 1 Page Name: Title Page Last Revised: Page: Monday, April 30, 2001 Doc: Monday, April 30, 2001 Revision: Platform Applications Engineering 1.05 1900 Prairie City Road Page No: Folsom, CA 95630 1 of 33 A B C D E A B C D E

BLOCK DIAGRAM

VRM 370-PIN SOCKET PROCESSOR CLOCK 4 4 ADDR CTRL DATA

GTL BUS ADDR CTRL DATA

AGP Connector 3 DIMM GMCH Modules

Digital Video 3 Out Device 3 PCI CONN 1 PCI CONN 2 PCI CONN3

IDE Primary PCI CNTRL UDMA/100 IDE Secondary PCI ADDR/DATA ICH2

USB PORT 1-4 USB

2 FirmWare Hub 2

CNR AC'97 LINK Connector

SIO Audio Codec

1 Document: Intel(R) 815E Chipset Universal Socket 370 CRB 1 Page Name: Block Diagram Last Revised: Page: Monday, April 30, 2001 Doc: Monday, April 30, 2001 Keyboard Revision: Floppy Game Port Serial 1 Serial 2 Parallel Platform Applications Engineering 1.05 Mouse 1900 Prairie City Road Page No: Folsom, CA 95630 2 of 33 A B C D E 5 4 3 2 1

VTT VCCVID

HA#[3..31] HA#[3..31] 7

HD#[0..63] HD#[0..63] 7

U3A B26 C3 AK2 AF2 AB2 T2 P2 K2 F4 E5 AM4 AE5 AA5 W5 S5 N5 J5 F2 D6 B6 AM8 AJ9 E9 B10 AM12 AJ13 E13 B14 AM16 AJ5 AJ17 E17 B18 AM20 AJ21 D20 F22 AM24 AJ25 D24 F26 AM28 AJ29 D28 AK34 F30 B30 AM32 AH32 Z32 V32 R32 M32 H32 AF34 AB34 X34 T34 P34 K34 F34 B34 AH36 B22 V36 R36 H36 D36 D32 AD32 AH24 F14 K32 AA37 Y35

D HD#0 W1 AK8 HA#3 D HD#0 HA#3 HD#1 T4 AH12 HA#4 HD#1 HA#4 HD#2 N1 AH8 HA#5 HD#2 HA#5 HD#3 M6 VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID AN9 HA#6 HD#3 HA#6 HD#4 U1 AL15 HA#7 HD#4 HA#7 HD#5 S3 AH10 HA#8 HD#5 HA#8 HD#6 T6 AL9 HA#9 HD#6 HA#9 HD#7 J1 AH6 HA#10 HD#7 HA#10 HD#8 S1 AK10 HA#11 HD#8 HA#11 HD#9 P6 AN5 HA#12 HD#9 HA#12 HD#10 Q3 AL7 HA#13 HD#10 HA#13 HD#11 M4 AK14 HA#14 HD#11 HA#14 HD#12 Q1 AL5 HA#15 HD#12 HA#15 HD#13 L1 AN7 HA#16 HD#13 HA#16 HD#14 N3 AE1 HA#17 VCC3_3 HD#14 HA#17 HD#15 U3 Z6 HA#18 HD#15 HA#18 HD#16 H4 AG3 HA#19 HD#16 HA#19 HD#17 R4 AC3 HA#20 HD#17 HA#20 HD#18 P4 AJ1 HA#21 HD#18 HA#21 2 4 6 8 HD#19 H6 AE3 HA#22 HD#19 HA#22 HD#20 L3 AB6 HA#23 RP3 HD#20 HA#23 HD#21 G1 AB4 HA#24 R371 HD#21 HA#24 10K/8P4R HD#22 F8 AF6 HA#25 HD#22 HA#25 HD#23 G3 Y3 HA#26 10K C HD#23 HA#26 C HD#24 K6 AA1 HA#27 HD#24 HA#27 HD#25 E3 AK6 HA#28 HD#25 HA#28 HD#26 E1 Z4 HA#29 1 3 5 7 HD#26 HA#29 HD#27 F12 AA3 HA#30 HD#27 HA#30 HD#28 A5 AD4 HA#31 HD#28 HA#31 HD#29 A3 X6 HD#29 HA#32 HD#30 J3 AC1 R372 1k HD#30 HA#33 HD#31 C5 W3 HD#31 HA#34 HD#32 F6 AF4 HD#32 HA#35 HD#33 C1 HD#33 370 - Pin Socket Part 1 RP4 HD#34 C7 AL35 CPU_VID0 HD#34 VID0 JPR_VID0 29,32 HD#35 B2 AM36CPU_VID1 1 2 HD#35 VID1 JPR_VID1 29,32 HD#36 C9 AL37 CPU_VID2 3 4 HD#36 VID2 JPR_VID2 29,32 HD#37 A9 AJ37 CPU_VID3 5 6 HD#37 VID3 JPR_VID3 29,32 HD#38 D8 AK36 CPU_VID4 7 8 HD#38 GND/VID4 JPR_VID4 29,32 HD#39 D10 AK18 HD#39 REQ#0 HREQ#0 7 HD#40 C15 AH16 1K/8P4R HD#40 REQ#1 HREQ#1 7 HD#41 D14 AH18 HD#41 REQ#2 HREQ#2 7 HD#42 D12 AL19 HD#42 REQ#3 HREQ#3 7 HD#43 A7 AL17 HD#43 REQ#4 HREQ#4 7 HD#44 A11 C33 HD#44 DEP0# HD#45 C11 C31 HD#45 DEP1# HD#46 A21 A33 HD#46 DEP2# HD#47 A15 A31 B HD#47 DEP3# B HD#48 A17 E31 HD#48 DEP4# HD#49 C13 C29 HD#49 DEP5# HD#50 C25 E29 VTT HD#50 DEP6# HD#51 A13 A29 HD#51 DEP7# HD#52 D16 HD#52 HD#53 A23 AH20 HD#53 VTT1_5 HD#54 C21 AK16 HD#54 VTT1_5 HD#55 C19 AL21 HD#55 VTT1_5 HD#56 C27 AN11 HD#56 VTT1_5 HD#57 A19 AN15 HD#57 VTT1_5 HD#58 C23 G35 HD#58 VTT1_5 HD#59 C17 AL13 HD#59 VTT1_5 HD#60 A25 U37 HD#60 VTT1_5 HD#61 A27 U35 HD#61 VTT1_5 HD#62 E25 S37 HD#62 VTT1_5 HD#63 F16 S33 HD#63 VTT1_5 E23 VTT1_5 AH26 AN21 7 RS#0 RS#0 VTT1_5 AH22 AA35 7 RS#1 RS#1 VTT1_5 AK28 AA33

7 RS#2 RS#2 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VTT1_5

Socket 370_9 AM34 AH2 AD2 Z2 V2 M2 D18 H2 D2 AL3 AG5 AC5 Y5 U5 Q5 L5 G5 D4 B4 AM6 AJ7 E7 B8 AM10 AJ11 E11 B12 AM14 AJ15 E15 B16 AM18 AJ19 E19 F20 B20 AM22 AJ23 D22 F24 B24 AM26 AJ27 D26 F28 B28 AM30 D30 AF32 AB32 X32 T32 P32 F32 B32 AH34 AD34 Z34 V34 R34 M34 H34 D34 X36 T36 P36 K36 F36 A37 AC33 Y37 A Document: Intel(R) 815E Chipset Universal Socket 370 CRB A Page Name: 370-pin Socket Part 1 Last Revised: Page: Monday, April 30, 2001 Doc: Monday, April 30, 2001 Revision: Platform Applications Engineering 1.05 1900 Prairie City Road Page No: Folsom, CA 95630 3 of 33 5 4 3 2 1 5 4 3 2 1

BSEL#1 BSEL#0 FSB 0 0 66M No-stuff R199 - see p.33. 0 1 100M 1 0 rsvd Stuff either R5 or R415. See p33. 1 1 133M VTT VCC2_5 VCMOS

Place near AB36 R338 CMOSREF generation circuit D R314 330 R373 R199 R15 R14 R13 R6 R5 R7 R8 V3SB V3SB D R9 BC1 75 1% CMOSREF 1K 1.8k 150 150 330 39 39 150 330 VTT R2 R1 R3 R4 R339 BC228 680 0.1UF GTLREFA ITP_VTT 150 150 1K 1K 150 1% 0.1uF J2 CMOSREF 2 1 2 1 R315 0 ITP_DBRESET 4 3 25 DBRESET# 4 3 AB36 AD36 Z36 E33 F18 K4 R6 V6 AD6 AK12 AK22 6 5 U3B 6 5 8 7 AN35 AH14 8 7 TDI BNR# BNR# 7 10 9 AN37 AN17 BPRI# 7 10 9 TDO V1_5 V2_5 BPRI# 12 11 AN33 AN25 12 11 TRST# VREF0 VREF1 VREF2 VREF3 VREF4 VREF5 VREF6 VREF7 TRDY# HTRDY# 7 14 13 R316 0 AL33 AN19 14 13 TCK V_CMOS DEFER# DEFER# 7 16 15 R317 0 AK32 AK20 16 15 TMS LOCK# HLOCK# 7 18 17 AN27 18 17 DRDY# DRDY# 7 20 19 J37 AL23 20 19 PREQ# HITM# HITM# 7 22 21 R318 243,1% A35 AL25 22 21 PRDY# HIT# HIT# 7 24 23 AL27 24 23 DBSY# DBSY# 7 26 25 VTT G33 AN31 26 25 BP2# ADS# HADS# 7 28 27 E37 AE37 FLUSH# 28 27 BP3# FLUSH# 30 29 R374 C35 6 ITPCLK 30 29 BPM0# E35 AJ33 C BPM1# BSEL0# BSEL#0 29,32 C AJ31 370 - Pin Socket BSEL1# BSEL#1 29,32 XHEADER_15X2 14 N33 AK30 RSRVD6 RSRVD12/JBSEL1# N35 RSRVD7 NCHCTRLP N37 AN29 RSRVD8 BR0# BR0# 5 Q33 AL31 33 N6395403 RSRVD9 Part2 THRMDP VTIN2 21,25 Q35 AL29 RSRVD10 THRMDN THRMDN 21,25 Q37 AH28 5 ITPRDY# RSRVD11 THERMTRIP# THERMTRIP# 33 AM2 AE33 RSRVD13 A20M# A20M# 12 ITP_CPURESET F10 AG35 RSRVD15 STPCLK# STPCLK# 12 VTT VTT W35 AH30 Tualatin THERMTRIP workaround circuit is on p RSRVD16 SLP# CPUSLP# 12 Y1 AJ35 RSRVD17 SMI# SMI# 12 R2 M36 RSRVD18 LINT0/INTR INTR 12 R319 R33 G37 L37 RSRVD19 LINT1/NMI NMI 12 L33 AG33 VCC5 RSRVD20 INIT# INIT# 12,17 AL1 AC35 RSRVD21 FERR# FERR# 12 R340 AG37 IGNNE# IGNNE# 12 243,1% 90.9,1% X2 AE35 R341 1k RESVD21(BR1#) IERR# VCCVID 2.2k R342 1k DYN_OE AN3 W33 PLL1 33uF (C size) L2 DYN_OE PLL1 26 VTTPWRGD AK4 U33 PLL2 VTTPWRGD PLL2 + TUAL5 6,7,26 J35 C6 VCC5 12 APICD0 PICD0 L35 AC37 4.7UH/SMD-0805 Q25 12 APICD1 PICD1 RSP# J33 AL11 2N7002 B 6 APICCLK_CPU PICCLK AP0# B W37 AN13 VTT R343 6 CPUHCLK BCLK AP1# Y33 AN23 2.2k CLKREF RP# AK26 R344 12,33 CPU_PWGD PWRGOOD AH4 B36 7,33 CPURST# RESET# BINIT# TUAL5# RESET2# X4 AK24 Debug only! RESET2# AERR# R345 1k AJ3 V4 R375 0 1k Q26 RSVD - NC BERR# AG1_VTT/NC AG1 AF36 TUALDET 2N3904 EDGCTRL/VRSEL TUALDET R406 VTT VCC2_5 E27 SLEWCNTR SLEWCNTR C37 S35 RTTCNTR 1k CPUPRES# RTTCNTR E21 PR4 VCOREDET Rds_on approx. 100 Socket 370_9 Stuff resistor mOhm @5Vgs 150,1% R275 Do Not stuff C Debug only! Do NOT place only on non-UMB Place Site w/in 0.5" PR1 PR5 JP6 jumper before removing platforms. Q27 of clock pin (W37) Debug sites only. GTLREF Generation Circuit R375 FDN335N PR6 MC7 BC7 C3 22 FB30BEAD VTT Use 0603 Packages and distribute 56,%1 110,%1 JUMPER 4.7UF 0.1UF X18PF 1 2 GTLREF Inputs ( 1 cap for every 2 inputs ) 6,7,26 TUAL5 150,1% C12 within 500 mils of processor C163 R346 10PF PR7 0.1uF 1k GTLREFA 32 Document: Intel(R) 815E Chipset Universal Socket 370 CRB A 75,1% A GTLREFA GTLREF 7,32 Page Name: 370-pin Socket Part 2 R330 X0 PR8 Do not stuff R330 Last Revised: Page: Monday, April 30, 2001 BC18 BC17 BC16 BC12 GTLREFA to CPU. Doc: Monday, April 30, 2001 GTLREF to GMCH. Revision: 150,1% 0.1UF 0.1UF 0.1UF 0.1UF Platform Applications Engineering 1.05 1900 Prairie City Road Page No: Folsom, CA 95630 4 of 33 5 4 3 2 1 5 4 3 2 1

D D

VTT R23 56 BR0# 4 R12 150 ITPRDY# 4

C C

VTT

MC23 MC22 BC34 BC35 BC36 BC37 BC38 BC24 BC23 BC5 BC14 BC22 BC9 BC15 BC2 BC13 BC3

4.7UF 4.7UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF

VTT Do not populate in assembly - debug sites only. Debug cap sites - place near processor

C164 B 820uF B

VTT Decoupling

A Document: Intel(R) 815E Chipset Universal Socket 370 CRB A Page Name: VTT Decoupling Last Revised: Page: Monday, April 30, 2001 Doc: Monday, April 30, 2001 Revision: Platform Applications Engineering 1.05 1900 Prairie City Road Page No: Folsom, CA 95630 5 of 33 5 4 3 2 1 A B C D E

PFB4 PFB2 VCC_CLOCK 1 2 AV3 USBV3 1 2 VCC_CLOCK BEAD BC56 BC55 BC32 BC31 MC18 BEAD

0.1UF 0.01UF R249 8.2K 0.01UF 0.1UF 4.7UF

PFB5 PFB1 VCC_CLOCK 1 2 PCIV3 MEMV3 1 2 VCC_CLOCK 4 BEAD MC28 MC29 BC62 BC61 BC57 BC58 BC59 BC60 BC226 BC227 BC28 BC27 BC29 BC30 BC33 BC21 BC63 BC64 MC20 MC19 BEAD 4

4.7UF 4.7UF 0.01UF 0.1UF 0.01UF 0.1UF 0.01UF 0.1UF 0.01UF 0.1UF 0.01UF 0.1UF 0.01UF 0.1UF 0.01UF 0.1UF 0.01UF 0.1UF 4.7UF 4.7UF R347

0 PFB11 APICCLK_CPU 4 L_VCC2_5 VCC2_5 1 2 R348 TUAL5 4,7,26 BEAD MC21 BC25 BC26 Q28 130 4.7UF 0.1UF 0.01UF C35 U6 2 56 5 9 14 20 25 31 35 40 44 49 18PF 2N7002 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDL VDDL

Y3 VDDA R320 33 ITPCLK 4 6 54 R46 33 X1 CPUCLK_0 CPUHCLK 4 29 FMOD1 14.318MHZ 53 R45 33 CPUCLK_1 GMCHHCLK 7 C33 7 1 R57 33 X2 IOAPIC R60 10 18PF 4 R58 33 REF0 APICCLK_ICH 12 13 ICH_CLK14 51 8 7 MEMCLK0 SDRAM0 13 ICH_3V66 R64 33 10 50 6 5 MEMCLK1 3V66-0 SDRAM1 8 GMCH_3V66 R65 33 11 47 4 3 MEMCLK2 3V66-1 SDRAM2 11 AGPCLK_CONN R66 33 12 46 2 1 MEMCLK3 3V66-2 SDRAM3 RN19 22/8P4R 12 PCLK_0/ICH R67 33 15 45 8 7 MEMCLK4 3 PCICLK0 SDRAM4 3 R290 33 16 42 6 5 MEMCLK5 PCICLK1 SDRAM5 41 4 3 MEMCLK6 SDRAM6 29 FMOD0 18 38 2 1 MEMCLK7 FS0 SDRAM7 28 RN20 22/8P4R FS1 37 R50 22 MEMCLK8 SDRAM8 13,21,28 SLP_S3# R72 10 21 36 R51 22 MEMCLK9 PD# SDRAM9 32 R_SMBCLK 22 33 R62 22 MEMCLK10 SCLK SDRAM10 32 R_SMBDATA 23 32 R63 22 MEMCLK11 SDATA SDRAM11 R44 22 29 DCLK_WR 7 C29 C39 C40 C41 C42 SDRAM12

X10PF X10PF X10PF X10PF X10PF 26 R48 33 48MHZ_0 USBCLK 13 27 R49 33 48MHZ_1 DOTCLK 8 ICS9250-28 R47 33 SIO_CLK24 21 VCC3_3 GNDL GNDL GND GND GND GND GND GND GND GND GND GND GND MEMCLK[0..7] MEMCLK[0..7] 9

Q29 3 55 8 13 17 19 24 30 34 39 43 48 52 C19 C21 C20 C133 C25 C24 C28 C30 FDN359AN MEMCLK[8..11] 26 VTTPWRGD12 X10PF X10PF X10PF X10PF X10PF X10PF X10PF X10PF MEMCLK[8..11] 10

2 VCC_CLOCK 2

PFB12 Clock power gate VCC3_3 1 2 U29 BEAD MC66 BC221 BC222 R302 R303 4 Rds_on = 100 mOhm. VDD 4.7UF 0.1UF 0.01UF 13 RN34 VDD 10K 10K 2 7 8 CLKA1 PCLK_1 14 3 5 6 CLKA2 PCLK_2 14 9 14 3 4 FS1 CLKA3 PCLK_3 15 8 15 1 2 FS2 CLKA4 PCLK_7 21 PCLK_REF 1 6 REF CLKB1 7 33/8P4R CLKB2 MEMCLK0 MEMCLK4 MEMCLK8 10 MEMCLK1 MEMCLK5 MEMCLK9 CLKB3 R277 33 11 PCLK_8 17 MEMCLK2 MEMCLK6 MEMCLK10 CLKB4 MEMCLK3 MEMCLK7 MEMCLK11 16 R312 X33 CLKOUT 5 GND 12 GND 2 4 6 8

CN6 2 4 6 8 2 4 6 8 2 4 6 8 ICS9112B-17 C120 1 Document: Intel(R) 815E Chipset Universal Socket 370 CRB 1

2 4 6 8 CN4 2 4 6 8 CN5 X10P/8P4C C34 C31 C23 C22 Ensure that the buffer used will disable X10PF

1 3 5 7 Page Name: Clock Generator X10P/8P4C X10P/8P4C its PLL and tristate outputs when no X10PF X10PF X10PF X10PF Last Revised: Page: Monday, April 30, 2001 1 3 5 7 1 3 5 7 refclk is present; otherwise, must gate C132 1 3 5 7 Doc: Monday, April 30, 2001 power here, too. Revision: 1 3 5 7 1 3 5 7 X18PF Platform Applications Engineering 1.05 1900 Prairie City Road Page No: Folsom, CA 95630 6 of 33 A B C D E 5 4 3 2 1

VTT Debug sites only. SM_MAC#[4..7] 10 SM_MAC#[4..7] 1 2 VTT SM_MAB#[4..7] SM_MD[0..63] VCC3SBY 9 SM_MAB#[4..7] SM_MD[0..63] 9,10 FB31BEAD C168 PR42 R61 U7A HD#[0..63] SM_MAA[0..12] HD#[0..63] 3 9,10 SM_MAA[0..12] 0.1uF 63.4 1% U7B Place close AA1 HD#0 SM_MAA0 D13 D23 SM_MD0 BC188 BC190 BC191 BC189 HD#0 SMAA0 SMD0 AB2 HD#1 SM_MAA1 B16 C23 SM_MD1 to GMCH HD#1 SMAA1 SMD1 90.9,1% AF2 HD#2 SM_MAA2 F12 D22 SM_MD2 X0.1UF X0.1UF X0.1UF X0.1UF 4,32 GTLREF HD#2 SMAA2 SMD2 AD4 HD#3 SM_MAA3 RN37 A16 F21 SM_MD3 HD#3 SMAA3 SMD3 PR43 AB1 HD#4 SM_MAA4 1 2 B12 E21 SM_MD4 HD#4 SMAA4 SMD4 D BC72 BC73 U6 AB3 HD#5 SM_MAA5 3 4 A12 G20 SM_MD5 D GTLREFA HD#5 SMAA5 SMD5 AA10 AA3 HD#6 SM_MAA6 5 6 C11 F20 SM_MD6 GTLREFB HD#6 SMAA6 SMD6 150,1% 0.1UF 0.1UF AC4 HD#7 SM_MAA7 7 8 A11 D20 SM_MD7 HD#7 SMAA7 SMD7 Backside decouping , should be AC1 HD#8 SM_MAA8 D12 F19 SM_MD8 HD#8 SMAA8 SMD8 placed under chipset memory signal AA7 AF3 HD#9 SM_MAA9 C13 E19 SM_MD9 6 GMCHHCLK HCLK HD#9 SMAA9 SMD9 H3 AD1 HD#10 SM_MAA10 10/8P4R E11 D19 SM_MD10 field 16,17,21,30 PCIRST# RESET# HD#10 SMAA10 SMD10 AA5 AE3 HD#11 SM_MAA11 A13 E18 SM_MD11 4,33 CPURST# CPURST# HD#11 SMAA11 SMD11 L4 AD2 HD#12 SM_MAA12 B7 B18 SM_MD12 4 HLOCK# HLOCK# HD#12 SMAA12 SMD12 M3 AD3 HD#13 RN38 10/8P4R F18 SM_MD13 4 DEFER# DEFER# HD#13 SMD13 G1 AF1 HD#14 SM_MAB#4 1 2 B15 G18 SM_MD14 HADS# ADS# HD#14 SMAB#4 SMD14 N4 AA4 HD#15 SM_MAB#5 3 4 A15 D17 SM_MD15 4 BNR# BNR# HD#15 SMAB#5 SMD15 M5 AD6 HD#16 SM_MAB#6 5 6 C14 A3 SM_MD16 4 BPRI# BPRI# HD#16 SMAB#6 SMD16 J3 AC3 HD#17 SM_MAB#7 7 8 A14 A1 SM_MD17 4 DBSY# DBSY# HD#17 SMAB#7 SMD17 J1 AE1 HD#18 C1 SM_MD18 R407 Place 4 DRDY# DRDY# HD#18 SMD18 K1 AB6 HD#19 SM_MAC#4 1 2 B10 F2 SM_MD19 VDDQ 4 HIT# HIT# HD#19 SMAC4 SMD19 56 near GMCH L3 AF4 HD#20 SM_MAC#5 3 4 A10 G3 SM_MD20 4 HITM# HITM# HD#20 SMAC5 SMD20 K3 AE5 HD#21 SM_MAC#6 5 6 C10 D6 SM_MD21 4 HTRDY# HTRDY# HD#21 SMAC6 SMD21 AC8 HD#22 SM_MAC#7 7 8 A9 C5 SM_MD22 VTT HD#22 SMAC7 SMD22 HA#[3..31] HA#3 R4 AB5 HD#23 RN36 10/8P4R B4 SM_MD23 BC192 BC193 BC194 BC195 3 HA#[3..31] HA#3 HD#23 SMD23 HA#4 P1 AF5 HD#24 B13 D4 SM_MD24 HA#4 HD#24 9,10 SM_BS0 SBS0 SMD24 HA#5 T2 AC6 HD#25 D11 C2 SM_MD25 X0.1UF X0.1UF X0.1UF X0.1UF HA#5 HD#25 9,10 SM_BS1 SBS1 SMD25 HA#6 R3 AF6 HD#26 D3 SM_MD26 HA#6 HD#26 SMD26 HA#7 N5 AD11 HD#27 SM_CSA#0 D15 E4 SM_MD27 HA#7 HD#27 SCSA#0 SMD27 HA#8 P5 AF8 HD#28 SM_CSA#1 A17 F5 SM_MD28 C HA#8 HD#28 SCSA#1 SMD28 C HA#9 R1 AD8 HD#29 SM_CSA#2 D14 G4 SM_MD29 HA#9 HD#29 SCSA#2 SMD29 HA#10 U1 AD5 HD#30 SM_CSA#3 E14 J6 SM_MD30 HA#10 HD#30 SCSA#3 SMD30 Backside decouping , should be HA#11 P2 AB7 HD#31 SM_CSA#4 E13 K5 SM_MD31 HA#11 HD#31 SCSA#4 SMD31 placed under chipset AGP signal HA#12 T1 AF7 HD#32 SM_CSA#5 B17 A26 SM_MD32 HA#12 HD#32 SCSA#5 SMD32 HA#13 T3 AD7 HD#33 A25 SM_MD33 field HA#13 HD#33 SMD33 HA#14 P3 AB8 HD#34 SM_CSB#0 F9 B24 SM_MD34 HA#14 HD#34 SCSB#0 SMD34 HA#15 T5 AE7 HD#35 SM_CSB#1 F8 A24 SM_MD35 HA#15 HD#35 SCSB#1 SMD35 HA#16 R5 AE9 HD#36 SM_CSB#2 D10 B23 SM_MD36 HA#16 HD#36 SCSB#2 SMD36 HA#17 V5 AB9 HD#37 SM_CSB#3 D9 A23 SM_MD37 HA#17 HD#37 SCSB#3 SMD37 HA#18 Y2 AF9 HD#38 SM_CSB#4 B9 C22 SM_MD38 SM_MAA12 HA#18 HD#38 SCSB#4 SMD38 HA#19 V3 AD10 HD#39 SM_CSB#5 A8 A22 SM_MD39 HA#19 HD#39 SCSB#5 SMD39 HA#20 W1 AF12 HD#40 D21 SM_MD40 R349 HA#20 HD#40 SMD40 HA#21 U4 AB11 HD#41 C16 B21 SM_MD41 10k HA#21 HD#41 9,10 SM_RAS# SRAS# SMD41 HA#22 V2 AB10 HD#42 D18 A21 SM_MD42 HA#22 HD#42 9,10 SM_CAS# SCAS# SMD42 HA#23 W3 AD9 HD#43 E16 C20 SM_MD43 HA#23 HD#43 9,10 SM_WE# SWE# SMD43 HA#24 W4 AC10 HD#44 B20 SM_MD44 HA#24 HD#44 SMD44 HA#25 U5 AF10 HD#45 SM_CKE0 D8 A20 SM_MD45 Q30 HA#25 HD#45 SCKE0 SMD45 HA#26 Y5 AD14 HD#46 SM_CKE1 E8 C19 SM_MD46 2N7002 HA#26 HD#46 SCKE1 SMD46 4,6,26 TUAL5 HA#27 Y3 AD12 HD#47 SM_CKE2 E9 A19 SM_MD47 HA#27 HD#47 SCKE2 SMD47 HA#28 U3 AB12 HD#48 SM_CKE3 D7 A4 SM_MD48 HA#28 HD#48 SCKE3 SMD48 HA#29 Y1 AE11 HD#49 SM_CKE4 C8 A2 SM_MD49 SM_WE# R90 8.2K HA#29 HD#49 SCKE4 SMD49 R_BSEL#0 29 HA#30 W5 AE15 HD#50 SM_CKE5 C7 B1 SM_MD50 HA#30 HD#50 SCKE5 SMD50 HA#31 V1 AF11 HD#51 E1 SM_MD51 SM_CAS# R89 8.2K HA#31 HD#51 SMD51 R_REFCLK 29 AF13 HD#52 F7 G2 SM_MD52 B HD#52 6 DCLK_WR SCLK SMD52 B HREQ#0 M1 AB14 HD#53 G10 E6 SM_MD53 SM_MAA9 R88 10K 3 HREQ#0 HREQ#0 HD#53 RESVD SMD53 HREQ#1 N1 AF14 HD#54 SM_DQM[0..7] D5 SM_MD54 3 HREQ#1 HREQ#1 HD#54 9,10 SM_DQM[0..7] SMD54 HREQ#2 M2 AB13 HD#55 SM_DQM0 D16 C4 SM_MD55 R68 X10K SM_MAA10 3 HREQ#2 HREQ#2 HD#55 SDQM0 SMD55 HREQ#3 L5 AB15 HD#56 SM_DQM1 F15 B3 SM_MD56 3 HREQ#3 HREQ#3 HD#56 SDQM1 SMD56 HREQ#4 N3 AE13 HD#57 SM_DQM2 A7 D2 SM_MD57 3 HREQ#4 HREQ#4 HD#57 SDQM2 SMD57 AC14 HD#58 SM_DQM3 A6 E3 SM_MD58 R77 X10K SM_RAS# HD#58 SDQM3 SMD58 RS#0 K2 AD13 HD#59 SM_DQM4 A18 F4 SM_MD59 3 RS#0 RS#0 HD#59 SDQM4 SMD59 RS#1 L1 AD15 HD#60 SM_DQM5 C17 F6 SM_MD60 3 RS#1 RS#1 HD#60 SDQM5 SMD60 RS#2 H1 AF16 HD#61 SM_DQM6 B6 G5 SM_MD61 3 RS#2 RS#2 HD#61 SDQM6 SMD61 AF15 HD#62 SM_DQM7 A5 H4 SM_MD62 HD#62 SDQM7 SMD62 SM_WE# Host Freq : HI=100 LO=66 AC12 HD#63 J4 SM_MD63 HD#63 SMD63 SM_MAA9 FSB P-MOS Kicker : HI=NON-Cu LO=Cu VCC3SBY PR9 40.2,1% G7 SM_CAS# Host Freq : HI=133 LO=100/66 Do Not Stuff C SRCOMP SBA7 LM FREQ : HI=133 LO=100 Place Site w/in C38 82815 GMCH SM_BS0 0.5" of clock X18PF Host Interface C36 SM_BS1 SM/LM muxing strap , active low ball(v6) SYSTEM MEMORY SM_MAA10 ALLZ : LO=ALLZ HI=Normal 22PF SM_MAA11 IOQ depth : HI=4 LO=1 SM_MAA12 LO = Future 0.13u Socket 370 processors HI = Pentium(R) III Processor or Intel(R) Celeron(tm) Processor w/CPUID = 068Xh SM_RAS# XOR chain : LO=XOR HI=Normal SM_CKE[0..3] 9 SM_CKE[0..3] Document: Intel(R) 815E Chipset Universal Socket 370 CRB A SM_CKE[4..5] A 10 SM_CKE[4..5] Page Name: GMCH Part 1 SM_CSA#[0..3] 9 SM_CSA#[0..3] Last Revised: Page: Monday, April 30, 2001 SM_CSA#[4..5] Doc: Monday, April 30, 2001 10 SM_CSA#[4..5] Revision: SM_CSB#[0..3] 9 SM_CSB#[0..3] Platform Applications Engineering 1.05 SM_CSB#[4..5] 10 SM_CSB#[4..5] 1900 Prairie City Road Page No: Folsom, CA 95630 7 of 33 5 4 3 2 1 5 4 3 2 1

SBA[0..7] SBA[0..7] 11 HL[0..10] HL[0..10] 12 VDDQ VCC3SBY VCC1_8 FTD[0..11] FTD[0..11] 16 GAD[0..31] 11 GAD[0..31] U7C U7D U7E D GAD0 K26 AD16 FTD0 W6 AB4 P11 N2 D GAD0/LDQM0 LTVDATA0 VCC_1.8 GND GND GND GAD1 J22 AF17 FTD1 Y9 E7 P12 N6 GAD1/LMD4 LTVDATA1 VCC_1.8 GND GND GND GAD2 K25 AE17 FTD2 VCC1_8 Y18 AC2 P13 N11 GAD2/LMD7 LTVDATA2 VCC_1.8 GND GND GND GAD3 J21 AD17 FTD3 AA6 AC5 P14 N12 GAD3/LMD3 LTVDATA3 VCC_1.8 GND GND GND GAD4 L24 AF18 FTD4 L6 22nH AA8 AC7 P15 N13 GAD4/LMD6 LTVDATA4 VCC_1.8 GND GND GND GAD5 J20 AD18 FTD5 AA11 AC9 P16 N14 GAD5/LMD2 LTVDATA5 VCC_1.8 GND GND GND GAD6 L26 AF20 FTD6 AA13 AC11 R2 N15 GAD6/LMD5 LTVDATA6 VCC_1.8 GND GND GND GAD7 K23 AD20 FTD7 C169 C170 C171 AA15 AC13 R6 N16 GAD7/LMD1 LTVDATA7 VCC_1.8 GND GND GND GAD8 K22 AC20 FTD8 AA17 AC15 R11 N23 GAD8/LMD0 LTVDATA8 VCC_1.8 GND GND GND GAD9 M25 AF21 FTD9 33uF 0.1uF 0.01uF AA19 AC17 R12 AA23 GAD9/LMA4 LTVDATA9 VCC_1.8 GND GND GND GAD10 M24 AE21 FTD10 AB16 AC19 R13 F16 GAD10/LDQM1 LTVDATA10 VCC_1.8 GND GND GND GAD11 M26 AD21 FTD11 AB20 AC21 R14 F25 GAD11/LMA2 LTVDATA11 VCC_1.8 GND GND GND GAD12 M21 AB19 AC22 AC25 R15 G9 GAD12/LMD8 BLANK# FTBLNK# 16 VCC_1.8 GND GND GND GAD13 N24 AC18 AD19 AE2 R16 G17 GAD13/LMA5 TVCLKIN/SL_STALL SL_STALL 16 VCC_1.8 GND GND GND GAD14 N22 AE19 C25 AE4 R23 G21 GAD14/LMD9 CLKOUT0 FTCLK0 16 VCC_1.8 GND GND GND GAD15 N26 AF19 E24 AE6 R25 G23 GAD15/LMA1 CLKOUT1 FTCLK1 16 VCC_1.8 GND GND GND GAD16 T26 AC16 F23 AE8 T4 P24 GAD/16/LMA8 TVVSYNC FTVSYNC 16 VCC_1.8 GND GND GND GAD17 T22 AB17 G22 AE10 T11 H6 GAD17/LMD14 TVHSYNC FTHSYNC 16 VCC_1.8 GND GND GND GAD18 U24 J7 AE12 T12 H22 GAD18/LMA11 VCC_1.8 GND GND GND GAD19 T23 AB21 K6 AE14 T13 J2 GAD19/LMD15 LTVCK 3VFTSCL 16 VCC_1.8 GND GND GND GAD20 U26 AA20 M6 AE16 T14 J5 GAD20/LMA9 LTVDA 3VFTSDA 16 VCC_1.8 GND GND GND GAD21 T24 P6 AE18 T15 J23 GAD21/LMD16 VCC_1.8 GND GND GND GAD22 V24 T6 AE20 T16 J25 GAD22/LCS# VCC_1.8 GND GND GND GAD23 U21 V7 B26 L15 K4 C GAD23/LMD17 VCC_1.8 GND GND GND C GAD24 V25 AA18 G26 C3 L16 K7 GAD24/LCKE DDDA 3VDDCDA 16 VCC_1.8 GND GND GND GAD25 V21 AB18 C6 L22 K21 GAD25/LMD18 DDCK 3VDDCCL 16 GND GND GND GAD26 V26 AA21 C9 M4 L2 GAD26/LCAS# VCC1_8 GND GND GND GAD27 W21 AE24 R251 22 Y7 C12 M11 L6 GAD27/LMD19 DCLKREF DOTCLK 6 VCC1_8 GND GND GND GAD28 W24 Y20 C58 E23 C15 M12 L11 GAD28/LTCLK1 IWASTE VCC1_8 GND GND GND GAD29 W22 AD23 AF26 C18 M13 L12 GAD29/LMD20 IREF VCC1_8 GND GND GND GAD30 W26 10PF AF25 C21 M14 L13 GAD30/LTCLK0 VCC1_8 GND GND GND GAD31 Y21 AF22 C24 M15 L14 GAD31/LMD21 VSYNC CRT_VSYNC 16 GND GND GND AF23 B2 D1 M16 AA25 HSYNC CRT_HSYNC 16 VCC3SBY GND GND GND H23 AD22 Do Not Stuff C B5 E5 L25 P4 11 GCBE#0 GCBE#0/LMA3 RED VID_RED 16 VCC3SBY GND GND GND N21 AE22 Place Site w/in 0.5" B8 E10 11 GCBE#1 GCBE#1/LMD10 GREEN VID_GREEN 16 VCC3SBY GND T25 AE23 of clock ball(AA21) B11 E12 11 GCBE#2 GCBE#2/LMD13 BLUE VID_BLUE 16 VCC3SBY GND Solano Y26 B14 E15 11 GCBE#3 GCBE#3/LRDS# VCC3SBY GND F22 B19 E17 HCLK GMCH_3V66 6 VCC3SBY GND R26 H24 HL0 B22 E20 11 GFRAME# GFRAME#/LMA10 HL0 VCC3SBY GND P26 H26 HL1 VCC1_8 B25 E22 11 GDEVSEL# GDEVSEL#/LMD11 HL1 VCC3SBY GND P23 H25 HL2 E2 F1 11 GIRDY# GIRDY#/LMD12 HL2 VCC3SBY GND P21 G24 HL3 F10 F3 11 GTRDY# GTRDY#/LMA7 HL3 VCC3SBY GND P25 F24 HL4 PR18 Place R as F14 F11 11 GSTOP# GSTOP#/LMA0 HL4 VCC3SBY GND R24 E26 HL5 F17 F13 11 GPAR GPAR/LMA6 HL5 Close as VCC3SBY GND AE26 E25 HL6 G6 T21 VDDQ 11 GREQ# GREQ#/LMD27 HL6 possible to VCC3SBY GND AD25 D26 HL7 G8 U2 C69 11 GGNT# GGNT# HL7 GMCH VCC3SBY GND AC26 D25 HL8 40.2,1% G19 U7 11 PIPE# PIPE#/LMD24 HL8 VCC3SBY GND D24 HL9 H2 K24 B HL9 VCC3SBY GND B M22 C26 HL10 H5 V4 560PF 11 ADSTB0 ADSTB0 HL10 VCC3SBY GND L23 H21 HUBREF_GMCH H7 V6 PR21 PR23 11 ADSTB0# ADSTB0# HUBREF VCC3SBY GND U22 G25 V20 11 ADSTB1 ADSTB1 HLSTB HLSTB 12 GND V23 F26 K20 V22 82,1% 1K,1% 11 ADSTB1# ADSTB1# HLSTB# HLSTB# 12 VDDQ GND Y23 H20 HCOMP Y24 W2 11 SBSTB SBSTB HCOMP VDDQ GND AA24 VCC1_8 L21 W7 11 SBSTB# SBSTB# VDDQ GND GMCH_AGPREF 11 AB22 M23 W23 SBA0/LMD31 SBA0 11 VDDQ GND AD24 AB25 U25 W25 11 ST0 ST0/LMD28 SBA1/LMD25 SBA1 11 VDDQ GND AC24 AB23 N25 Y4 PR24 PR22 11 ST1 ST1/LDQM3 SBA2/LDQM2 SBA2 11 VDDQ GND AC23 AB26 R21 Y6 11 ST2 ST2/LMD29 SBA3/LMD26 SBA3 11 VDDQ GND AA22 PR16 U20 Y8 82,1% 1K,1% SBA4/LMD23 SBA4 11 VDDQ GND AD26 AA26 U23 Y10 C72 11 RBF# RBF#/LMD30 SBA5/LWE# SBA5 11 VDDQ GND AB24 Y22 301,1% W20 Y17 11 WBF# WBF# SBA6/LMD22 SBA6 11 VDDQ GND J24 Y25 Y19 11,32 CONN_AGPREF AGPREF SBA7/LGM_FREQ_SEL SBA7 11 GND GRCOMP J26 AA2 560PF GRCOMP GND PR14 15.1% OCLK R22 AF24 AA9 OCLOCK GND GND RCLK P22 AE25 AA12 RCLOCK GND GND PR15 PR13 BC90 PR17 AA14 GND BC89 C61 82815 GMCH AA16 40.2,1% 174,1% 0.1UF 301,1% GND 0.1UF 15PF/5%,MPO 82815 GMCH Display Cache, Video, and Power and Ground A HUB Interface Document: Intel(R) 815E Chipset Universal Socket 370 CRB A NOTE : OCLK = 0.5" Place as close as Place as close as Page Name: GMCH Part 2 RCLK = 1.5" Possible to GMCH Possible to GMCH and via straight and via straight Last Revised: Page: Monday, April 30, 2001 Doc: Monday, April 30, 2001 to VSS plane to VSS plane Revision: Platform Applications Engineering 1.05 1900 Prairie City Road Page No: Folsom, CA 95630 8 of 33 5 4 3 2 1 A B C D E

VCC3SBY VCC3SBY VCC3SBY VCC3SBY

DIMM1 DIMM2 1 85 1 85 VSS VSS VSS VSS SM_MD0 2 86 SM_MD32 SM_MD0 2 86 SM_MD32 SM_MAA[0..12] DQ0 DQ32 DQ0 DQ32 SM_MAA[0..12] 7,10 SM_MD1 3 87 SM_MD33 SM_MD1 3 87 SM_MD33 DQ1 DQ33 DQ1 DQ33 SM_MD2 4 88 SM_MD34 SM_MD2 4 88 SM_MD34 SM_MD[0..63] DQ2 DQ34 DQ2 DQ34 SM_MD[0..63] 7,10 SM_MD3 5 89 SM_MD35 SM_MD3 5 89 SM_MD35 DQ3 DQ35 DQ3 DQ35 6 90 6 90 SM_MAB#[4..7] VDD VDD VDD VDD SM_MAB#[4..7] 7 SM_MD4 7 91 SM_MD36 SM_MD4 7 91 SM_MD36 DQ4 DQ36 DQ4 DQ36 SM_MD5 8 92 SM_MD37 SM_MD5 8 92 SM_MD37 SM_DQM[0..7] DQ5 DQ37 DQ5 DQ37 SM_DQM[0..7] 7,10 4 SM_MD6 9 93 SM_MD38 SM_MD6 9 93 SM_MD38 4 DQ6 DQ38 DQ6 DQ38 SM_MD7 10 94 SM_MD39 SM_MD7 10 94 SM_MD39 MEMCLK[0..7] DQ7 DQ39 DQ7 DQ39 MEMCLK[0..7] 6 SM_MD8 11 95 SM_MD40 SM_MD8 11 95 SM_MD40 DQ8 DQ40 DQ8 DQ40 12 96 12 96 SM_CKE[0..3] VSS VSS VSS VSS SM_CKE[0..3] 7 SM_MD9 13 97 SM_MD41 SM_MD9 13 97 SM_MD41 DQ9 DQ41 DQ9 DQ41 SM_MD10 14 98 SM_MD42 SM_MD10 14 98 SM_MD42 SM_CSA#[0..3] DQ10 DQ42 DQ10 DQ42 SM_CSA#[0..3] 7 SM_MD11 15 99 SM_MD43 SM_MD11 15 99 SM_MD43 DQ11 DQ43 DQ11 DQ43 SM_MD12 16 100 SM_MD44 SM_MD12 16 100 SM_MD44 SM_CSB#[0..3] DQ12 DQ44 DQ12 DQ44 SM_CSB#[0..3] 7 SM_MD13 17 101 SM_MD45 SM_MD13 17 101 SM_MD45 DQ13 DQ45 DQ13 DQ45 18 102 18 102 SM_WE# VDD VDD VDD VDD SM_WE# 7,10 SM_MD14 19 103 SM_MD46 SM_MD14 19 103 SM_MD46 DQ14 DQ46 DQ14 DQ46 SM_MD15 20 104 SM_MD47 SM_MD15 20 104 SM_MD47 SM_RAS# DQ15 DQ47 DQ15 DQ47 SM_RAS# 7,10 21 105 21 105 CB0 CB4 CB0 CB4 22 106 22 106 SM_CAS# CB1 CB5 CB1 CB5 SM_CAS# 7,10 23 107 23 107 VSS VSS VSS VSS 24 108 24 108 SM_BS0 CB8 CB12 CB8 CB12 SM_BS0 7,10 25 109 25 109 CB9 CB13 CB9 CB13 26 110 26 110 SM_BS1 VDD VDD VDD VDD SM_BS1 7,10 SM_WE# 27 111 SM_CAS# SM_WE# 27 111 SM_CAS# WE#/WE0# CAS#/DU WE#/WE0# CAS#/DU SM_DQM0 28 112 SM_DQM4 SM_DQM0 28 112 SM_DQM4 DQM0 DQM4 DQM0 DQM4 SM_DQM1 29 113 SM_DQM5 SM_DQM1 29 113 SM_DQM5 DQM1 DQM5 DQM1 DQM5 SM_CSA#0 30 114 SM_CSA#1 SM_CSA#2 30 114 SM_CSA#3 SMBDATA CS0# CS1# CS0# CS1# SMBDATA 10,13,21,24,30,32 31 115 SM_RAS# 31 115 SM_RAS# SMBCLK DU/OE0# RAS#/DU DU/OE0# RAS#/DU SMBCLK 10,13,21,24,30,32 32 116 32 116 3 VSS VSS VSS VSS 3 SM_MAA0 33 117 SM_MAA1 SM_MAA0 33 117 SM_MAA1 A0 A1 A0 A1 SM_MAA2 34 118 SM_MAA3 SM_MAA2 34 118 SM_MAA3 A2 A3 A2 A3 SM_MAA4 35 119 SM_MAA5 SM_MAB#4 35 119 SM_MAB#5 A4 A5 A4 A5 SM_MAA6 36 120 SM_MAA7 SM_MAB#6 36 120 SM_MAB#7 A6 A7 A6 A7 SM_MAA8 37 121 SM_MAA9 SM_MAA8 37 121 SM_MAA9 A8 A9 A8 A9 SM_MAA10 38 122 SM_BS0 SM_MAA10 38 122 SM_BS0 A10/AP BA0/A11 A10/AP BA0/A11 SM_BS1 39 123 SM_MAA11 SM_BS1 39 123 SM_MAA11 BA1/A12 A11/A13 BA1/A12 A11/A13 40 124 40 124 VDD VDD VDD VDD 41 125 MEMCLK1 41 125 MEMCLK5 VDD CLK1/DU VDD CLK1/DU MEMCLK0 42 126 SM_MAA12 MEMCLK4 42 126 SM_MAA12 CLK0/DU A12/DU CLK0/DU A12/DU 43 127 43 127 VSS VSS VSS VSS 44 128 SM_CKE0 44 128 SM_CKE2 DU/OE2# CKE0/DU DU/OE2# CKE0/DU SM_CSB#0 45 129 SM_CSB#1 SM_CSB#2 45 129 SM_CSB#3 CS2# CS3# CS2# CS3# SM_DQM2 46 130 SM_DQM6 SM_DQM2 46 130 SM_DQM6 DQM2 DQM6 DQM2 DQM6 SM_DQM3 47 131 SM_DQM7 SM_DQM3 47 131 SM_DQM7 DQM3 DQM7 DQM3 DQM7 48 132 48 132 DU/WE2# A13/DU DU/WE2# A13/DU 49 133 49 133 VDD VDD VDD VDD 50 134 50 134 VCC3SBY CB10 CB14 CB10 CB14 51 135 51 135 CB11 CB15 CB11 CB15 52 136 52 136 CB2 CB6 CB2 CB6 53 137 53 137 R28 CB3 CB7 CB3 CB7 54 138 54 138 2.2K VSS VSS VSS VSS SM_MD16 55 139 SM_MD48 SM_MD16 55 139 SM_MD48 DQ16 DQ48 DQ16 DQ48 SM_MD17 56 140 SM_MD49 SM_MD17 56 140 SM_MD49 2 DQ17 DQ49 DQ17 DQ49 2 SM_MD18 57 141 SM_MD50 SM_MD18 57 141 SM_MD50 DQ18 DQ50 DQ18 DQ50 DM_SA_PU 10 SM_MD19 58 142 SM_MD51 SM_MD19 58 142 SM_MD51 DQ19 DQ51 DQ19 DQ51 59 143 59 143 VDD VDD VDD VDD SM_MD20 60 144 SM_MD52 SM_MD20 60 144 SM_MD52 DQ20 DQ52 DQ20 DQ52 61 145 61 145 NC NC NC NC 62 146 62 146 VREF/DU VREF/DU VREF/DU VREF/DU SM_CKE1 63 147 SM_CKE3 63 147 CKE1 REGE CKE1 REGE 64 148 64 148 VSS VSS VSS VSS SM_MD21 65 149 SM_MD53 SM_MD21 65 149 SM_MD53 DQ21 DQ53 DQ21 DQ53 SM_MD22 66 150 SM_MD54 SM_MD22 66 150 SM_MD54 DQ22 DQ54 DQ22 DQ54 SM_MD23 67 151 SM_MD55 SM_MD23 67 151 SM_MD55 DQ23 DQ55 DQ23 DQ55 68 152 68 152 VSS VSS VSS VSS SM_MD24 69 153 SM_MD56 SM_MD24 69 153 SM_MD56 DQ24 DQ56 DQ24 DQ56 SM_MD25 70 154 SM_MD57 SM_MD25 70 154 SM_MD57 DQ25 DQ57 DQ25 DQ57 SM_MD26 71 155 SM_MD58 SM_MD26 71 155 SM_MD58 DQ26 DQ58 DQ26 DQ58 SM_MD27 72 156 SM_MD59 SM_MD27 72 156 SM_MD59 DQ27 DQ59 DQ27 DQ59 73 157 73 157 VDD VDD VDD VDD SM_MD28 74 158 SM_MD60 SM_MD28 74 158 SM_MD60 DQ28 DQ60 DQ28 DQ60 SM_MD29 75 159 SM_MD61 SM_MD29 75 159 SM_MD61 DQ29 DQ61 DQ29 DQ61 SM_MD30 76 160 SM_MD62 SM_MD30 76 160 SM_MD62 DQ30 DQ62 DQ30 DQ62 SM_MD31 77 161 SM_MD63 SM_MD31 77 161 SM_MD63 DQ31 DQ63 DQ31 DQ63 78 162 78 162 VSS VSS VSS VSS MEMCLK2 79 163 MEMCLK3 MEMCLK6 79 163 MEMCLK7 CLK2/NC CLK3/NC CLK2/NC CLK3/NC Document: Intel(R) 815E Chipset Universal Socket 370 CRB 1 80 164 80 164 1 NC NC NC NC 81 165 81 165 WP SA0 WP SA0 Page Name: DIMMs 1 and 2 SMBDATA 82 166 SMBDATA 82 166 SDA SA1 SDA SA1 SMBCLK 83 167 SMBCLK 83 167 Last Revised: Page: Monday, April 30, 2001 SCL SA2 SCL SA2 84 168 84 168 Doc: Monday, April 30, 2001 VDD VDD VDD VDD Revision: DIMM168 DIMM168 Platform Applications Engineering 1.05 1900 Prairie City Road Page No: Folsom, CA 95630 9 of 33 A B C D E

CH6-12 A B C D E

VCC3SBY VCC3SBY

DIMM3 1 85 VSS VSS SM_MAA[0..12] SM_MD0 2 86 SM_MD32 7,9 SM_MAA[0..12] DQ0 DQ32 SM_MD1 3 87 SM_MD33 DQ1 DQ33 SM_MD[0..63] SM_MD2 4 88 SM_MD34 7,9 SM_MD[0..63] DQ2 DQ34 SM_MD3 5 89 SM_MD35 DQ3 DQ35 SM_MAC#[4..7] 6 90 7 SM_MAC#[4..7] VDD VDD SM_MD4 7 91 SM_MD36 DQ4 DQ36 SM_DQM[0..7] SM_MD5 8 92 SM_MD37 7,9 SM_DQM[0..7] DQ5 DQ37 4 SM_MD6 9 93 SM_MD38 4 DQ6 DQ38 MEMCLK[8..11] SM_MD7 10 94 SM_MD39 DQ7 DQ39 6 MEMCLK[8..11] SM_MD8 11 95 SM_MD40 DQ8 DQ40 12 96 SM_CKE[4..5] VSS VSS 7 SM_CKE[4..5] SM_MD9 13 97 SM_MD41 DQ9 DQ41 SM_MD10 14 98 SM_MD42 SM_CSA#[4..5] DQ10 DQ42 7 SM_CSA#[4..5] SM_MD11 15 99 SM_MD43 DQ11 DQ43 SM_MD12 16 100 SM_MD44 DQ12 DQ44 SM_CSB#[4..5] SM_MD13 17 101 SM_MD45 7 SM_CSB#[4..5] DQ13 DQ45 18 102 VDD VDD SM_WE# SM_MD14 19 103 SM_MD46 DQ14 DQ46 7,9 SM_WE# SM_MD15 20 104 SM_MD47 DQ15 DQ47 SM_RAS# 21 105 CB0 CB4 7,9 SM_RAS# 22 106 CB1 CB5 SM_CAS# 23 107 7,9 SM_CAS# VSS VSS 24 108 CB8 CB12 SM_BS0 25 109 7,9 SM_BS0 CB9 CB13 26 110 VDD VDD SM_BS1 SM_WE# 27 111 SM_CAS# 7,9 SM_BS1 WE#/WE0# CAS#/DU SM_DQM0 28 112 SM_DQM4 DQM0 DQM4 SM_DQM1 29 113 SM_DQM5 DQM1 DQM5 SMBDATA SM_CSA#4 30 114 SM_CSA#5 9,13,21,24,30,32 SMBDATA CS0# CS1# SMBCLK 31 115 SM_RAS# 9,13,21,24,30,32 SMBCLK DU/OE0# RAS#/DU 32 116 3 VSS VSS 3 SM_MAA0 33 117 SM_MAA1 A0 A1 SM_MAA2 34 118 SM_MAA3 A2 A3 SM_MAC#4 35 119 SM_MAC#5 A4 A5 SM_MAC#6 36 120 SM_MAC#7 A6 A7 SM_MAA8 37 121 SM_MAA9 A8 A9 SM_MAA10 38 122 SM_BS0 A10/AP BA0/A11 SM_BS1 39 123 SM_MAA11 BA1/A12 A11/A13 40 124 VDD VDD 41 125 MEMCLK9 VDD CLK1/DU MEMCLK8 42 126 SM_MAA12 CLK0/DU A12/DU 43 127 VSS VSS 44 128 SM_CKE4 DU/OE2# CKE0/DU SM_CSB#4 45 129 SM_CSB#5 CS2# CS3# SM_DQM2 46 130 SM_DQM6 DQM2 DQM6 SM_DQM3 47 131 SM_DQM7 DQM3 DQM7 48 132 DU/WE2# A13/DU 49 133 VDD VDD 50 134 CB10 CB14 51 135 CB11 CB15 52 136 CB2 CB6 53 137 CB3 CB7 54 138 VSS VSS SM_MD16 55 139 SM_MD48 DQ16 DQ48 SM_MD17 56 140 SM_MD49 2 DQ17 DQ49 2 SM_MD18 57 141 SM_MD50 DQ18 DQ50 SM_MD19 58 142 SM_MD51 DQ19 DQ51 59 143 VDD VDD SM_MD20 60 144 SM_MD52 DQ20 DQ52 61 145 NC NC 62 146 VREF/DU VREF/DU SM_CKE5 63 147 CKE1 REGE 64 148 VSS VSS SM_MD21 65 149 SM_MD53 DQ21 DQ53 SM_MD22 66 150 SM_MD54 DQ22 DQ54 SM_MD23 67 151 SM_MD55 DQ23 DQ55 68 152 VSS VSS SM_MD24 69 153 SM_MD56 DQ24 DQ56 SM_MD25 70 154 SM_MD57 DQ25 DQ57 SM_MD26 71 155 SM_MD58 DQ26 DQ58 SM_MD27 72 156 SM_MD59 DQ27 DQ59 73 157 VDD VDD SM_MD28 74 158 SM_MD60 DQ28 DQ60 SM_MD29 75 159 SM_MD61 DQ29 DQ61 SM_MD30 76 160 SM_MD62 DQ30 DQ62 SM_MD31 77 161 SM_MD63 DQ31 DQ63 78 162 VSS VSS MEMCLK10 79 163 MEMCLK11 CLK2/NC CLK3/NC Document: Intel(R) 815E Chipset Universal Socket 370 CRB 1 80 164 1 NC NC 9 DM_SA_PU 81 165 WP SA0 Page Name: DIMM 3 SMBDATA 82 166 SDA SA1 SMBCLK 83 167 Last Revised: Page: Monday, April 30, 2001 SCL SA2 84 168 Doc: Monday, April 30, 2001 VDD VDD Revision: DIMM168 Platform Applications Engineering 1.05 1900 Prairie City Road Page No: Folsom, CA 95630 10 of 33 A B C D E A B C D E

VCC3_3 VCC12 VCC12 VCC5 VDDQ

R106

2.2K 4 4 VDDQ AGP1 B1 A1 18 AGP_OC# OVRCNT# 12V RN49 B2 A2 5V_A TYPEDET# TYPEDET# 26 GSERR# 1 2 B3 A3 5V_B RESV_A GPAR 3 4 B4 A4 18 AGPUSBP USB+ USB- AGPUSBN 18 GPERR# 5 6 B5 A5 GND_K GND_A GDEVSEL# 7 8 B6 A6 14,15,30 PIRQ#B INTB# INTA# PIRQ#A 14,15,30 B7 A7 6 AGPCLK_CONN CLK RST# PCI_RST# 14,15,30 8.2K/8P4R GREQ# B8 A8 GGNT# REQ#/DQ27 GNT# GGNT# 8 RN48 8 GREQ# B9 A9 VCC3.3_F VCC3.3_A GFRAME# 1 2 ST0 B10 A10 ST1 8 ST0 ST0/DQ28 DQM3/ST1 ST1 8 GIRDY# 3 4 ST2 B11 A11 8 ST2 ST2/DQ29 RESV_B GTRDY# 5 6 RBF# B12 A12 PIPE# RBF#/DQ30 DQ24/PIPE# PIPE# 8 GSTOP# 7 8 8 RBF# B13 A13 GND_L GND_B B14 A14 WBF# RESV_H WBF# WBF# 8 8.2K/8P4R SBA0 B15 A15 SBA1 SBA0/DQ31 DQ25/SBA1 RN42 B16 A16 VCC3.3_G VCC3.3_B GREQ# 1 2 SBA2 B17 A17 SBA3 SBA2/DQM2 DQ26/SBA3 GGNT# 3 4 SBSTB B18 A18 SBSTB1# SB_STB SB_STB# SBSTB# 8 ST0 5 6 8 SBSTB B19 A19 GND_M GND_C ST1 7 8 SBA4 B20 A20 SBA5 SBA4/DQ23 WE#/SBA5 SBA6 B21 A21 SBA7 SBA6/DQ22 M_FREQ_SEL/SBA7 8.2K/8P4R V3SB B22 A22 3 RESV RESV_C 3 RN43 B23 A23 GND_N GND_D ST2 1 2 B24 A24 3.3VAUX1 RESV_D RBF# 3 4 B25 A25 VCC3.3_H VCC3.3_C PIPE# 5 6 GAD31 B26 A26 GAD30 AD31/DQ21 TCLK0/AD30 WBF# 7 8 GAD29 B27 A27 GAD28 AD29/DQ20 TCLK1/AD28 B28 A28 VCC3.3_I VCC3.3_D 8.2K/8P4R GAD27 B29 A29 GAD26 AD27/DQ19 CAS#/AD26 RN44 GAD25 B30 A30 GAD24 AD25/DQ18 AD24 SBA0 1 2 B31 A31 GND_O GND_E SBA1 3 4 ADSTB1 B32 A32 ADSTB1# 8 ADSTB1 AD_STB1 AD_STB1# ADSTB1# 8 SBA2 5 6 GAD23 B33 A33 AD23/DQ17 RAS#/C/BE3# GCBE#3 8 SBA3 7 8 B34 A34 VDDQ_F VDDQ_A GAD21 B35 A35 GAD22 AD21/DQ16 A0/AD22 8.2K/8P4R GAD19 B36 A36 GAD20 AD19/DQ15 A9/AD20 RN46 B37 A37 GND_P GND_F SBA7 1 2 GAD17 B38 A38 GAD18 AD17/DQ14 A11/AD18 SBA6 3 4 B39 A39 GAD16 8 GCBE#2 C/BE2#/DQ13 A8/AD16 5 6 B40 A40 VDDQ_G VDDQ_B 7 8 GIRDY# B41 A41 GFRAME# IRDY#/DQ12 A10/FRAME# GFRAME# 8 8 GIRDY# B42 A42 3.3VAUX2 RESV_E 8.2K/8P4R B43 A43 GND_Q GND_G B44 A44 RESV_K RESV_F ADSTB0 8.2K R332 B45 A45 VCC3.3_J VCC3.3_E ADSTB0# 8.2K R333 GDEVSEL# B46 A46 GTRDY# VDDQ 2 8 GDEVSEL# DEVSEL#/DQ11 A7/TRDY# GTRDY# 8 2 ADSTB1 8.2K R334 B47 A47 GSTOP# VDDQ_H CS#/STOP# GSTOP# 8 ADSTB1# 8.2K R335 GPERR# B48 A48 PERR# PME# PCI_PME# 12,14,15,22 B49 A49 GND_R GND_H GSERR# B50 A50 GPAR SERR# A6/PAR GPAR 8 RN45 B51 A51 GAD15 C/BE1#/DQ10 A1/AD15 SBSTB# 1 2 8 GCBE#1 B52 A52 VDDQ_I VDDQ_C SBSTB 3 4 GAD14 B53 A53 GAD13 PR20 AD14/DQ9 A5/AD13 Place close SBA5 5 6 GAD12 B54 A54 GAD11 AD12/DQ8 A2/AD11 SBA4 7 8 B55 A55 to GMCH 301,1% GND_S GND_I GAD10 B56 A56 GAD9 CON_AGPREF AD10/DQM1 A4/AD9 8.2K/8P4R GAD8 B57 A57 AD8/DQ0 A3/C/BE0# GCBE#0 8 B58 A58 VDDQ_J VDDQ_D ADSTB0 B59 A59 ADSTB0# PR19 8 ADSTB0 AD_STB0 AD_STB0# ADSTB0# 8 GAD7 B60 A60 GAD6 AD7/DQ1 DQ5/AD6 B61 A61 200,1% GND_T GND_J GAD5 B62 A62 GAD4 AD5/DQ2 DQ6/AD4 GAD3 B63 A63 GAD2 AD3/DQ3 DQ7/AD2 B64 A64 Q13 VDDQ_K VDDQ_E GAD1 B65 A65 GAD0 2N7002 AD1/DQ4 DQM0/AD0 B66 A66 8 GMCH_AGPREF VREF_CG VREF_GC CONN_AGPREF 8,32 AGP4XU_20

1 Document: Intel(R) 815E Chipset Universal Socket 370 CRB 1 GAD[0..31] 8 GAD[0..31] Page Name: AGP Last Revised: Page: Monday, April 30, 2001 SBA[0..7] Doc: Monday, April 30, 2001 8 SBA[0..7] Revision: Platform Applications Engineering 1.05 1900 Prairie City Road Page No: Folsom, CA 95630 11 of 33 A B C D E

CH6-18 5 4 3 2 1

VCC3_3 VCC1_8 VCC1_8 V3SB V3SB V3SB V1_8SB V1_8SB

U12A 82801BA ICH2 AD[0..31] E14 E15 E16 E17 E18 F18 G18 H18 J18 P18 R18 R5 T5 U5 V5 V6 V7 V8 D10 E5 K19 L19 P5 V9 D2 U18 T18 F5 G5 V17 V18 V14 V15 V16 H5 J5 14,15 AD[0..31] AD0 AA4 HL[0..10] AD0 HL[0..10] 8

AD1 AB4 VCCA AD2 AD1 VCCPS1 VCCPS2 VCCPX1 VCCPX2 VCCAX1 VCCAX2 Y4 VCCCS1 VCCCS2 VCCCS3 D11 AD2 A20M# A20M# 4

D VCCUSB1 VCCUSB2 D AD3 W5 VCC3_3_2 VCC3_3_3 VCC3_3_4 VCC3_3_5 VCC3_3_6 VCC3_3_7 VCC3_3_8 VCC1_8_1 VCC1_8_2 VCC1_8_3 VCC1_8_4 VCC1_8_5 VCC1_8_6 A12 AD3 VCC3_3_10 VCC3_3_11 VCC3_3_12 VCC3_3_13 VCC3_3_14 VCC3_3_15 VCC3_3_16 VCC3_3_17 VCC3_3_18 VCC3_3_19 VCC3_3_20 CPUSLP# CPUSLP# 4 AD4 W4 R22 AD4 FERR# FERR# 4 AD5 Y5 A11 AD5 IGNNE# IGNNE# 4 AD6 AB3 C12 AD6 INIT# INIT# 4,17 AD7 AA5 C11 AD7 INTR INTR 4 AD8 AB5 B11 AD8 NMI NMI 4 AD9 Y3 B12 AD9 SMI# SMI# 4 AD10 W6 C10 AD10 STPCLK# STPCLK# 4 AD11 W3 B13 AD11 RCIN# KBRST# 21,30 AD12 Y6 C13 AD12 A20GATE A20GATE 21,30 AD13 Y2 A13 AD13 CPUPWRGOD CPU_PWGD 4,33 AD14 AA6 AD14 AD15 Y1 A4 HL0 AD15 HL0 AD16 V2 B5 HL1 AD16 HL1 AD17 AA8 A5 HL2 AD17 HL2 AD18 V1 B6 HL3 AD18 HL3 AD19 AB8 B7 HL4 AD19 HL4 AD20 U4 A8 HL5 VCC1_8 AD20 HL5 AD21 W9 B8 HL6 AD21 HL6 AD22 U3 A9 HL7 AD22 HL7 AD23 Y9 C8 HL8 AD23 HL8 AD24 U2 C6 HL9 PR27 Place R as AD24 HL9 AD25 AB9 C7 HL10 Close as AD25 HL10 AD26 U1 C5 40.2,1% C AD26 HL11 possible to C AD27 W10 A6 AD27 HLSTB HLSTB 8 ICH AD28 T4 A7 AD28 HLSTB# HLSTB# 8 AD29 Y10 A3 AD29 HCOMP AD30 T3 B4 HUBREF_ICH AD30 HUBREF HUBREF_ICH 32 AD31 AA10 AD31 P1 PIRQ#A ICH_IRQ#A 30 AA3 P2 VCC1_8 14,15 C_BE#0 C_BE#0 PIRQ#B ICH_IRQ#B 30 AB6 P3 14,15 C_BE#1 C_BE#1 PIRQ#C ICH_IRQ#C 30 Y8 N4 14,15 C_BE#2 C_BE#2 PIRQ#D ICH_IRQ#D 30 AA9 14,15 C_BE#3 C_BE#3 F21 IRQ14 IRQ14 17 W11 C16 PR25 6 PCLK_0/ICH PCICLK IRQ15 IRQ15 17 V3 N20 14,15,30 FRAME# FRAME# APICCLK APICCLK_ICH 6 C101 AB7 N19 301,1% 14,15,30 DEVSEL# DEVSEL# APICD1 APICD1 4 W8 P22 14,15,30 IRDY# IRDY# APICD0 APICD0 4 10PF V4 N21 14,15,30 TRDY# TRDY# SERIRQ SERIRQ 21,30 NPOP W1 14,15,30 STOP# STOP# AA15 R2 30 ICHRST# PCIRST# REQ#0 PREQ#0 14,30 AA7 R3 BC119 PR26 14,15,30 PLOCK# PLOCK# REQ#1 PREQ#1 14,30 W2 T1 14,15 PAR PAR REQ#2 PREQ#2 15,30 W7 AB10 0.01UF 301,1% 14,15,30 SERR# SERR# REQ#3 PREQ#3 30 Y7 P4 14,15,30 PERR# PERR# REQ#4 PREQ#4 30 Y15 L3 11,14,15,22 PCI_PME# PCI_PME# REQ#B/GPI1/REQ#5 PREQ#5 30 B B M3 M2 30 PCI_REQ#A REQ#A/GPI0 GNT#0 PGNT#0 14 L2 M1 Place as close as GNT#A/GPO16 GNT#1 PGNT#1 14 R4 Possible to ICH GNT#2 PGNT#2 15 N3 T2 30 ICH_IRQ#E PIRQ#E/GPI2 GNT#3 and via straight N2 R1 30 ICH_IRQ#F PIRQ#F/GPI3 GNT#4 to VSS plane N1 L4 30 ICH_IRQ#G PIRQ#G/GPI4 GNT#B/GPO17/GNT#5 M4 30 ICH_IRQ#H PIRQ#H/GPI5 Y11 G2 17 P66DET GPI6 LAN_RXD0 LAN_RXD0 24 AA11 G1 17 S66DET GPI7 LAN_RXD1 LAN_RXD1 24 Y14 H1 30 GPI8 GPI8 LAN_RXD2 LAN_RXD2 24 W14 RN69 22/8P4R 24 EXTSMI# GPI12 AB15 F3 U12_RN69-1 1 2 21,30 LPC_PME# GPI13 LAN_TXD0 LAN_TXD0 24 A15 F2 U12_RN69-3 3 4 GPO18 LAN_TXD1 LAN_TXD2 24 D14 F1 U12_RN69-5 5 6 GPO19 LAN_TXD2 LAN_TXD1 24 C14 U12_RN69-7 7 8 GPO20 L1 GPO21 B14 H2 GPOD22 LAN_RSTSYNC LAN_RSTSYNC 24 A14 G3 17 GPIO23 GPO23 LAN_CLK LAN_CLK 24 AB14 30 GPIO27 GPIOD27 AA14 24,29 PRI_DWN# GPIOD28

A Document: Intel(R) 815E Chipset Universal Socket 370 CRB A VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 Page Name: ICH2 Part 1

A1 A10 A2 A21 A22 AA1 AA2 AA21 AA22 AB1 AB2 AB21 AB22 B1 B10 B2 B21 B22 B3 B9 C2 C3 C4 C9 D3 D5 D6 D7 D8 D9 E6 E7 E8 E9 J10 J11 J12 J13 J14 J9 K1 K10 K11 K12 K13 K14 K9 L10 L11 L12 L13 L14 L9 M9 M10 M11 M12 M13 M14 N9 N10 N11 N12 N13 N14 P9 P10 P11 P12 P13 P14 Last Revised: Page: Monday, April 30, 2001 Doc: Monday, April 30, 2001 Revision: Platform Applications Engineering 1.05 1900 Prairie City Road Page No: Folsom, CA 95630 12 of 33 5 4 3 2 1 A B C D E

VCC3_3 V3SB VCCRTC VCC5SBY VCMOS 6 ICH_CLK14 R141 10 Q16 C96 BC197 3 2N7002 D18

3 D19 R134 1K X10P 0.1UF VCC5 SS12/SMD BAT54C R129 1K VCC5

2 1 R325 1K 4 VCC3_3 4

2 1 C104 VCC3_3 C91 BC125 D8 SS12/SMD VCC_CLOCK 1.0UF Target 20ms after U12B U21 D12 D13 V19 M20 K2 1.0UF 0.1UF W15 VCC_CLOCK is 30 GPIO25 GPIO25 V21 GPIO24 powered AA13 V5R1 V5R2 5 21,30 OVT# THRM# VCPU1 VCPU2 R376 43k U33 W16 E21 6,21,28 SLP_S3# VCCRTC PDCS#1 17 SLP_S3# V5R_SUS PDCS#1 1 AB18 C15 A 28 SLP_S5# SLP_S5# SDCS#1 SDCS#1 17

Vcc 4 ICH_PWROK R20 E19 Y PWROK PDSC#3 PDCS#3 17 C172 Y16 D15 RSM_PWROK SDCS#3 SDCS#3 17 2 JP1 W21 PDA[0..2]

B GND 21,33 PWRBTN# PWRBTN# PDA[0..2] 17 1.0uF R174 15K R174_JP1 1 AA17 F20 PDA0 22,30 ICH_RI# RI# PDA0 741G08 AND 2 R21 F19 PDA1 21 RSMRST# RSMRST# PDA1 3 C113 3 Y17 E22 PDA2 SUS_STAT# PDA2 AA18 A16 SDA0 21 SUSCLK SUSCLK SDA0 D12 1.0UF CCM0S AA16 D16 SDA1 9,10,21,24,30,32 SMBDATA SMBDATA SDA1 R187 AB16 B16 SDA2 21,25 PWROK 9,10,21,24,30,32 SMBCLK SMBCLK SDA2 AB17 SDA[0..2] 30 SMBALERT# SMBALTER#/GPI11 SDA[0..2] 17 SS12/SMD 1K T19 G22 21,25 CASEOPEN# INTRUDER# PDDREQ PDREQ 17 B18 SDDREQ SDREQ 17 R181 1K F22 PDDACK# PDDACK# 17 R377 0 M19 B17 3 CLK14 SDDACK# SDDACK# 17 3 C110 P20 G19 6 USBCLK CLK48 PDIOR# PDIOR# 17 Debug only - do D4 D17 6 ICH_3V66 CLK66 SDIOR# SDIOR# 17 0.047UF G21 not stuff PDIOW# PDIOW# 17 BAT1 VBIAS T21 C17 VBIAS SDIOW# SDIOW# 17 RTCX1 U22 G20 RTCX1 PIORDY PIORDY 17 BATTERY RTCX2 T22 A17 RTCX2 SIORDY SIORDY 17 RTCRST# T20 RTCRST# H19 PDD0 PDD0 R162 H22 PDD1 PDD1 V22 J19 PDD2 24,29 AC_RST# AC_RST# PDD2 P19 J22 PDD3 19,24 AC_SYNC AC_SYNC PDD3 10M C88 R19 K21 PDD4 19,24 AC_BITCLK AC_BITCLK PDD4 P21 L20 PDD5 19,24,29 AC_SDOUT AC_SDOUT PDD5 X18PF Y22 M21 PDD6 19,24,30 AC_SDIN0 AC_SDIN0 PDD6 R149 10M W22 M22 PDD7 24,30 AC_SDIN1 AC_SDIN1 PDD7 N22 L22 PDD8 19,24,29 ICH_SPKR SPKR PDD8 Y2 L21 PDD9 PDD9 17,21 LAD0 Y12 K22 PDD10 LAD0/FWH0 PDD10 17,21 LAD1 W12 K20 PDD11 LAD1/FWH1 PDD11 32.768KHZ 17,21 LAD2 AB13 J21 PDD12 LAD2/FWH2 PDD12 C103 C102 17,21 LAD3 AB12 J20 PDD13 LAD3/FWH3 PDD13 17,21 LFRAME# AB11 H21 PDD14 LFRAME#/FWH4 PDD14 18PF 18PF Y13 H20 PDD15 21 LDRQ#0 LDRQ#0 PDD15 W13 PDD[0..15] 2 LDRQ#1 PDD[0..15] 17 2 RN70 15/8P4R D18 SDD0 SDD0 1 2 W17 B19 SDD1 18 USBP0P USBP0P SDD1 3 4 Y18 D19 SDD2 18 USBP0N USBP0N SDD2 5 6 AB19 A20 SDD3 18 USBP1P USBP1P SDD3 RN71 15/8P4R 7 8 AA19 C20 SDD4 18 USBP1N USBP1N SDD4 1 2 W18 C21 SDD5 18 USBP2P USBP2P SDD5 3 4 Y19 D22 SDD6 18 USBP2N USBP2N SDD6 5 6 AB20 E20 SDD7 18 USBP3P USBP3P SDD7 7 8 AA20 D21 SDD8 18 USBP3N USBP3N SDD8 C22 SDD9 SDD9 W19 D20 SDD10 VCC3_3 18 USBOC#0-1 OC#0 SDD10 Y20 B20 SDD11 OC#1 SDD11 Y21 C19 SDD12 18 USBOC#2-3 OC#2 SDD12 W20 A19 SDD13 OC#3 SDD13 C18 SDD14 R403 SDD14 K4 A18 SDD15 V3SB 24 EE_CS EE_CS SDD15 1K K3 SDD[0..15] 24 EE_DIN EE_DIN SDD[0..15] 17 J4 U19 24 EE_DOUT EE_DOUT SMLINK0 SMLINK0 15,30 J3 V20 24 EE_SHCLK EE_SHCLK SMLINK1 SMLINK1 15,30 B15 VRMPWRGD VRM_PWRGD 27 U20 R324 1K TP0 AA12 R271 R164 2 4 6 8 2 4 6 8 FS0 1 Document: Intel(R) 815E Chipset Universal Socket 370 CRB 1

CP1 2 4 6 8 2 4 6 8 CP2 Page Name: ICH2 Part 2 560K 560K 47PF/8P4C 82801BA ICH2 47PF/8P4C Last Revised: Page: Monday, April 30, 2001 1 3 5 7 1 3 5 7 Doc: Monday, April 30, 2001 Revision: 1 3 5 7 1 3 5 7 Platform Applications Engineering 1.05 1900 Prairie City Road Page No: Folsom, CA 95630 13 of 33 A B C D E A B C D E

V3SB V3SB VCC5 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC5 VCC5 VCC5 VCC12 VCC12- VCC12 VCC12-

4 4 PCI1 PCI2 B1 A1 B1 A1 -12V TRST# -12V TRST# B2 A2 B2 A2 TCK +12V TCK +12V B3 A3 B3 A3 GND TMS GND TMS B4 A4 B4 A4 TDO TDI TDO TDI B5 A5 B5 A5 +5V +5V +5V +5V B6 A6 B6 A6 PIRQ#B +5V INTA# PIRQ#A 11,15,30 +5V INTA# B7 A7 PIRQ#C B7 A7 PIRQ#D 11,15,30 PIRQ#B INTB# INTC# PIRQ#C 15,30 INTB# INTC# B8 A8 PIRQ#A B8 A8 15,30 PIRQ#D INTD# +5V INTD# +5V B9 A9 B9 A9 PRSNT#1 RESERVED PRSNT#1 RESERVED B10 A10 B10 A10 RESERVED +5V(I/O) RESERVED +5V(I/O) B11 A11 B11 A11 PRSNT#2 RESERVED PRSNT#2 RESERVED B12 A12 B12 A12 GND GND GND GND B13 A13 B13 A13 GND GND GND GND B14 A14 B14 A14 RESERVED RESERVED RESERVED RESERVED B15 A15 B15 A15 PCI_RST# GND RST# PCI_RST# 11,15,30 GND RST# 6 PCLK_1 B16 A16 6 PCLK_2 B16 A16 CLK +5V(I/O) CLK +5V(I/O) B17 A17 B17 A17 GND GNT PGNT#0 12 GND GNT PGNT#1 12 B18 A18 B18 A18 12,30 PREQ#0 REQ# GND 12,30 PREQ#1 REQ# GND B19 A19 B19 A19 PCI_PME# +5V(I/O) PME# PCI_PME# 11,12,15,22 +5V(I/O) PME# AD31 B20 A20 AD30 AD31 B20 A20 AD30 AD31 AD30 AD31 AD30 AD29 B21 A21 AD29 B21 A21 AD29 +3.3V AD29 +3.3V B22 A22 AD28 B22 A22 AD28 3 GND AD28 GND AD28 3 AD27 B23 A23 AD26 AD27 B23 A23 AD26 AD27 AD26 AD27 AD26 AD25 B24 A24 AD25 B24 A24 AD25 GND AD25 GND B25 A25 AD24 B25 A25 AD24 +3.3V AD24 +3.3V AD24 C_BE#3 B26 A26 R_AD16 R133 AD16 C_BE#3 B26 A26 R_AD17 R142 AD17 C/BE#3 IDSEL C/BE#3 IDSEL AD23 B27 A27 100 AD23 B27 A27 100 AD23 +3.3 AD23 +3.3 B28 A28 AD22 B28 A28 AD22 GND AD22 GND AD22 AD21 B29 A29 AD20 AD21 B29 A29 AD20 AD21 AD20 AD21 AD20 AD19 B30 A30 AD19 B30 A30 AD19 GND AD19 GND B31 A31 AD18 B31 A31 AD18 +3.3V AD18 +3.3V AD18 AD17 B32 A32 AD16 AD17 B32 A32 AD16 AD17 AD16 AD17 AD16 C_BE#2 B33 A33 C_BE#2 B33 A33 C/BE#2 +3.3V C/BE#2 +3.3V B34 A34 B34 A34 FRAME# GND FRAME# FRAME# 12,15,30 GND FRAME# B35 A35 IRDY# B35 A35 12,15,30 IRDY# IRDY# GND IRDY# GND B36 A36 B36 A36 TRDY# +3.3V TRDY# TRDY# 12,15,30 +3.3V TRDY# B37 A37 DEVSEL# B37 A37 12,15,30 DEVSEL# DEVSEL# GND DEVSEL# GND B38 A38 B38 A38 STOP# GND STOP# STOP# 12,15,30 GND STOP# 12,15,30 PLOCK# B39 A39 PLOCK# B39 A39 LOCK# +3.3V LOCK# +3.3V 12,15,30 PERR# PERR# B40 A40 PERR# B40 A40 PERR# SDONE PERR# SDONE B41 A41 B41 A41 +3.3V SBO# +3.3V SBO# B42 A42 SERR# B42 A42 12,15,30 SERR# SERR# GND SERR# GND B43 A43 B43 A43 PAR +3.3V PAR PAR 12,15 +3.3V PAR C_BE#1 B44 A44 AD15 C_BE#1 B44 A44 AD15 C/BE#1 AD15 C/BE#1 AD15 AD14 B45 A45 AD14 B45 A45 AD14 +3.3V AD14 +3.3V B46 A46 AD13 B46 A46 AD13 2 GND AD13 GND AD13 2 AD12 B47 A47 AD11 AD12 B47 A47 AD11 AD12 AD11 AD12 AD11 AD10 B48 A48 AD10 B48 A48 AD10 GND AD10 GND B49 A49 AD9 B49 A49 AD9 GND AD9 GND AD9

AD8 B52 A52 C_BE#0 AD8 B52 A52 C_BE#0 AD8 C/BE#0 AD8 C/BE#0 AD7 B53 A53 AD7 B53 A53 AD7 +3.3V AD7 +3.3V B54 A54 AD6 B54 A54 AD6 +3.3V AD6 +3.3V AD6 AD5 B55 A55 AD4 AD5 B55 A55 AD4 AD5 AD4 AD5 AD4 AD3 B56 A56 AD3 B56 A56 AD3 GND AD3 GND B57 A57 AD2 B57 A57 AD2 GND AD2 GND AD2 AD1 B58 A58 AD0 AD1 B58 A58 AD0 AD1 AD0 AD1 AD0 B59 A59 B59 A59 +5V(I/O) +5V(I/O) +5V(I/O) +5V(I/O) ACK64# B60 A60 ACK64# B60 A60 15,30 ACK64# ACK64# REQ64# REQ64#1 30 ACK64# REQ64# REQ64#2 30 B61 A61 B61 A61 +5V +5V +5V +5V B62 A62 B62 A62 +5V +5V +5V +5V

PCI_CON_32BIT PCI_CON_32BIT

AD[0..31] 12,15 AD[0..31] 1 Document: Intel(R) 815E Chipset Universal Socket 370 CRB 1 C_BE#[0..3] 12,15 C_BE#[0..3] Page Name: PCI 1 and 2 Last Revised: Page: Monday, April 30, 2001 Doc: Monday, April 30, 2001 Revision: Platform Applications Engineering 1.05 1900 Prairie City Road Page No: Folsom, CA 95630 14 of 33 A B C D E A B C D E

V3SB VCC3_3 VCC3_3

VCC5 VCC5

VCC12- VCC12

4 4 PCI3 B1 A1 -12V TRST# B2 A2 TCK +12V B3 A3 GND TMS B4 A4 TDO TDI B5 A5 +5V +5V B6 A6 +5V INTA# PIRQ#C 14,30 B7 A7 14,30 PIRQ#D INTB# INTC# PIRQ#A 11,14,30 B8 A8 11,14,30 PIRQ#B INTD# +5V B9 A9 PRSNT#1 RESERVED B10 A10 RESERVED +5V(I/O) B11 A11 PRSNT#2 RESERVED B12 A12 GND GND B13 A13 GND GND B14 A14 RESERVED RESERVED B15 A15 GND RST# PCI_RST# 11,14,30 6 PCLK_3 B16 A16 CLK +5V(I/O) B17 A17 GND GNT PGNT#2 12 B18 A18 12,30 PREQ#2 REQ# GND B19 A19 +5V(I/O) PME# PCI_PME# 11,12,14,22 AD31 B20 A20 AD30 AD31 AD30 AD29 B21 A21 AD29 +3.3V B22 A22 AD28 3 GND AD28 3 AD27 B23 A23 AD26 AD27 AD26 AD25 B24 A24 AD25 GND B25 A25 AD24 +3.3V AD24 C_BE#3 B26 A26 R_AD18 R148 AD18 C/BE#3 IDSEL AD23 B27 A27 100 AD23 +3.3 B28 A28 AD22 GND AD22 AD21 B29 A29 AD20 AD21 AD20 AD19 B30 A30 AD19 GND B31 A31 AD18 +3.3V AD18 AD17 B32 A32 AD16 AD17 AD16 C_BE#2 B33 A33 C/BE#2 +3.3V B34 A34 GND FRAME# FRAME# 12,14,30 B35 A35 12,14,30 IRDY# IRDY# GND B36 A36 +3.3V TRDY# TRDY# 12,14,30 B37 A37 12,14,30 DEVSEL# DEVSEL# GND B38 A38 GND STOP# STOP# 12,14,30 12,14,30 PLOCK# B39 A39 LOCK# +3.3V 12,14,30 PERR# PERR# B40 A40 PERR# SDONE SMLINK0 13,30 B41 A41 +3.3V SBO# SMLINK1 13,30 B42 A42 12,14,30 SERR# SERR# GND B43 A43 +3.3V PAR PAR 12,14 C_BE#1 B44 A44 AD15 C/BE#1 AD15 AD14 B45 A45 AD14 +3.3V B46 A46 AD13 2 GND AD13 2 AD12 B47 A47 AD11 AD12 AD11 AD10 B48 A48 AD10 GND B49 A49 AD9 GND AD9

AD8 B52 A52 C_BE#0 AD8 C/BE#0 AD7 B53 A53 AD7 +3.3V B54 A54 AD6 +3.3V AD6 AD5 B55 A55 AD4 AD5 AD4 AD3 B56 A56 AD3 GND B57 A57 AD2 GND AD2 AD1 B58 A58 AD0 AD1 AD0 B59 A59 +5V(I/O) +5V(I/O) ACK64# B60 A60 14,30 ACK64# ACK64# REQ64# REQ64#3 30 B61 A61 +5V +5V B62 A62 +5V +5V

PCI_CON_32BIT

Document: Intel(R) 815E Chipset Universal Socket 370 CRB 1 AD[0..31] 1 12,14 AD[0..31] Page Name: PCI 3 C_BE#[0..3] Page: Monday, April 30, 2001 12,14 C_BE#[0..3] Last Revised: Doc: Monday, April 30, 2001 Revision: Platform Applications Engineering 1.05 1900 Prairie City Road Page No: Folsom, CA 95630 15 of 33 A B C D E A B C D E VCC5

VCC5 VCC1_8

F5 BC68 BC223 FUSE_1.0A 0.22UF 0.22UF

4 4 VFB3 F5_FB11 8 VID_RED 1 2 R73 R84 2

BEAD 1K FB11 1K C50 C49 VGA1 PR12 U28 BEAD 6 75,1% 3.3PF X10PF 1 RV 1 1 16 MONOPU 11 VCC3 SD2 7 2 15 GV 2 VCC1 SD1 DDCDA 12 3 14 8 VFB2 VIDEO_1 SYNC_OUT2 BV 3 8 VID_GREEN 1 2 4 13 HS 13 VIDEO_2 SYNC_IN2 9 BEAD 5 12 MON2PU 4 VIDEO_3 SYNC_OUT1 PR11 C47 C46 VS 14 6 11 10 75,1% GND SYNC_IN1 3.3PF X10PF 5 7 10 R321 10 DDCCL 15 POWER_UP DDC_OUT2 VFB1 8 9 R322 10 VGA_CONN 8 VID_BLUE VCC2 DDC_OUT1 3 1 2 3 R85 33 R87 33 BEAD PAC-VGA201/QSOP PR10 C43 C45 BC224 BC225 C55 C54 C57 C56 C48 C53 75,1% 3.3PF X10PF 0.22UF0.22UF 22PF 10PF 22PF 10PF 10PF 10PF

U8 QST3384 D4 24 U8_VCC VCC VCC5 8 3VDDCDA 3 2 5VDDCDA 1 2 1A1 1B1 8 3VDDCCL 4 5 5VDDCCL 3 4 1A2 1B2 8 CRT_HSYNC 7 6 5VHSYNC R326 22 5 6 1N4148 1A3 1B3 8 CRT_VSYNC 8 9 5VVSYNC R327 22 7 8 1A4 1B4 11 10 R95 BC86 1A5 1B5 8 3VFTSDA 14 15 5VFTSDA VCC3SBY VCC1_8 C134 C135 RN41 2.2K/8P4R 2A1 2B1 8 3VFTSCL 17 16 5VFTSCL 4.7K 0.1UF 2A2 2B2 18 19 100PF 100PF 2A3 2B3 21 20 2A4 2B4 22 23 2A5 2B5 1 R97 R96 BEA# 13 12 R328 2.2K VCC1_8 BEB# GND 2 4.7K 4.7K R329 2.2K 2

R350 1k Place 100pF cap near DVO pin 40 FTVREF VCC5 C136 C137 FTVSYNC 8 R351 FTHSYNC 8 1k 0.01uF 100pF SL_STALL 8 7,17,21,30 PCIRST# 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60

Y J3 C HS SP2 VS SP0 SP1 SP3 5V2 3V1 PD# I/C 5V1 3V2 3V3 3V4 SCL SDA RST# CVBS SCL5 VREF VDD1 VDD2 VDD3 VDD4 SDA5 VCC5 VCC3_3 VCC1_8 DVO CONNECTOR G9 G3 G7 G10 G1 G2 G5 G6 G8 G11 G4 G12 D/B D11 D10 STB D5 D4 D9 D8 D7 D6 ST# D3 D2 D1 C138 C139 C140 C141 C142 C143 C144 D0 1 3 G1 5 7 G2 9 11 G3 13 15 G4 17 19 21 23 G5 25 27 G6 29 31 G7 33 35 G8 37 39 41 43 G9 45 47 G10 49 51 G11 53 55 G12 57 59 1.0uF 1.0uF 1.0uF 2.2uF 1.0uF 1.0uF 2.2uF FTD11 Document: Intel(R) 815E Chipset Universal Socket 370 CRB 1 FTD10 1 FTD9 Page Name: VGA Header and DVO Debug Header FTD8 FTCLK0 8 FTD7 Page: Monday, April 30, 2001 FTCLK1 8 Last Revised: FTD6 Doc: Monday, April 30, 2001 FTBLNK# 8 FTD5 Revision: FTD4 Platform Applications Engineering FTD3 1.05 FTD2 1900 Prairie City Road FTD1 Page No: 8 FTD[0..11] FTD[0..11] FTD0 Folsom, CA 95630 16 of 33 A B C D E 8 7 6 5 4 3 2 1 IDE

FWH PDD[0..15] 13 PDD[0..15] VCC3_3 VCC3_3 PDA[0..2] 13 PDA[0..2] IDE1 IDERST# R113 33 IDERST_IDE1_PIN1 1 2 30 IDERST# PDD7 3 4 PDD8 D D BC173 BC175 BC177 BC178 VCC3_3 PDD6 5 6 PDD9 R207 PDD5 7 8 PDD10 0.1UF PDD4 9 10 PDD11 0 0.1UF 0.1UF 0.1UF PDD3 11 12 PDD12 R79 PDD2 13 14 PDD13 PDD1 15 16 PDD14 4.7K PDD0 17 18 PDD15 U23 19 20 1 32 21 22 VPP VCC 13 PDREQ 2 31 23 24 7,16,21,30 PCIRST# RST# CLK PCLK_8 6 13 PDIOW# R206 8.2K 3 30 FPGI4 R211 8.2K 25 26 FGPI3 FGPI4 13 PDIOR# 4 29 27 28 FGPI2 IC 13 PIORDY 5 28 29 30 FGPI1 GNDA 13 PDDACK# 6 27 31 32 FGPI0 VCCA 12 IRQ14 7 26 PDA1 33 34 WP# GND P66DET 12 12 GPIO23 8 25 VCC3_3 R83 8.2K PDA0 35 36 TBL# VCC 9 24 37 38 ID3 INIT# INIT# 4,12 13 PDCS#1 PDCS#3 13 10 23 39 40 ID2 FWH4 LFRAME# 13,21 24 IDEACTP# 11 22 ID1 RFU 12 21 PIN_2X20 ID0 RFU 13,21 LAD0 13 20 PDA2 R80 FWH0 RFU 13,21 LAD1 14 19 C51 FWH1 RFU 13,21 LAD2 15 18 10K FWH2 RFU 16 17 LAD3 13,21 47PF C GND FWH3 C FWH32

SDD[0..15] 13 SDD[0..15] SDA[0..2] 13 SDA[0..2] IDE2 IDERST# R112 33 IDERST_IDE2_PIN1 1 2 SDD7 3 4 SDD8 VCC3_3 SDD6 5 6 SDD9 SDD5 7 8 SDD10 SDD4 9 10 SDD11 SDD3 11 12 SDD12 R76 SDD2 13 14 SDD13 SDD1 15 16 SDD14 4.7K SDD0 17 18 SDD15 19 20 21 22 13 SDREQ 23 24 13 SDIOW# 25 26 13 SDIOR# 13 SIORDY 27 28 29 30 B 13 SDDACK# B 31 32 12 IRQ15 SDA1 33 34 S66DET 12 VCC3_3 R75 8.2K SDA0 35 36 13 SDCS#1 37 38 SDCS#3 13 39 40 24 IDEACTS# PIN_2X20 R70 SDA2 C44 10K 47PF

A Document: Intel(R) 815E Chipset Universal Socket 370 CRB A Page Name: FWH and UDMA100 IDE Last Revised: Page: Monday, April 30, 2001 Doc: Monday, April 30, 2001 Revision: Platform Applications Engineering 1.05 1900 Prairie City Road Page No: Folsom, CA 95630 17 of 33 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1

VCC5DUAL

F4 FUSE_1.0A

13 USBOC#0-1 USB1 1 2 1 VCC0 2 DATA0- FB8 BEAD 3 DATA0+ EC18 BC4 4 + GND0 5 VCC1 D 100UF 470PF 6 D DATA1- 1 2 7 DATA1+ 8 GND1 1 2 FB21 BEAD USB_CON2 13 USBP0N 1 2 FB22 BEAD 13 USBP0P 13 USBP1N 1 2 FB23 BEAD 13 USBP1P FB24 BEAD 2 4 6 8 1 3 5 7 2 4 6 8 RN72 CP3 15K/8P4R 47PF/8P4C 1 3 5 7 2 4 6 8 V3SB 1 3 5 7

R266 R267 330K 330K C C

24 CNR_OC# R268 X0 VCC5DUAL

11 AGP_OC# R269 X0 F7 FUSE_1.0A

13 USBOC#2-3

1 2 USB2 FB25 BEAD 1 2 3 4 1 2 5 6 7 8 EC39 C122 1 2 FB26 BEAD + 9 10 470PF 100UF 1 2 FB27 BEAD HEADER5X2

1 2 FB28 BEAD

FB29 BEAD 13 USBP2N B 13 USBP2P B

13 USBP3N 2 4 6 8 13 USBP3P 2 4 6 8 CP4 1 3 5 7 RN73 47PF/8P4C

15K/8P4R 1 3 5 7 2 4 6 8 1 3 5 7

1 2 JP4 24 CNRUSBN 3 JP4 Pin 3 near USB2 Pin 5 24 CNRUSBP 4 HEADER5 JP4 Pin 4 near USB2 Pin 7 5 1 2 JP5 11 AGPUSBN 3 11 AGPUSBP 4 JP5 Pin 3 near USB2 Pin 6 5 JP5 Pin 4 near USB2 Pin 8 HEADER5

A Document: Intel(R) 815E Chipset Universal Socket 370 CRB A Page Name: USB Last Revised: Page: Monday, April 30, 2001 Doc: Monday, April 30, 2001 Revision: Platform Applications Engineering 1.05 1900 Prairie City Road Page No: Folsom, CA 95630 18 of 33 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1

VCC3_3 VCC5 VCC5_AUDIO 1 PFB6

BEAD 2 D D

BC140 BC139 BC136 BC129 0.1UF 0.1UF 0.1UF 0.1UF

U15 4 1 7 9 38 42 25 26 40 44 43 NC40 NC44 NC43 AVSS2 AVSS1 DVSS1 DVSS2 AVDD2 AVDD1 DVDD1 DVDD2

13,24,29 ICH_SPKR R336 1K R336_MC56 MC56 1UF PC_BEEP 12 PC_BEEP 20 LINE_IN_R 24 LINE_IN_R 20 LINE_IN_L 23 LINE_IN_L 20 MIC_IN 21 11 MIC1 RESET# PRI_DWN_RST# 29 22 5 C MIC2 SDATA_OUT AC_SDOUT 13,24,29 C 20 CD_R 20 8 CD_R SDATA_IN AC_SDIN0 13,24,30 20 CD_L 18 10 CD_L SYNC AC_SYNC 13,24 20 CD_REF 19 6 CD_REF AC'97 BIT_CLK AC_BITCLK 13,24 17 VIDEO_R 16 46 VIDEO_L CODEC CS1 20 AUX_L 14 45 AUX_L CS0 20 AUX_R 15 48 AUX_R CHAIN_CLK 13 47 PHONE EAPD EAPD 20 24 AC97SPKR R154 100 R154_MC58 MC58 1UF MONO_OUT 37 MONO_OUT 20 LNLVL_OUT_R 36 C99 LINE_OUT_R 20 LNLVL_OUT_L 35 LINE_OUT_L 41 X10PF LNLVL_OUT_R 39 LNLVL_OUT_L

AFILT1 AFILT2 FILT_L FILT_R RX3D CX3D VREF VREFOUT XTL_OUT XTL_IN R252 CS4299

29 30 32 31 33 34 27 28 3 2 1K

B R253 X0 AUD_VREFOUT 20 B

XTAL_IN AFILT1 AFILT2 FILT_L FILT_R CX3D VREF RX3D

MC51 VREFOUT Y1 R254

0.1uF NPOP XTAL_OUT 1K 24.576MHZ

R337 R155 C95 C94 MC53 MC54 MC52 MC55 MC46 MC48 C98 C97 220K 220K 2700PF 2700PF 1UF 1UF 1UF 0.1UF 4.7UF 2.2UF 22PF 22PF

"SINGLE POINT CONNECTION"

A Document: Intel(R) 815E Chipset Universal Socket 370 CRB A Page Name: AC'97 Codec Last Revised: Page: Monday, April 30, 2001 Doc: Monday, April 30, 2001 Revision: Platform Applications Engineering 1.05 1900 Prairie City Road Page No: Folsom, CA 95630 19 of 33 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1

Stereo HP/Spkr out

C77 R104 FB13

C87_C77 + 1 2 SPKROUT_R JK1 100UF 22 BEAD

C78 R105 FB14

+ 1 2 SPKROUT_L D D 100UF 22 BEAD MC47 R132 PHONEJACK MC47_R132 C75 C74 19 LNLVL_OUT_L 1UF 20K 100PF 100PF C87 100PF C74_JK1

R126 20K

U11_OUTA VCC5_AUDIO U11 MC45 R127 1 8 R128 OUTA VDD MC45_R127 U11_INA 2 7 U11_OUTB 20K C90 19 LNLVL_OUT_R INA OUTB U11_BYPASS 3 6 U11_INB 100PF BYPASS INB 1UF 20K 4 5 GND SHUTDN LM4880

MC40 1UF BC123 C C 0.1UF 19 EAPD

Line_In Analog Input CD Analog Input MC44 FB17 CD2 MC44_R122 R122 R122_FB17 1 2 JK2_LINE_IN_R R115 MC43 19 LINE_IN_R 1K CD_INR CDIN_R JK2 1 CD_R 19 1UF BEAD 2 3 CD_ING 1K 1UF CD_INL MC42 FB16 4 R117 MC39 MC42_R121 R121 R121_FB16 1 2 JK2_LINE_IN_L CDIN_L 19 LINE_IN_L CD_L 19 1K 2.54_WAFER_4 1K 1UF BEAD 1UF C80 C86 PHONEJACK R116 MC38 CDIN_REF CD_REF 19 100PF 100PF 1K 1UF B CD1 B 1 R125 C81 R118 C79 R124 C82 2 220K 220K 220K 3 100PF 100PF 100PF 4

2mm_WAFER_4

R119 Microphone Input R119_FB15 JK3 AUX1 MC36 19 AUD_VREFOUT AUX_INL 2.2K 1 AUX_L 19 2 MC41 R120 FB15 3 1UF MC37 R120_MC41 1 2 JK3_MICIN 4 AUX_INR 19 MIC_IN AUX_R 19 1K 1UF BEAD 2.54_WAFER_4 1UF C76 PHONEJACK C83 C84 C85 0.01UF 100PF 100PF 100PF

A Document: Intel(R) 815E Chipset Universal Socket 370 CRB A "SINGLE POINT CONNECTION" Page Name: Audio I/O Last Revised: Page: Monday, April 30, 2001 Doc: Monday, April 30, 2001 Revision: Platform Applications Engineering 1.05 1900 Prairie City Road Page No: Folsom, CA 95630 20 of 33 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1

IRRX 23 25 VTT_SENSE IRTX 23 RI#1 22 DCD#1 22 9,10,13,24,30,32 SMBDATA R185 TXD1 22 300 RXD1 22 9,10,13,24,30,32 SMBCLK R193 DTR#1 22 300 RTS#1 22 25 -5VIN DSR#1 22 25 -12VIN CTS#1 22 25 +12VIN 25 +3.3VIN CASEOPEN# 13,25 D D 25 VCORE SUSCLK 13 25 HM_VREF 25 VTIN3 SLP_S3# 6,13,28 FB20 R157 VCC5SBY VCC5 IOAVCC 10K 1 2 R166 PS_ON 25 FB19 0 1 2 BEAD PWROK 13,25 BC172 R167 V3SB 0.1UF 10K BEAD RSMRST# 13 4,25 THRMDN PANSWIN 24,32 VCCRTC PWRBTN# 13,33 VCC5 MDAT 23 BC154 BC161 MCLK 23 0.1UF 0.1UF U17 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VSS VCC RIB# SINB -5VIN VBAT VREF AVCC MCLK VTIN3 MDAT AGND PSIN# -12VIN RTSB# CTSB# DTRB# DSRB# +12VIN DCDB# SOUTB +3.3VIN PSOUT# VCOREA VCOREB SCL/GP21 SDA/GP22 SUSCLKIN IRTX/GP26 IRRX/GP25 PLED/GP23 WDTO/GP24 CIRRX/GP34 CASEOPEN# 4,25 VTIN2 103 SUSCIN/GP30 PWROK/GP32 64 VTIN2 PWRCTL#/GP31 RSMRST#/GP33 SUSLED/GP35 SUSLED 24 25 VTIN1 104 63 C VTIN1 KDAT KDAT 23 C 13,30 OVT# 105 62 OVT# KCLK KCLK 23 106 61 VID4 VSB VCC5SBY 27,29,32 VID3 107 60 VID3 KBRST KBRST# 12,30 27,29,32 VID2 108 59 VID2 GA20M A20GATE 12,30 27,29,32 VID1 109 58 VID1 KBLOCK# KEYLOCK# 24 27,29,32 VID0 110 57 VID0 RIA# RI#0 22 25 FANIO3 111 56 FANIO3 DCDA# DCD#0 22 25 FANIO2 112 55 FANIO2 VSS 25 FANIO1 113 54 FANIO1 SOUTA TXD0 22 114 53 VCC SINA RXD0 22 115 52 25 FANPWM2 FANPWM2 DTRA# DTR#0 22 116 51 25 FANPWM1 FANPWM1 W83627HF RTSA# RTS#0 22 117 50 VSS DSRA# DSR#0 22 24 BEEP 118 49 BEEP CTSA# CTS#0 22 23 MIDI_IN 119 48 MSI/GP20 VCC VCC5 23 MIDI_OUT 120 47 MSO/IRQIN0 STB# STB# 22 23 J1BUTTON2 121 46 GPSA2/GP17 AFD# AFD# 22 23 J2BUTTON2 122 45 GPSB2/GP16 ERR# ERR# 22 23 JOY1Y 123 44 GPY1/GP15 INIT# PAR_INIT# 22 23 JOY2Y 124 43 GPY2/P16/GP14 SLIN# SLIN# 22 23 JOY2X 125 42 GPX2/P15/GP13 PD0 23 JOY1X 126 41 GPX1/P14/GP12 PD1 23 J2BUTTON1 127 40 BC151 GPSB1/P13/GP11 PD2 23 J1BUTTON1 128 39 0.1UF GPSA1/P12/GP10 PD3

B B DRVDEN0 DRVDEN1 INDEX# MOA# DSB# DSA# MOB# DIR# STEP# WD# WE# VCC TRAK0# WP# RDATA# HEAD# DSKCHG# CLKIN PME# VSS PCICLK LDRQ# SERIRQ LAD3 LAD2 LAD1 LAD0 VCC3V LFRAME# LRESET# SLCT PE BUSY ACK# PD7 PD6 PD5 PD4 PDR0 22 FDD Signals Trace 8 or 10 mil W83627HF PDR1 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 PDR2 22 FDC1 PDR3 22 RWC# 1 2 PDR4 22 3 4 PDR5 22 DS1# 5 6 PDR6 22 7 8 PDR7 22 MOA# 9 10 ACK# 22 DSB# 11 12 BUSY 22 DSA# 13 14 PE 22 MOB# 15 16 SLCT 22 17 18 DIR# STEP# 19 20 PCIRST# 7,16,17,30 21 22 WD# VCC5 23 24 WE# 25 26 VCC3_3 27 28 29 30 31 32 HEAD# BC162 BC155 33 34 .1U .1U

HEADER_17X2 6 SIO_CLK24 12,30 LPC_PME# 6 PCLK_7 A A 13 LDRQ#0 Document: Intel(R) 815E Chipset Universal Socket 370 CRB 12,30 SERIRQ Page Name: Super I/O and FDC 13,17 LAD3 13,17 LAD2 Last Revised: Page: Monday, April 30, 2001 13,17 LAD1 Doc: Monday, April 30, 2001 13,17 LAD0 Revision: 13,17 LFRAME# Platform Applications Engineering 1.05 1900 Prairie City Road Page No: Folsom, CA 95630 21 of 33 8 7 6 5 4 3 2 1 A B C D E

WAKE ON LAN VCC12- VCC12 VCC5 COM1 VCC5SBY D6 D7 COM1 U9 DCD0 1 SS12/SMD SS12/SMD DSR0 6 10 1 RXDD0 2 -12V 12V 4 11 20 RTS0 7 4 GND 5V TXDD0 3 11,12,14,15 PCI_PME# WOL1 12 9 DCD0 BC99 CTS0 8 21 DCD#0 RY5 RA5 3 13 8 DTR0 .1U DTR0 4 21 DTR#0 DA3 DY3 Q21 R230 2 14 7 CTS0 RI0 9 21 CTS#0 RY4 RA4 1 15 6 TXDD0 5 21 TXD0 DA2 DY2 16 5 RTS0 21 RTS#0 DA1 DY1 100 17 4 RXDD0 21 RXD0 RY3 RA3 2 4 6 8 2 4 6 8 2N3904 HEADER_3*1(2MM) 18 3 DSR0 CONNECTOR_DB9 21 DSR#0 RY2 RA2 R229 19 2 RI0 CN3 2 4 6 8 2 4 6 8 CN2 4.7K 21 RI#0 RY1 RA1 GD75232 100PF/8P4C 100PF/8P4C 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 WAKE ON MODEM 13,30 ICH_RI# U10 COM2 R107 10 1 CTS1 -12V 12V RI0 Q14 11 20 DSR1 2N3904 GND 5V DTR1 10K R108 12 9 DCD1 BC54 RXDD1 3 21 DCD#1 RY5 RA5 3 2.2K 13 8 DTR1 .1U COM2 21 DTR#1 DA3 DY3 14 7 CTS1 DCD1 21 CTS#1 RY4 RA4 1 2 15 6 TXDD1 TXDD1 21 TXD1 DA2 DY2 3 4 16 5 RTS1 21 RTS#1 DA1 DY1 5 6 R109 17 4 RXDD1 RTS1 21 RXD1 RY3 RA3 7 8 RI1 Q15 18 3 DSR1 RI1 21 DSR#1 RY2 RA2 9 10 2N3904 19 2 RI1 21 RI#1 RY1 RA1 10K R110 HEADER_5X2 2.2K GD75232 2 4 6 8 2 4 6 8

CN11 2 4 6 8 2 4 6 8 CN9

21 AFD# Parallel Port 100PF/8P4C 100PF/8P4C 1 3 5 7 1 3 5 7 21 ERR#

VCC5 1 3 5 7 1 3 5 7 D2

U5 SS12/SMD 21 PAR_INIT# 1 28 P1 P8 BC49 2 21 SLIN# 2 27 .1U 2 P2 P7 LPT1 21 STB# 3 26 1 SI1 SO1 14 21 PDR0 4 25 2 SI2 SO2 15 21 PDR1 5 24 3 SI3 SO3 16 21 PDR2 6 23 4 SI4 SO4 17 21 PDR3 7 22 5 SI5 GND 18 21 SLCT 8 21 6 P3 SO5 19 21 PDR4 9 20 7 SI6 VCC 20 21 PE 10 19 8 P4 SO6 21 21 PDR5 11 18 9 SI7 SO7 22 21 BUSY 12 17 10 P5 SO8 23 21 PDR6 13 16 11 SI8 SO9 24 Document: Intel(R) 815E Chipset Universal Socket 370 CRB 1 21 PDR7 14 15 12 1 SI9 P6 25 Page Name: Serial, Parallel, WOL, and WOR 13 Last Revised: Page: Monday, April 30, 2001 PAC-S1284 Doc: Monday, April 30, 2001 21 ACK# LPT Revision: Platform Applications Engineering 1.05 1900 Prairie City Road Page No: Folsom, CA 95630 22 of 33 A B C D E A B C D E

VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 R103 0

F6 XFUSE_1.0A 2 FB12 BEAD R92 R99 R94 R93 R102 R101 C70 4 4 4.7K 4.7K 4.7K 4.7K 1 4.7K 4.7K 470PF J1 1 RN40 1K/8P4R 9 J1BUT1 21 J1BUTTON1 8 7 2 6 5 J2BUT1 10 21 J2BUTTON1 4 3 JOY_1X 3 21 JOY1X 2 1 JOY_2X 11 21 JOY2X 4 R98 47 MIDI_OUTPUT 21 MIDI_OUT 12 RN39 1K/8P4R 5 8 7 JOY_2Y 13 21 JOY2Y 6 5 JOY_1Y 6 21 JOY1Y 4 3 J2BUT2 14 21 J2BUTTON2 J1BUT2 21 J1BUTTON2 2 1 7 R91 47 MIDI_INPUT 15 21 MIDI_IN 8

C60 C66 GAME_PORT 1000PF 22PF 8 6 4 2 8 6 4 2 C73 8 6 4 2 8 6 4 2 C64 C68 C62 C59 CN8 CN10 3 3 1000PF 22PF 470PF 470PF 470PF

C63 C67 470PF/8P4C 7 5 3 1 7 5 3 1 470PF/8P4C 22PF 1000PF

7 5 3 1 7 5 3 1 Game Port C65 C71 22PF 1000PF

VCC5DUAL R17 0 FB1 F1 XFUSE_1.0A 1 2

BEAD R18 0

F2 XFUSE_1.0A FB3 U1 1 2 CN1_U1 21 KDAT 1 2 BEAD 3 FB5 2 4 2 1 2 21 KCLK 5 6 BEAD RN4 4.7K/8P4R 13 8 7 14 6 5 FB2 15 4 3 1 2 2 1 16 BEAD 17 FB4 1 2 21 MDAT 7 8 BEAD 9 FB6 10 1 2 21 MCLK 11 12 BEAD KB/MOUSE IR1 CN1 VCC5 1 8 7 8 7 2 6 5 C1 C2 6 5 3 4 3 21 IRRX 4 3 4 2 1 2.2UF 2.2UF Keyboard 1 2 1 Document: Intel(R) 815E Chipset Universal Socket 370 CRB 1 21 IRTX 5 470PF8P4C Page Name: PS/2, Game, and IR HEADER_1X5 Mouse Last Revised: Page: Monday, April 30, 2001 Doc: Monday, April 30, 2001 Revision: IR Platform Applications Engineering 1.05 1900 Prairie City Road Page No: Folsom, CA 95630 23 of 33 A B C D E 8 7 6 5 4 3 2 1

Power V3SB VCC5SBY VCC5 VCC3_3 VCC12-VCC5SBY VCC12 V3SB VCC5 CNRSLOT1 Switch SW2 B1 A1 RESERVED RESERVED 1 2 B2 A2 1 2 RESERVED RESERVED B3 A3 RESERVED GND R246 B4 A4 GND RESERVED 3 4 R233 R242 R244 R243 R238 2.2K B5 A5 3 4 RESERVED RESERVED 10K 220 10K 150 220 B6 A6 RESERVED GND SW_4 B7 A7 GND LAN_TXD2 LAN_TXD2 12 D B8 A8 D 12 LAN_TXD1 LAN_TXD1 LAN_TXD0 LAN_TXD0 12 B9 A9 12 LAN_RSTSYNC LAN_RSTSYNC GND PN1 B10 A10 GND LAN_CLK LAN_CLK 12 R238_PN1 B11 A11 1 12 LAN_RXD2 LAN_RXD2 LAN_RXD1 LAN_RXD1 12 B12 A12 2 12 LAN_RXD0 LAN_RXD0 RESERVED B13 A13 3 GND USB+ CNRUSBP 18 KEYLOCK B14 A14 21 KEYLOCK# 4 RESERVED GND B15 A15 5 +5VDUAL USB- CNRUSBN 18 12 EXTSMI# 18 CNR_OC# B16 A16 6 USB_OC# +12V R243_PN1 B17 A17 7 GND GND D15_PN1 HDD LED B18 A18 R272 C125 R273 C126 8 -12V +3.3VDUAL B19 A19 15K 15K R242_PN1 9 +3.3VD +5VD 47PF 47PF 10 PWR_SW 21,32 PANSWIN 11 B20 A20 12 GND GND R241 BC185 B21 A21 13 13 EE_DIN EE_DOUT EE_DIN EE_DOUT 13 10K R240 R240_PN1 SMI_SW B22 A22 14 13 EE_SHCLK EE_SHCLK EE_CS 0.1UF 0 B23 A23 EE_CS 13 GND SMB_A1 C119 HEADER_14 B24 A24 SMB_A0 SMB_A2 9,10,13,21,30,32 SMBCLK B25 A25 SMB_SCL SMB_SDA SMBDATA 9,10,13,21,30,32 0.1UF 12,29 PRI_DWN# B26 A26 PRIMARY_DN# AC97_RESET# AC_RST# 13,29 B27 A27 GND RESERVED D15 1N4148 13,19 AC_SYNC B28 A28 AC97_SYNC AC97_SD_IN1 AC_SDIN1 13,30 13,19,29 AC_SDOUT B29 A29 C 17 IDEACTP# AC97_SD_OUT AC97_SD_IN0 AC_SDIN0 13,19,30 C 13,19 AC_BITCLK B30 A30 AC97_BITCLK GND

D14 1N4148 CNR R247 17 IDEACTS# 20K

SW3 VCC5 1 2 1 2 VCC5SBY VCC5 3 4 VCC5 VCC5 R255 3 4 10K SW_4 SMBCLK Reset R235 R234 Switch 10K 150 SMBDATA PN2 1 25,32 HWRST# RESET SMB2 SMB1 2 1 1 3 2 2 4 3 3 5 SPEAKER 4 4 B 6 B R237_PN2 5 5 7 8 SMBCON SMBCON 9 GREEN LED 10 11 D16 21 SUSLED Q22 R237 12 RESERVE VCC5SBY R239 330 2N3904 13 14 0 LED

R237_2 HEADER_14 VCC5 VCC5 SP1 R236 R223 10K R232 68 33 BUZZER

21 BEEP Q19 R231 68 R256 0 2N3904

JP2 13,19,29 ICH_SPKR R226 2.2K Q20 Document: Intel(R) 815E Chipset Universal Socket 370 CRB A 1 2 2N3904 BC184 A 3 4 0.1UF Page Name: Front Panel Headers and CNR XHEADER 2X2 Last Revised: Page: Monday, April 30, 2001 Doc: Monday, April 30, 2001 19 AC97SPKR Revision: JP2 PC_BEEP SELECTION Platform Applications Engineering 1-2 ON TRADITIONAL 1.05 3-4 ON CONTROLLED by AC97 CODEC 1900 Prairie City Road Page No: Folsom, CA 95630 24 of 33 8 7 6 5 4 3 2 1 A B C D E

VCC3_3 VCC5SBY VCC5 V3SB

ATXPR1 11 1 3.3V 3.3V VCC12- 12 2 BC164 D10 -12V 3.3V 13 3 .1U 1N4148 R190 R189 GND GND 14 4 VCC5SBY 15K 21 PS_ON PS_ON +5V 15 5 4.7K GND GND 14 16 6 U20C U19A GND +5V 17 7 GND GND VCC_5- 18 8 ATXPWROK 5 6 1 2 -5V PWROK 4 19 9 4 +5V AUX5V VCC5SBY VCC5 20 10 74LVC14A C115 R192 +5V +12V VCC12 74LVC06A 33K

ATX_PWCON 7 2.2UF

VCC5SBY

U20F U19F

R245 100 13 12 13 12 VCC5SBY 24,32 HWRST# 74LVC14A U20D U19E V3SB V3SB 74LVC06A 9 8 11 10 PWROK 13,21 74LVC14A R323 BC165 V3SB VCC5SBY 74LVC06A 1K .1U U20A U19B 14 4 DBRESET# 1 2 3 4 7 74LVC14A 3 3 74LVC06A Temperature Sensing JP3

1 2 HEADER_2

21 VTIN3

PR38 RT2 t VCC12 VCC5 21 HM_VREF 10K,1% X10K_1%-THRM/0603 R218 "system use" 4.7K 21 VTIN1 Q18 CHASSIS FAN R210 PR39 RT1 t R217 1K 2N2907 D13 R212 +12CHFAN 4,21 VTIN2 30K 10K,1% 10K_1%-THRM/0603 1N4148 1K C118 Q17 FAN3 "power use" EC38 3300PF + 3 FANIO1 21 2N7002 2 21 FANPWM1 4,21 THRMDN R216 510 22UF 1 PR36 HEADER_3 VCC12 PR37 Voltage Sensing 2 28K,1% 10K,1% 2 VCC12 VCC5 +12VIN 21 R11 VCCVID R209 VCORE 21 4.7K 10K Q2 CPU FAN 2N2907 D1 R19 VTT R208 R10 1K VTT_SENSE 21 +12CPUFAN 10K 1K 1N4148 R214 FAN1 VCC3_3 Q1 EC3 +3.3VIN 21 + 3 2N7002 FANIO2 21 10K 2 21 FANPWM2 22UF PR35 PR34 R16 510 1 VCC12- 56K,1% 232K,1% HEADER_3 -12VIN 21 VCC12 VCC5 -5VIN 21 PR33 PR32 VCCRTC R213 10M VCC_5- 56K,1% 120K,1% 13,21 CASEOPEN# PWR FAN EC35 + D5 R100 If case is opened, Document: Intel(R) 815E Chipset Universal Socket 370 CRB 1 this switch should be closed. 22UF 1N4148 1K 1 S1 FAN2 Page Name: ATX Power and HW Monitor 3 FANIO3 21 HEADER_2PIN 2 Last Revised: Page: Monday, April 30, 2001 1 Doc: Monday, April 30, 2001 Revision: HEADER_3 Platform Applications Engineering 1.05 1900 Prairie City Road Page No: Folsom, CA 95630 25 of 33 A B C D E A B C D E

VCC5SBY VCC12 VCC3_3

VCC5 Q39 2 1 U31_FORCE1 PHD55N03LT VDDQ 2 1 R354 C155 C156 C157 C158 C159 3.3k R357 4 0.1uF 100uF 100uF 4.7uF 4.7uF 4 3 0 D23 BAT54C U31_SENSE1

R356 3 3.3k R355_C147 R358 R401 R400 C147 1M - NPOP VCC3_3 220 220 11 TYPEDET# C148 1.0uF Q48_B Q48 R355 PNP VCC3_3 0.1uF 0 Q49_B Q49 U31 NPN 8 7 VCC FORCE 1 R359 U31_SHDN1# 5 6 R402 SHDN1# SENSE 1 10k 3 1 VCC3_3 SHDN2# FORCE 2 470 4 2 U31_SHDN2# GND SENSE 2 Empty for ADM1051AJR ADM1051A 3 3 Q40 U31_FORCE2 MTD3055VLT4 C150 C151 C152 C153 C149 VCC1_8 U31_SENSE2 100uF 100uF 4.7uF 4.7uF 0.1uF

VCC5 R360 VCC12 100 1% Target is R378 3 really 1.85V 2.2k

D24 3 R361 5620 1% BAT54C VTTPWRGD12 6 Q43 2N7002 VTT 2 1 VCC5

2 1 VCC5 R379 2 VTT VCC5 U32A ASSERTED LOW! 1k 2 VCC3_3 R380 VR1 8 20k V1_8SB U32B R381 VCC VTTPWRGD 4 2 3 1k VOUT IN+ 1 3 C160 1 D24_U32 5 Q44 VIN OUT 1 IN+ 2 R364 2 7 2N7002 IN- 1 OUT 2 1 VR1_FB 22uF Tantalum 4 C173 6 ADJ C162 GND 0.1 uF IN- 2 C174 LT1587-ADJ 49.9 1% V1_8SB 2.0ms delay 10 uF 0.1uF LM393 Ch1 nominal LM393 Ch2 VTTPWRGD5# 27

R366 732 1% Document: Intel(R) 815E Chipset Universal Socket 370 CRB Q41 FDN335N R367 U32-2 Page Name: VRegs: Vddq, Vcc1_8, and Vtt 4,6,7 TUAL5 1 R368 Last Revised: Page: Monday, April 30, 2001 1 10 1% 1k 1% Doc: Monday, April 30, 2001 Revision: Platform Applications Engineering 1.05 1900 Prairie City Road Folsom, CA 95630 Page No: 26 of 33 A B C D E A B C D E

VCC5 L7 1.7uH Q45_L7

C175 C176 C177 C178 C179 C180 C181 10uF 0.1uF 3300uF 3300uF 0.1uF 4.7uF 4.7uF

U34_R384 4 VCC12 C182 0.001uF 4 U34 U34_C182 R382 10 (805) R382_U34 16 11 Q45 VCC CS+ VID3 1 10 SUD50N03-07 R383 R384 VID3 CS- C183 C184 VID2 2 19 220 220 VID2 PGND 0.1uF 4.7uF VID1 3 18 U34-18R385 4.7 (805) VID1 DRVH VCCVID VID0 4 17 U34-17R386 2.2 (805) L8 1.2uH VID0 DRVL VID4 5 9 VCCVID_FB Q45_L8 VID25 FB 8 6 R389 2 mOhm (2512) 21,29,32 VID[0:4] SD PWRGD VRM_PWRGD 13 7 R388 C185 C186 C187 26 VTTPWRGD5# REF U34_R391 13 14 Q46_R386 820uF 820uF 1000uF COMP LRDRV U34_C18812 15 U34_1415 2.2 (805) CT LRFB VCC5 C188 20 GND Q46 ADP3170 SUD50N03-07 C189 C190 C191 C192 R390 100pF 4700pF 820uF 820uF 1000uF R391 0 3 25.5k 1% 3

R393 R392 0 C193 0.001uF C194 154k 1% 0.1uF

V3SB New V1_SB Circuitry

This takes the place of R404 the old V1_8SB circuit. V1_8SB 2 32.4 1% 2

C197 R405 38.3 1%

Document: Intel(R) 815E Chipset Universal Socket 370 CRB Page Name: VRegs: VCCVID, V1_8SB 1 Last Revised: Page: Monday, April 30, 2001 1 Doc: Monday, April 30, 2001 Revision: Platform Applications Engineering 1.05 1900 Prairie City Road Folsom, CA 95630 Page No: 27 of 33 A B C D E A B C D E

VCC5SBY VCC12 VCC3_3 VCC5 VCC2_5 Q3

3 2

EC17 EC11 EC19 VIN ADJ VOUT C7 + + + LM1117ADJ 4 4 0.1UF 100UF 10UF 100UF 1 + EC6 PR3 + EC5

1 14 U2 10UF 100,1% 100UF Q3_Feedback Q7 12V

Q4 5VSB 15 U2_Q7 DRV2 HUF76121D3S/TO252 U2_Q4 3 NZT651/SOT223 3V3DLSB PR2 16 VSEN2 VCC3SBY 4 100,1% V3SB U2_R20 3V3DL VCC5SBY 9 EC14 FAULT/MSET C5 EC20 + + C18 R20 1UF 1500UF 10UF 1UF 10K EC10 + 11 U2_Q5 5VDLSB Q5 100UF 6 NDS356AP/SOT23 6,13,21 SLP_S3# S3 7 13 SLP_S5# S5 5 12 EN5VDL 5VDL VCC5DUAL VCC5SBY 2 U2_C4 EN3VDL 3 13 10 3 SS GND DLA C8 C4 RT9641

8 1UF 0.1UF

U2_Q8

Q8

4 5 G2 D2 VCC3_3 3 6 S2 D2 Do not stuff this box. 2 7 G1 D1 Debug note: VCC5 1 8 VCC1_8 Stuff only one box. S1 D1 Stuff this box

VCC3_3 VCMOS R369 FDS8936 / SI9936 Q42 1.13 1% 2 EC22 EC15 2 + + 1206 pack 3 2

100UF 100UF VIN ADJ VOUT LT1117ADJ

+ EC42 1 + EC43 PR44 10UF 10UF R370 49.9 1% 9.31 1% 1210 pack Q42_Feedback

PR45

10 1%

1 Document: Intel(R) 815E Chipset Universal Socket 370 CRB 1 Page Name: VRegs: Duals, 3.3SB, 2.5, VCMOS Last Revised: Page: Monday, April 30, 2001 Doc: Monday, April 30, 2001 Revision: Platform Applications Engineering 1.05 1900 Prairie City Road Page No: Folsom, CA 95630 28 of 33 A B C D E A B C D E

V3SB 2 4 6 8 RN59 2.2K/8P4R 1 3 5 7

4 VCC3_3 SW1 DIPSW-8 4 1 16 2 15 3 14 4 13 SW1_R262 R262 8.2K 5 12 AC_SDOUT 13,19,24 SW1_R263 R263 8.2K 6 11 ICH_SPKR 13,19,24 7 10 8 9

D17 13,24 AC_RST#

1N4148

VCC5SBY 3 3 U19C

12,24 PRI_DWN# 5 6 PRI_DWN_RST# 19

R153 74LVC06A

10K

SW 7 ON BOARD AC97 CODEC OFF PRIMARY CODEC ON DISABLE

VCC3_3 V3SB

J5 2 1 2 3 1 3,32 JPR_VID0 2 1 3 2 3 2 5 4 5 6 4 3,32 JPR_VID1 5 4 6 6 8 7 8 9 7 3,32 JPR_VID2 8 7 SW 5 AC_SDOUT 9 ON USE CPU FREQ STRAP IN ICH REGISTER 9 11 10 11 12 10 3,32 JPR_VID3 11 10 OFF FORCE CPU FREQ STRAP TO SAFE MODE(1111) 12 12 14 13 14 15 13 SW 6 STRAP(SPKR) 3,32 JPR_VID4 14 13 15 15 ON NO REBOOT ON 2ND WATCHDOG TIMEOUT 17 16 17 18 16 OFF REBOOT ON 2ND WATCHDOG TIMEOUT 4,32 BSEL#1 17 16 18 18 20 19 20 21 19 4,32 BSEL#0 20 19 21 21 7x3 JPR HDR 2 4 6 8 2 4 6 8 RP5 RP6 1K/8P4R 1K/8P4R

Document: Intel(R) 815E Chipset Universal Socket 370 CRB

1 1 3 5 7 1 3 5 7 1 Page Name: System Config DIP Switches 21,27,32 VID0 Last Revised: Page: Monday, April 30, 2001 21,27,32 VID1 Doc: Monday, April 30, 2001 21,27,32 VID2 Revision: 21,27,32 VID3 R394 8.2k 27,32 VID4 Platform Applications Engineering 7 R_REFCLK FMOD1 6 1.05 FMOD0 6 1900 Prairie City Road 7 R_BSEL#0 Page No: R395 8.2k Folsom, CA 95630 29 of 33 A B C D E A B C D E

PCI VCC5 ICH2 V3SB VCC3_3 VCC3_3 VCC5 RP2 RN55 12,14,15 PERR# 1 5 13 SMBALERT# 1 2 R1 C 12,14,15 SERR# 2 13,22 ICH_RI# 3 4 R2 12,14,15 PLOCK# 3 9,10,13,21,24,32 SMBCLK 5 6 BC163 R196 R3 12,14,15 STOP# 4 10 9,10,13,21,24,32 SMBDATA 7 8 .1U 1K R4 C 14 12,14,15 DEVSEL# 6 R5 12,14,15 TRDY# 7 8.2K/8P4R V3SB U18A R6 12,14,15 IRDY# 8 RN60 1 2 R7 IDERST# 17 12,14,15 FRAME# 9 12,21 LPC_PME# 1 2 R8 3 4 74LVC07A 4 2.7K/10P8R 13,15 SMLINK0 5 6 4

RN58 13,15 SMLINK1 7 8 7 1 2 12,15 PREQ#2 3 4 4.7K/8P4R V3SB VCC3_3 12,14 PREQ#1 5 6 RN54 VCC3_3 12,14 PREQ#0 7 8 12 GPI8 1 2 13 GPIO25 3 4 R197 2.7K/8P4R 12 GPIO27 5 6 RN64 7 8 1K 1 2 14 12 PREQ#3 3 4 8.2K/8P4R VCC3_3 U18B 12 PREQ#5 5 6 RN51 3 4 PCI_RST# 11,14,15 12 PREQ#4 7 8 12 PCI_REQ#A 1 2 13,21 OVT# 3 4 74LVC07A 2.7K/8P4R 12,21 KBRST# 5 6

RN66 12,21 A20GATE 7 8 7 14,15 ACK64# 1 2 14 REQ64#1 3 4 8.2K/8P4R VCC3_3 VCC3_3 14 REQ64#2 5 6 VCC3_3 VCC3_3 VCC3_3 15 REQ64#3 7 8 12,21 SERIRQ R276 8.2K 2.7K/8P4R R188 R198 13,19,24 AC_SDIN0 R147 10K 1K 1K 14 14 3 3 13,24 AC_SDIN1 R152 10K U18D U18C 12 ICHRST# R188_U18 9 8 5 6 PCIRST# 7,16,17,21 74LVC07A 74LVC07A

VCC3_3 7 7 RN74 RN75 11,14,15 PIRQ#A 1 2 1 2 11,14,15 PIRQ#B 3 4 3 4 14,15 PIRQ#C 5 6 5 6 14,15 PIRQ#D 7 8 7 8

0/8P4R 8.2K/8P4R RN76 RN77 1 2 1 2 3 4 3 4 VCC3_3 5 6 5 6 7 8 7 8

X0/8P4R 8.2K/8P4R 12 ICH_IRQ#A 14 U20B 12 ICH_IRQ#B U18E 3 4 12 ICH_IRQ#C VCC5SBY 11 10 2 12 ICH_IRQ#D 74LVC14A 2 74LVC07A 12 ICH_IRQ#E

12 ICH_IRQ#F 7 U20E 12 ICH_IRQ#G U19D 11 10 12 ICH_IRQ#H 9 8 74LVC14A VCC3_3

74LVC06A 14 U18F 13 12 74LVC07A 7

1 Document: Intel(R) 815E Chipset Universal Socket 370 CRB 1 Page Name: Pullup/Pulldown Rs and Unused Gates Last Revised: Page: Monday, April 30, 2001 Doc: Monday, April 30, 2001 Revision: Platform Applications Engineering 1.05 1900 Prairie City Road Page No: Folsom, CA 95630 30 of 33 A B C D E A B C D E

VCC12 " ATX POWER " VCC12- " ATX POWER " VCC3_3 " ATX POWER " VCC5 " ATX POWER " VCC_5- " ATX POWER "

EC26 BC168 BC180 BC143 BC157 EC36 BC142 BC156 BC167 BC179 EC33 BC85 BC83 EC27 BC41 BC53 EC28 BC69 BC70 22UF 0.1UF 0.1UF 0.1UF 0.1UF 22UF 0.1UF 0.1UF 0.1UF 0.1UF 22UF 0.1UF 0.1UF 22UF 0.1UF 0.1UF 22UF 0.1UF 0.1UF

4 4

VCCVID

MC3 MC4 MC2 MC1 MC5 MC6 MC8 MC9 MC10 MC13 MC14 MC15 MC49 MC50 MC64 MC65

4.7UF/X7R 4.7UF/X7R 4.7UF/X7R 4.7UF/X7R 4.7UF/X7R 4.7UF/X7R 4.7UF/X7R 4.7UF/X7R 4.7UF/X7R 4.7UF/X7R 4.7UF/X7R 4.7UF/X7R 4.7UF/X7R 4.7UF/X7R 4.7UF/X7R 4.7UF/X7R

VCC3SBY " DIMM0 : Near Power Pins " VDDQ " Display Cache : Near the Power Pins "

MC31 MC30 MC11 MC16 BC76 BC66 BC39 BC19 BC8 BC10 MC35 MC34 MC33 MC32 BC101 BC102 BC103 BC104 BC112 BC111 BC110 BC108

4.7UF 4.7UF 4.7UF 4.7UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 4.7UF 4.7UF 4.7UF 4.7UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF

3 3 VCC1_8 " GMCH : 0.1U//0.01U at each conner and each side-center "

MC26 MC24 BC78 BC71 BC50 BC42 BC43 BC44 BC45 BC81 BC75 BC114 BC105 BC95 BC96 BC79 BC46 BC47

4.7UF 4.7UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF

VCC3SBY " GMCH : Near System Mem Quadrant " VDDQ " GMCH : Near Display Cache Quadrant " VCC3SBY " DIMM1 : Near Power Pins " " Within 70 mils of GMCH "

BC87 BC82 BC80 BC74 BC88 BC65 BC48 BC51 BC52 BC94 BC91 BC97 BC92 BC93 BC98 MC12 MC17 MC27 MC25 BC11 BC20 BC40 BC67 BC77 BC84

0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 4.7UF 4.7UF 4.7UF 4.7UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF

VCC3_3 " ICH : 0.1U//0.01U at each conner " V3SB " ICH : Near Power Pins " VCC1_8 " ICH : Near Power Pins " V1_8SB " ICH : Near Power Pins " 2 2

BC131 BC132 BC138 BC121 BC150 BC149 BC147 BC124 MC57 MC59 BC204 BC205 BC206 BC207 BC115 BC113 BC116 BC208 BC209 BC210 BC211 BC212

0.1UF 0.1UF 0.1UF 0.1UF 0.01UF 0.01UF 0.01UF 0.01UF 2.2UF 2.2UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF

VCC3_3 " misc. " VCC3SBY " DIMM2 : Near Power Pins "

BC100 BC107 BC106 BC109 BC122 BC128 BC145 BC146 BC144 BC158 BC159 BC160 BC169 BC170 BC171 BC183 BC182 BC181 BC187 BC186 MC60 MC61 MC62 MC63 BC213 BC214 BC215 BC216 BC217 BC218

0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 4.7UF 4.7UF 4.7UF 4.7UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF

H1 HOLE A H3 HOLE A H4 HOLE A H5 HOLE A H6 HOLE A H7 HOLE A H8 HOLE A H9 HOLE A 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 Document: Intel(R) 815E Chipset Universal Socket 370 CRB 1 2 7 2 7 2 7 2 7 2 7 2 7 2 7 2 7 1 3 6 3 6 3 6 3 6 3 6 3 6 3 6 3 6 Page Name: Decoupling Caps 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 Last Revised: Page: Monday, April 30, 2001 Doc: Monday, April 30, 2001 Revision: Platform Applications Engineering 1.05 1900 Prairie City Road Page No: Folsom, CA 95630 31 of 33 A B C D E A B C D E

4 21,27,29 VID[4:0] J4 4 VID0 1 2 VID1 3,29 JPR_VID[4:0] 1 2 VID2 3 4 VID3 3 4 VID4 5 6 5 6 7 8 7 8 9 10 9 10 11 12 11 12 13 14 13 14 15 16 15 16 BSEL#1 4,29 17 18 17 18 BSEL#0 4,29 19 20 R_SMBDATA 19 20 R_SMBDATA 6 21 22 R_SMBCLK 21 22 R_SMBCLK 6 23 24 JPR_VID0 21,24 PANSWIN 23 24 JPR_VID1 25 26 JPR_VID2 25 26 JPR_VID3 27 28 JPR_VID4 R396 0 27 28 29 30 24,25 HWRST# 29 30 SMBDATA 9,10,13,21,24,30 SMBCLK 9,10,13,21,24,30 3 2x15 HDR 3 R397 0

VTT VTT VCC1_8 VCC3SBY VDDQ

J6 J7 J8 J9 J10 3 3 3 3 3 2 GTLREF 4,7 2 GTLREFA 4 2 HUBREF_ICH 12 2 2 CONN_AGPREF 8,11 1 1 1 1 1

HEADER_3 HEADER_3 HEADER_3 HEADER_3 HEADER_3

2 2

Document: Intel(R) 815E Chipset Universal Socket 370 CRB Page Name: Internal Debug headers 1 Last Revised: Page: Monday, April 30, 2001 1 Doc: Monday, April 30, 2001 Revision: Platform Applications Engineering 1.05 1900 Prairie City Road Folsom, CA 95630 Page No: 32 of 33 A B C D E A B C D E

4 4 VCC1_8 VCC1_8 V3SB

R409 R410 R411 4.7k 1K 20k

PWRBTN# 13,21

R412 1K Q51 2N3904

Q51_Q52

R408 Q50 4 THERMTRIP# 2N3904 0 R416 Q52_R416 Q52 3 4,7 CPURST# 2N3904 3 2.2k

2 2

4,12 CPU_PWGD Stuff either R5 or R415. See p4. R413 510 R415 0 N6395404 N6395403 4 R414 C198 1.3k X0.01uF 1 Document: Intel(R) 815E Chipset Universal Socket 370 CRB 1 No-stuff C198 - debug site only Page Name: Thermtrip Last Revised: Page: Monday, April 30, 2001 Doc: Monday, April 30, 2001 Revision: Platform Applications Engineering 1.05 1900 Prairie City Road Page No: Folsom, CA 95630 33 of 33 A B C D E