Europaisches Patentamt 0 384 257 J) European Patent Office © Publication number: A2 Office europeen des brevets

EUROPEAN PATENT APPLICATION

G09G 1/16 © Application number: 90102671.6 @) int. ci.5:

@ Date of filing: 12.02.90

© Priority: 23.02.89 US 314623 © Inventor: Lumelsky, Leon 30 Gaxton Road @ Date of publication of application: Stamford, Connecticut 06905(US) Inventor: Peevers, Alan Wesley 29.08.90 Bulletin 90/35 122 Wells Street Peekskill, New York 10566(US) © Designated Contracting States: DE FR GB © Representative: Herzog, Friedrich Joachim, © Applicant: International Business Machines Dipl.-lng. Corporation IBM Deutschland GmbH Schonaicher Old Orchard Road Strasse 220 Armonk, N.Y. 10504(US) D-7030 Boblingen(DE)

Audio video interactive display.

© A method and apparatus for synchronizing two synchronously with the high resolution graphics which of the independent rasters, such that a standard TV video monitor. A switching mechanism selects video is to and a high resolution computer generated graphics TV video and the high resolution graphics The TV frame buffer video may each be displayed on a high resolution be displayed at a given time. The graphics monitor. This is accomplished utilizing dual includes an on screen and off screen portion. frame buffers. A TV frame buffer, comprises a dual computer provides computer data, including high audio data to the TV port VRAM, with the serial and random ports operat- resolution graphics data and data stored in ing asynchronously. The primary port receives in- frame buffer, with the graphics being audio data coming TV video synchronously as it comes in, and the on screen portion and the being data is the secondary port reads the TV video out synchro- stored in the off screen portion. The audio The nously with the high resolution graphics monitor. A read out to an audio circuit for replay. graphics for of high resolution frame buffer in a computer is utilized data is combined with the TV video purposes to store high resolution graphics which is read out windowing. FIG. 1 mK "IOJO ;NfEKACn«E DISPLAY

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Field of Invention puter, so that video "windows" can be placed on the high resolution screen. The source of video can be any standard video source, such as a video The invention is in the field of display devices, camera, an optical videodisc player, a VCR, etc. and specifically is directed to an audio video inter- 5 Many video formats are supported, including, PAL, active display device in which two independent NTSC, SECAM, SVHS, etc. rasters are synchronized, such that a standard TV The audio section of the invention allows real video and a high resolution computer generated time stereo audio playback and recording from the graphics video may each be displayed in different host. This audio processing is completely indepen- combinations on a high resolution graphics monitor. io dent of the video capture process thus allowing the Computer generated audio may be played in con- user complete control over the audio portion of a junction with the display on the high resolution multi-media application. For example, a user may graphics monitor. select from one of several "soundtracks" to accom- pany a given video presentation. One application of 75 this feature could be the release of multi-lingual Background of The Invention material, where the audio/voice information is shipped in many languages, with the user selecting whichever language is preferred. One of the difficulties encountered when dis- There are three major ideas that are incor- playing motion video from a standard (e.g. NTSC) 20 porated into the approach taken to solve the tech- video source on a high-resolution graphics screen nical problems that are presented. The combination is that of synchronizing the two independent of these ideas yield a unique solution for smoothly "rasters". There is no inherent relationship between integrating digital video and audio within a host the timing (synchronization) of the two independent workstation environment. sources. If one were to try to use a conventional 25 memory architecture, it would be extremely difficult to synchronize the write operation, which is syn- TIME BASE CORRECTION chronous with the incoming video, with the read operation, which must be synchronous with the The problem of synchronizing the incoming TV high-resolution display on which the video is ulti- 30 video with the high-resolution graphics output from mately presented. the host can be solved using the unique dual-port Another challenge is presented by the high properties of VRAM technology. The secondary speed with which the video information must be (serial) port of these special-purpose VRAMs can manipulated in order to achieve full-motion video be operated completely asynchronously to the pri- performance. Attempting to do this with a conven- 35 mary (random) port. Hence, the primary port can tional display controller design risks having inad- be used to store incoming video information syn- equate performance. chronously, as it comes in, while the secondary Yet another challenge is presented by the fact port can read the video data out of the frame buffer that the manner in which television signals are synchronously with the high-resolution graphics displayed is fundamentally different from the meth- 40 display. Thus, a form of time base correction can od used by most high-resolution displays. The in- be achieved by appropriate use of the independent herently interlaced characteristic of the incoming properties of the video RAM's two ports. video in TV information must be eliminated in order to present it on the non-interlaced high-resolution graphics screen. Several possibilities exist for solv- 45 DUAL FRAME BUFFER APPROACH ing this problem, each having relative advantages and disadvantages. There are several approaches to combining video with high resolution graphics. Some methods simply double the scan rate of the incoming video Summary of The Invention 50 through the use of a line buffer, reading out each video line twice for each line of the high-resolution screen. This method, although it is quite simple to According to the present invention, a implement, has several major drawback. First, it workstation-based frame buffer is intended to add assumes that the high-resolution display is exactly full-motion, full-color, video and medium-to-high 55 twice the scan rate of the incoming video. This is quality stereo audio to a personal workstation envi- seldom the case, and always requires a gen-lock ronment. It supports the mixing of this motion video circuit at the very least to force this strict relation- with the high-resolutfon graphics of the host com- ship between the video and the graphics. It also EP 0 384 257 A2 fails to provide random access to the video in- display controller which is shown generally in FIG. formation from the host workstation, since there is 1; no frame buffer to store the video information. FIG. 4 is a block diagram of the sync gener- Another method involves converting the video and ator which is shown generally in FIG. 3; graphics information into a common format (e.g. 5 FIG. 5 is a block diagram of the source RGB) and storing the two into a single, common control logic which is shown generally in FIG. 4; frame buffer. While this may at first seem to be an FIG. 6 is a diagram illustrating sampling re- advantage in that only one frame buffer is required, gion parameters and sampling destination address- it can be seen that the requirements on this buffer es; require far more memory than having two separate w FIG. 7 is a block diagram of the FIFO shown dedicated buffers. Consider the following: generally in FIG. 3; High-resolution graphics has limited color content FIG. 8 is a block diagram of the memory (typically 8 or less bits/pixel) while having a large controller and arbiter shown generally in FIG. 3; number of pixels (typically 640x480, 1024x768, or FIG. 9 is a block diagram of the address higher). On the other hand, video information is rich 15 generator shown generally in FIG. 3; in color information (16-24 bits/pixel) but only limit- FIG. 10 is a block diagram of the video ed resolution (780x480 or less). In order to use a buffer shown generally in FIG. 3; single frame buffer to store both types of visual FIG. 1 1 is a block diagram of the serializer data, a very large frame buffer is required that is shown generally in FIG. 3; both "wide" and "deep" (e.g. 1024x768x24). Also, 20 FIG. 12 is a block diagram of the color key by storing both types of information in a common network shown generally in FIG. 3; frame buffer, the available update bandwidth has to FIG. 13 is a block diagram of the digital be shared between the two contending processes. audio circuitry shown generally in FIG. 1; By using a separate dedicated frame buffer for FIG. 14 is a block diagram of the digital TV the incoming video information, a memory organi- 25 input circuitry shown generally in FIG. 1 ; zation optimized for the unique characteristics of FIG. 15 is a block diagram of the digital TV motion video can be used. In addition, the update output circuitry shown generally in FIG. 1 ; and of the host computer's high-resolution graphics FIG. 16 and 17 are timing diagrams which screen is unimpeded by the process of sampling are useful in the understanding of the invention. live video. 30 Description of The Preferred Embodiment

DIGITAL TELEVISION APPROACH The system herein described may have many The use of a standard off-the-shelf digital TV 35 of the specific characteristics generalized to ac- chip set offers many advantages. These include commodate future improvements in digital televi- low cost, ready availability, more accurate control sion and personal computer display technologies of video parameters, ready acceptance of a wide without departing from the spirit of the invention. In variety of TV standards for worldwide use, and this embodiment, the digital television subsystem is convenient access for digital communications net- 40 based on a chip set manufactured by Philips. The works. It is also important to select a chip technol- host system is an IBM Personal System/2 Model ogy that uses the CCITT 601 recommendation of 70, which includes a VGA graphics (640x480x4 bit sampling video with a frequency that is an integer pixel) subsystem. A 12-bit luminance chrominance multiple of the incoming video Horizontal Sync (Y-C) representation is referred to here, however period. This feature eliminates the jitter that results 45 the concepts described can be generalized to in- when a sub-carrier based system is used in con- clude systems with wider (e.g. 16 or more bits) junction witb a non-standard source, such as a data paths and higher bandwidths e.g. high defini- VCR or videodisk. tion television (HDTV). In addition, the high-resolu- tion video described need not be limited to the so bandwidth and bits/pixel provided by the VGA. Fu- Brief Description of The Drawings ture digital TV and graphics technologies can read- ily be incorporated without departing from the spirit of this invention. FIG. 1 is a block diagram of an audio video interactive display; 55 FIG. 2 is a block diagram illustrating the dual AUDIO VIDEO DISPLAY CONTROLLER buffer concept; FIG. 3 is a block diagram of the audio video FIG. 1 is a system block diagram showing how EP 0 384 257 A2 a Audio Video Display Controller 100 interfaces to as microphones, CD players, stereo audio sources the other components of the system. It takes inputs and the like. Audio output signals, audio out left from digital TV input circuitry 200, a host computer (AOUTL) and audio out right (AOUTR) are provided 300, and a digital audio circuitry 400. The host to amplifiers and speakers (not shown). The control computer may receive input commands from input 5 of the digital audio circuitry is provided by a plural- devices such as a mouse 340 and keyboard 360. ity of signals from the audio video display control- The controller 100 provides outputs to the host ler 100. These signals include a sampling clock computer 300, a digital TV output circuitry 500, the signal for audio (SCAUD); an audio control or sync digital audio circuitry 400, and a high-resolution signal (ACTL); and an audio data signal ADAT. monitor 600 via the digital TV output circuitry 500. 10 The audio video display controller 100 re- The digital TV input circuitry 200 and the digital TV sponds to the respective signals from input cir- output circuitry 500 are of the type set forth in cuitry 200, host 300 and audio circuitry 400 to Phillips Corporation's manual 9398 063 3001 1 , date provide a plurality of signals to the digital TV of release 6/88 entitled "Digital Video Signal Pro- output circuity 500. These signals include control cessing." ;5 signals on bus I2C; a TV video image out (YCOUT); The digital TV input circuitry 200 receives a and a video color switch signal (KEY) which selects plurality of analog input signals VIN1, VIN2 and between the TV image YCOUT and the high reso- VIN3 which may be, for example a cable TV input, lution image HRRGB from the host for display on a TV antenna input, a VCR input or the like. It is to the high resolution monitor 600. Red, green and be appreciated there may be more or less video 20 blue output signals ROUT, GOUT and BOUT, re- inputs from different combinations of TV video spectively are applied to the monitor 600 from TV sources, such as two or more VCR inputs, two or output circuitry 500. more cable inputs etc. Refer now the FIG. 2 which illustrates in gen- The digital TV input circuitry responds to these eral the dual frame buffer concept of the invention. analog input signals to provide a plurality of digitiz- 25 A more detailed description is set forth in the ed TV output signals to the audio video display remaining figures. As previously stated, relative to controller 100. These output signals include a TV FIG. 1, the digital TV output circuitry 500 selects clock or sampling clock signal TVCK; horizontal between a standard digital TV video signal from a and vertical sync signals TVHS and TVVS, respec- buffer in the audio video display controller 100 and tively; and a digitized TV data signal YCIN. Control 30 a high resolution graphics video signal from a buff- signals are provided to the input circuit 200 from er in the host computer 300. In FIG. 2, a logic controller 100 on a control bus SVIN, which may block 700 includes a digital TV chip set 710, which also be known as an I2C bus. is a composite of digital TV input and output cir- The host computer 300, which for example cuitry 200 and 500, respectively of FIG. 1; a TV may be an IBM Personal System/2, the operation 35 frame buffer 720 and VLSI controller 730 which are of which is described in detail in the IBM Personal included in the audio video display controller 100 System/2 Model 50 and 60 Technical Reference, of FIG. 1; and a switch 740 which is included in the provides a plurality of signals to the controller 100. digital TV output circuitry 500 of FIG. 1. A Video These signals include a PC data signal (PCDATA) Graphics Adaptor (VGA) display controller 750 and which may include graphics information for inser- 40 a high resolution frame buffer 760 are connected to tion in the on screen portion of a TV frame buffer a PC bus 770 and are included in the host com- 145 (FIG. 3), or digitized audio to be stored in an puter 300 of FIG. 1. The PC bus is also connected off screen portion of buffer 145 for subsequent play to the digital TV chip set 710 and controller 730. by audio circuit 400, or other data applications; a The controller 730 receives PCDATA, PCADDR PC address signal (PCADDR) which indicates 45 and PCCNTL on the PC bus. The PC data may be where PCDATA is to be stored in the frame buffer host computer graphics data which is stored in an 145 (FIG. 3); PC control signals (PCCNTL); video on screen portion of buffer 720; or PC digital audio data for high resolution display (VDAT); high reso- data which is stored in an off screen portion of lution horizontal and vertical sync signals, (HRHS) buffer 720. This is described in detail relative to and (HRVS), respectively; a high resolution blan- so FIGS. 3 and 10. king signal (HRB); a high resolution clock signal In practice, an NTSC TV video signal is pro- (HRCK); and high resolution red, green and blue vided to chip set 710 and is converted to a digitiz- signals, (HRRGB) from a high-resolution buffer in ed TV speed signal which is written to the TV the host 300 is provided to the digital TV output frame buffer 720 under control of controller 730. A circuitry 500. 55 TV modified speed video signal is read from the The Digital Audio Circuitry 400 receives a plu- buffer 720, also under control of controller 730 to rality of audio inputs such as audio in left (AINL) chip set 710. The read and write operations are and audio in right (AINR) from audio sources such asynchronous with respect to each other. A TV EP 0 384 257 A2

RGB signal is then provided from chip set 710 as a the off screen portion of video buffer 145, this first input to switch 740. This first input is from the audio data may then be subsequently read out and TV Frame buffer. High resolution video information provided to AXVR 90 and transmitted to digital such as graphics video information is provided on audio circuit 400 for subsequent replay. PC Buss 770 to VGA display controller 750, which 5 The memory controller and arbiter 125 arbi- in turn provides high resolution pixel data to frame trates for various requests for memory cycles un- buffer 760. Buffer 760 provides a high resolution der control of PC control signals (PCCNTL) from graphics RGB signal to a second input of switch host 300. Besides the control signals utilized for 740. Switch 740 under control of control signals FIFO 1 1 5, AXCVR 90 and XCVR 92, as discussed from computer 300 selects which of the dual buff- w above, control signals are also provided to address ers 720 and 760 provides a RGB video signal to generator 135 and video buffer 145. Buffer 145 the high resolution VGA monitor at a given time. At receives a video control signal (VBCTRL) and ad- MOP and DONE any given time, the following is viewed on the VGA dress generator 135 receives a monitor: signals, which are described shortly. 1) An all TV image from buffer 720. 75 Address generator 135 receives PC addresses 2) An all graphics image from buffer 760. (PCADDR) from host 300 which are indicative of 3) A TV image from buffer 720 with at least where PC data is to be stored. Addresses one window of graphic images from buffer 760. (VBAADDR) are provided to the video buffer 1 45 to 4) A graphics image from buffer 760 with at indicate where data on the VIBUS is to be stored. least one window of TV images from buffer 720. 20 The PCADDR is also applied to a serial inter- A detailed description of the respective image face 94 which connects to the I2C bus, providing generations and selection process is set forth in SCVIN to digital input circuitry 200; SCVOUT to detail below. digital output circuitry 400, and SCAUD to digital FIG. 3 is a detailed block diagram, showing the audio circuitry 400. various components of the display controller 100. 25 Serializer 155 takes the video data out from The display controller 100 includes transceivers 90 video buffer 145 and provides it to digital TV output and 92, a serial interface 94, a sync generator 105; circuitry 500. Color key 165 provides a KEY signal FIFO logic 115; memory controller and arbiter 125; to digital TV output circuitry 145 for determining address generator 135; video buffer 145; serializer which video is displayed on high resolution display 155; and color key 165. 30 600 at a given time. The general operation of audio video display The main components of audio video display controller 100 is as follows. A sync generator 105 controller 100 are described in detail below. receives the TV clock signal (TVCK), TV horizontal sync signal (TVHS) and the TV vertical sync signal (TVVS) and in response thereto generates an audio 35 SYNC GENERATOR 105 control signal (ACTL) which is sent to the digital audio circuitry 400 and memory control and arbiter The main purpose of the Sync Generator cir- 125 to indicate when control of audio operations is cuit 105, as shown in FIG. 4, is to generate re- to take place. A SREQ signal output is utilized by quests to the memory controller for a video sam- TV is the memory control and arbiter 125 for windowing 40 pling cycle whenever the incoming raster operations. within a user-specified region. All information inside A FIFO 115 buffers incoming TV video data this region is written into the video buffer 145, while YCIN under control of TVCK and SGNT from mem- all information outside of this region is ignored. ory control and arbiter 125. Video out from the FIG. 6 illustrates how the "video sampling region" FIFO 115 is provided to the video bus (VIDBUS) 45 is defined. There are four parameters written to the when SGNT is high. The VIDBUS also receives Sync Generator 105 by the host computer 300. data from transceiver AXCVR 90 and transceiver These are: XStart, XEnd, YStart, and YEnd. XCVR 92. AXCVR 90 transmits to, and receives Referring to FIG. 4, it is seen that two counters digital data (ADAT) from digital audio circuit 400. are employed to keep track of where in the TV XCVR 92 receives PC data from host 300. This PC so raster the incoming video is from. For each incom- 106 data may comprise graphics video in the on screen ing video "pixel" a horizontal counter (HCNT) portion of video buffer 145, or digital audio for is incremented by the clock signal TVCK, which storage in the off screen portion of video buffer has the same frequency as the incoming digital 145. Memory control and arbiter 125 controls which video data. In this embodiment, this frequency is of FIFO 115, AXCVR 90 and XCVR 92 is providing 55 13.5 MHz or 910 times the period of TVHS-. At the data to the VIDBUS at a given time, based on the end of a scanline, this counter is reset (by TVHS-). state of SGNT or AGNT or PGNT, respectively. In a similar manner, a vertical counter (VCNT) 107 When the PC data is audio data that is stored in is incremented by TVHS-one time for every scan- EP 0 384 257 A2 10 line of incoming video. It is reset at the end of a the continuous stream of incoming video data while field by the TWS- signal. A source control logic the memory controller is busy handling other re- receiver has as inputs, PCDATA, and the outputs quests, such as memory refresh. Whenever sam- from counters 106 and 107. An audio timing logic pling is taking place, as indicated by SREQ being 109 has a single input from counter 106. 5 asserted at gate 116, video data on line 117 is The source control logic 108 is shown in FIG. shifted into the FIFO at the rate of one video 5, and is comprised of two pairs of comparators, sample per TV Clock (TVCK) at gate 119. As long one pair 110 and 111 for horizontal comparison, as the memory controller is actually performing one pair 112 and 113 for vertical comparison. Sample cycles (indicated by the fact that Sampling When the X- coordinate of the incoming raster falls w Grant on line 120, or SGNT, is asserted), video between XSTART 114 and XEND 115, the signal data can be shifted out of the other end of the INX from gate 116 is asserted. Similarly, when the FIFO on line 121, also at the TVCK rate. Y- coordinate of the incoming raster falls between If however the memory controller is busy per- YSTART 117 and YEND 118, the signal INY from forming another cycle, SGNT on line 120 is not gate 119 is asserted. When both signals are true, rs active, and no data is clocked out of the FIFO. Any the raster is within the rectangular region depicted samples that arrive during this time, accumulate in in FIG. 6, and the Sync Generator 105 generates a the FIFO. The FIFO only drives data onto the Video Sample Request (SREQ) from gate 120 to the Bus (VIDBUS) 121 when it has been granted ac- memory controller and arbiter 1 35. cess to the bus (when SGNT=1) by the Memory An additional function of the Sync Generator 20 Controller/Arbiter. 105 is to generate the appropriate timing signals to control the digital audio circuit by the audio timing logic 109 (FIG. 4). The timing is generated based MEMORY CONTROLLER AND ARBITER 125 on the video clock, TVCK which controls counter 106, the output of which controls logic 109. The 25 This circuit, illustrated in FIG. 8, is responsible audio sample rate is based on an integer divisor of for arbitrating between the various requests for TVCK. For the system shown, the rate is approxi- memory cycles, and then carrying out the cycle by mately 64KHz. Every audio sample is initiated by generating the appropriate control signals to the the assertion of an Audio Request (AREQ) signal at video buffer 145. It also signals to the other com- a first output of logic 109. An LR signal at a second 30 ponents in the system which memory cycle it is output of logic 109 toggles back and forth on every currently performing, as well as providing an in- other audio request, causing the left and right audio dication that the current cycle is complete. It con- channels to be digitized or played back on al- trols access to the shared Video Data base ternate audio cycles. This yields an effective sam- (VIDBUS) via a request/grant protocol. Although pling rate of 32 KHz per channel in this embodi- 35 multiple devices are attached to the Video Bus, this ment. An AUDDIR signal at a third output of logic scheme assures that only one device at a time is 109 is a control register bit that determines the allowed to drive data onto it. Finally, it can delay type of audio cycle being requested. If AUDDIR is the host computer's I/O cycle long enough to in- 0, an audio record (digitize) cycle is performed. If sure that the host's data has been safely written to AUDDIR is 1, an audio playback cycle is per- 40 or read from the Video Buffer. formed. This signal is used directly to control the There are four possible requests that come to direction of the Audio Transceiver (AXCVR). the memory controller and arbiter 125, and are A Filter Clock signal (FCK) at a fourth output of applied to the arbiter logic 126. These are: Audio logic 109 is used to clock the pre- and post- filters Request (AREQ), Sample Request (SREQ), Trans- at the appropriate rate. This frequency directly de- 45 fer Request (TREQ), and PC Request (PREQ). termines the cut-off frequency of these low-pass There are two additional signals that specify the filters. For a sample rate of 32 KHz, the cutoff direction of the Audio and PC cycles requested. frequency should be no more than 16 KHz accord- These are AUDDIR and PCDIR, respectively. In ing to the Nyquist Theorem. If a lower sampling these two cases, the sequence of control signals rate is required, for example to handle speech- so generated depends on the whether the memory quality audio, or to reduce host storage require- cycle is a read or a write. Each of the requests has ments, the frequency of FCK would have to be a predefined priority in the arbitration scheme. In lowered correspondingly. decreasing priority, they are: 1 . TREQ 55 2. AREQ FIFO LOGIC 115 3. SREQ 4. PREQ The FIFO 115 shown in FIG. 7 is used to buffer The arbiter 126 provides input to a memory 11 EP 0 384 257 A2 12 controller section 127. When the current memory Host (PC) 137, Display Refresh 138, and Audio cycle is completed, a DONE signal is asserted at addressing 139. As various cycles repeatedly take the output of controller 127, indicating this fact. At place, this circuit automatically updates the coun- this time, the currently asserted request with the ters so that the appropriate region of the Video highest priority is serviced. If the serviced request 5 Buffer is accessed. There is a large multiplexor 140 requires use of the common Video Bus, the re- which selects the counter output appropriate for the questing device is given control of the bus via an current operation and correctly divides the address appropriate Grant signal. The grant signals are into row and column components for successive Audio Grant (AGNT), PC Grant (PGNT), and Sam- output to the Video Buffer during RAS- and CAS- ple Grant (SGNT) provided at respective outputs of w respectively. arbiter 126. Note that the PGNT signal is used to The Sample Address Counters 136 generate a enable the PC data bus transceiver (PXCVR), while sequence of addresses that fill a rectangular region the direction of this transceiver is controlled by the of the Video Buffer 145 corresponding in size with PCDIR signal. the input region selected by the Sync Generator Once arbitration is completed, the memory cy- 75 105. The upper left corner of this region is stored cle appropriate to the winning request is per- in two registers: Sampling Destination X-address formed. A memory operation code (MOP) is pro- (SDX) 141 and Sampling Destination Y-address duced, indicating the type of memory cycle cur- (SDY) 142. These registers are set by the host rently being performed. computer using the PCDATA bus. Refer to FIG. 6. The specific sequence of control signals for the 20 As each sampling memory cycle completes (as Video Buffer 145 depends on the particular VRAM indicated by decoding the Memory Operation devices used to construct it. The control signals (MOP) to MOPSAMP via the Memory Operation are typical of all DRAM devices, with the exception Decoder 143, and finding DONE asserted), the of the TR/QE-signal, which is typical of VRAMs Horizontal Sampling Address (HSADDR) incre- only. Note that their are two separate Write Enable 25 ments across a scanline. At the end of each scan- signals (WEY- and WEC-) at the output of control- line, as signalled by TVHS-, the Vertical Sampling ler 127. This allows separate write access to the Address (VSADDR) is incremented by 1, and Luminance (Y) and Chrominance (C) information in HSADDR is reset to its initial value (SDX). At the the Video Buffer 145. For example, to write a end of a field, as signalled by TVVS-, VSADDR is monochromatic image of the incoming video, the 30 reset to its initial value (SDY). Video Buffer could first be cleared, and then only The Host (PC) Address counters 137 operate in the Luminance information would be sampled, a manner very similar to the Sample Address coun- keeping the Chrominance Write Enable signal ters 136. As each host memory cycle completes (WEC-) inactive (high) throughout. (as indicated by decoding MOP = MOPPC and A typical set of timing diagrams is shown in 35 DONE asserted), the Horizontal PC Address FIGS. 16 and 17. These control sequences are (HPADDR) increments. After a full line of video has generated using a generic sequences design, been read from (or written to) the video buffer 145 PC Address which progresses through multiple states until a by the host 300, the Vertical its given sequence (memory cycle) is completed. At (VPADDR) increments, and HPADDR is reset to this time the DONE signal from controller 127 is 40 initial value. The upper left corner of the region asserted, indicating to the other subsystems that accessed by the host is determined by the PC the current cycle is completed. Destination X-address (PDX) register 144 and PC When the host computer requests a memory Destination Y-address (PDY) register 146, both of cycle (via PREQ to arbiter 126), the RDY signal which can be set via the host data bus (PCDATA). from controller 127 is immediately brought inactive 45 This auto-increment scheme allows the host com- (low) in order to extend the host's bus cycle long puter to fill a rectangular region of the Video Buffer enough to transfer the data to the video buffer 145. 145 with a single stream-oriented instruction, such When the data transfer is complete, the RDY signal as the OUTSW or INSW instruction of the Intel is released, allowing the host computer 300 to 80X86 processors. complete the bus cycle. so The Video Refresh Counter (VREF) 138 is used to determine which scanline of video memory is to be transferred to VRAM serial port on the next ADDRESS GENERATOR 135 Video Refresh (TR/QE-) cycle. During each Hori- zontal Sync interval of the host's high resolution The Address Generator circuit 135 shown in 55 display (HRHS-), one scanline of VRAM must be FIG. 9 provides all addresses for the various Video transferred, so that the contents of the appropriate shifted out Buffer memory cycles outlined above. It includes scanline in the Video Buffer 1 45 can be separate, dedicated counters for Sampling 136, synchronously with the high-resolution display 600. 13 EP 0 384 257 A2 14

The particular sequence of Video Buffer scanlines necessary to start shifting video samples out of the transferred can be controlled by the host 300 using Video Buffer starting with the leftmost sample the Refresh Mode Register (REFMODE) 147. Nor- (column 0). mally, the lines are transferred progressively, with the Video Refresh Address (VREF) incrementing by one after each scanline is transferred. This in VIDEO BUFFER 145 known as progressive scan mode. This mode pro- vides the highest effective vertical resolution, but The Video Buffer 145 shown in FIG. 10 is an exhibits some "scalloping" artifacts if the subject array of Video Memories including an on screen moves horizontally from one field to the next. The 10 portion and an off screen portion. The on screen subject is seen in one position on the even scan- portion is used to store the live TV video image lines, and in another on the odd ones in between data as it comes in, and to store PC DATA when it The effect is most noticeable in distinct vertical is graphics data. In this particular embodiment, the edges with substantial horizontal motion. organization is 1,024 video samples across by 512 For this reason, another mode, called double- 75 scanlines high by 12 bits deep, being comprised of scan mode, is provided. Here, each Video Refresh 61 Megabit (512x512x4 bit) devices. These num- Address is used twice in succession, resulting in bers were chosen to accommodate the specific each of the incoming scanlines in the first (even) resolution and depth characteristics of the digital TV field being shown twice in the first high-speed TV chip set used. For future digital TV systems output frame. During the next (odd) TV field, the 20 having either higher resolution or deeper samples, Video Refresh address are again used twice each, it is simple to change the size of the video buffer to causing the scanlines in the next-speed output accommodate the new system's characteristics. frame to again be doubled. This mode has slightly The off screen portion is used to store PC DATA lower vertical resolution than the progressive mode, when it is audio data. It is to be appreciated that but is more appropriate for images that exhibit 25 two separate memories could be utilized in the artifacts using that mode. Since the scanlines are practice of the invention, that is a first memory to doubled, each high-speed output frame only con- store TV video data and graphics data from the tains information from one incoming TV field, so no host 300; and a second memory to store audio scalloping occurs. data from the host 300. The Horizontal and Vertical Audio Addresses 30 The incoming data bus (VIDBUS) 148 carries (HAUDADDR and VAUDADDR) are produced by ail information to and from the primary port of the the auto incrementing Audio Counters 139 when VRAM array. This includes incoming TV video data PCDATA from host 300 is audio data. They pro- to be sampled, digital audio data (in PC DATA and duce a sequence of addresses corresponding to an out), and host computer graphics data (PC DATA in off-screen region portion of Video Buffer 1 45. After 35 and out). The particular access being performed is each audio memory cycle completes (as indicated determined via standard control signals RAS-, by MOPAUD and DONE asserted), the counters CAS0-, TR/QE, WEY- by the memory controller increment, so that the next audio data from host 125 described above. The address at which a 300 is sorted in contiguous locations in the Video given cycle takes place is determined by VBADDR, Buffer 145. 40 which is provided by the Address Generator circuit The Address Multiplexor 140 performs two 135, also described above. As set forth above, TV functions in parallel. First, it selects the appropriate video data and host computer graphics data are address "type" from among the counters, Sam- stored in the on screen portion; and host audio pling 136, Host (PC) 137, Video Refresh 138, and data is stored in the off screen portion of video Audio 139. Second, each of these address types 45 buffer 145. @ must be split into it's row and column components Note that there are left and right halves of the before being driven to the VRAM array. So there Video buffer. Each half has a unique CAS-Line, are actually 8 possible inputs to the MUX 140, which allows a 2:1 interleaved access to the Frame divided into 4 pairs. The appropriate pair is deter- Buffer. This effectively halves the cycle time re- mined by examining the two high order bits of the 50 quired to transfer data into the Buffer. This is MOP (the LSB of MOP is only used to indicate critical, since the incoming video samples are be- direction). The Row Address component must drive ing clocked out of the FIFO 115 at the TVCK rate, the Video Buffer Address while RAS- falls, in order or approximately every 70 nsec in this system. The to be strobed into the VRAM's Row Address fastest page mode cycle that can be performed latches. Once RAS- has fallen, the Column Address 55 using today's VRAM technology is around 90nsec. component of a pair is selected. Note that the By using 2:1 interleave, effective page mode ac- Column Address component of the Video Refresh cess times as fast as 45nsec are achieved, which Address is always exactly 0. This is because it is is sufficient for current motion video data rates. For 15 EP 0 384 257 A2 16 significantly higher data rates, higher interleave ra- The Color Key circuit 165, shown in FIG. 12, is tios and deeper Video Buffer organizations are used to generate a keying signal (KEY) on output required. line 166, which in turn is used by the digital TV There are separate Write Enable signals for output circuitry 500 to switch between TV video Luminance and Chrominance, for reasons men- 5 pixels (from the YCOUT bus) and the pixels from tioned above under the Memory Controller 125 the host's high-resolution graphics controller. With description. reference to FIG. 2, every pixel during which KEY There are two separate 12-bit serial data bus- is asserted is seen on the monitor as video from ses shown here, one for each of the left and right the TV frame buffer 720, while those during which halves. Every time the VRAM serial ports are shift- w KEY is low are seen as video from the high- ed via the SC signal from the serializer 155, two resolution frame buffer 760. separate video samples are shifted out. The The KEY signal on line 166 from key select serializer 155, described below, takes these two logic 167 is determined in comparator 168 by samples and presents them sequentially. The rate comparing the incoming high-resolution pixel with at which video samples are shifted out of the 75 two pre-defined colors set by the host computer as VRAMs is completely independent of the rate at manifested by Key 1 logic 169 and Key 2 logic which video samples are put in, being limited only 170. If the incoming pixel is between the two pro- by the maximum serial clock frequency of the grammed values (R1 < A < R2), the key signal is devices, which is typically 25 MHz or higher. This asserted. This allows a range of colors to be speci- is the primary advantage of using VRAMSs as the 20 fied for which video will be overlayed. If it is video buffer, since the host's high-resolution dis- desired to have only one specific color overlayed play will in general be completely asynchronous with video, the KEY signal should be derived from from the incoming digital video data. Again, the the A = R1 comparator 168 output and R1 should effective data rate of the VRAM serial outputs is be programmed with the keying color. twice the serial shift clock (SC) frequency, due to 25 Several interesting effects can be obtained by the 2:1 interleaving. For output video data rates in using different outputs of the comparator 168. For excess of 50MHz, higher interleaving ratios or example, if the A < R1 output is used, all high- deeper buffer organizations are again required. resolution pixels having a value less than R1 are seen as video. By painting a graphics object with 30 concentric rings of increasing color value, interest- SERIALIZER 155 ing "growing" and shrinking" window effects can be achieved by dynamically varying the threshold The serializer 155, shown in FIG. 11, takes the value, R1. incoming serial data from the Video Buffer 145 along 2 parallel 12-bit paths, SDAT0 on line 156 35 and SDAT1 on line 157, and serializes them by a DIGITAL AUDIO CIRCUIT 400 multiplexor 158, shifting them out onto the high- speed Luminance-Chrominance output data bus This circuitry, shown in FIG. 13, serves as the (YCOUT) one 12-bit sample at a time by flip-flop audio Input/Output subsystem in the system. The 159. The YCOUT is clocked synchronously with the 40 incoming analog stereo audio (AINL 402 and AINR host's high resolution display dot clock (HRCK). In 404) signals to input gain and balance control cir- the present embodiment, it is clocked using the cuit 406 are first gain and balance adjusted appro- same signal. This clock frequency can be in- priately and are subsequently low-pass prefiltered, creased by some fractional amount while remaining so that they contain no frequency content above synchronous with HRCK using conventional phase- 45 the Nyquist Frequency. The gain and balance can locked loop techniques. This may be necessary, be controlled by the host computer 300 via the 2- for example, to correct the aspect ratio of the video, bit serial data bus 408 (SCAUD). image on the high-resolution screen. There is also Once the signals have been conditioned, they a high-resolution blanking signal (HRB-), which is must be multiplexed onto a common wire by a used to force the YCOUT data to 0 (black) and also 50 multiplexor 410, in order to avoid the need for two to delay the start of clocking data out of the Video separate Analog-to-Digital (A/D) convertors. Every Buffer's serial ports (via SC) from gate 160 as other audio sample written into the video buffer controlled by flip-flop 161, until the active portion of comes from alternating channels of the incoming the high-resolution scanline starts. audio source. This toggling is performed via the 55 L/R signal 412 generated by the sync generator 105. The sync generator 105 also generates the COLOR KEY 165 basic timing pulses for the audio conversion pro- cesses. When the digital audio data is being re- 17 EP 0 384 257 A2 18 corded, (AUDDIR = 0) on line 414, the timing pulses accommodated. This digitized video is then pro- (AREQ) on line 416 are applied only to the A/D cessed by a Digital Multi-Standard Decoder converter 418 via gate 420. Similarly, if AUDDIR = 1 (DMSD) 206, driving a 12-bit digital (playback mode) on line 414, AREQ on line 416 are Luminance/Chrominance Input Bus (YCIN) 208 at only be applied to the Digital-to-Analog convertor 5 the TV data rate (TVCK). It is the DMSD 206 that (DAC) 422 via gate 424. Each time one of the interprets the variety of input video formats and convenors 418 or 422 receives a convert pulse, it decodes them appropriately. Various parameters of provides one sample of audio (A/D), or take one the decoder can be adjusted via the serial control sample and convert it to analog (DAC). These bus I2C. audio samples are read from or written to off- m A Sync Separator circuit 210 simply extracts screen regions of the Video Buffer by the memory Sync and Clock information from the currently se- controller. lected video input and provides this information The DAC used in this system is actually a dual (TVVS-, TVHS-.TVCK) to the rest of the system. channel DAC, taking a single digital input and pro- viding two analog outputs. The two output voltages 75 are updated on every other DAC conversion cycle, DIGITAL TV OUTPUT CIRCUIT 500 in a similar manner to the A/D. After the DAC, there is once again analog audio, which must be pro- This circuit, shown in FIG. 15, converts the cessed through a reconstruction filter 426 in order high-speed Luminance/Chrominance Bus (YCOUT) to remove unwanted artifacts of the sampling pro- 20 information on line 502 back to analog RGB form cess (i.e. quantization noise). This reconstruction by a convertor 504 and video Y and C to RGB filter has a cutoff frequency identical to that of the matrix 506, and multiplexes it in a multiplexer 508 input filter. The cutoff frequency is controlled by with RGB signals 510 from the host's high-resolu- the frequency of the FCK signal from the Sync tion graphics controller, under control of the KEY Generator 105. Thus, a range of sample rates 25 signals on line 511. (hence cutoff frequencies) can be accommodated. The Y/C to RGB Matrix 506 is a purely analog Finally, there is an output amplifier 428, to restore component which converts the analog Y/C repre- the signals to a level sufficient to drive an audio sentation to RGB using a standard conversion ma- pre-amp or headphones. trix. Various adjustments to the output video An interesting additional feature of this circuit is 30 (Saturation, Contrast, and Brightness) can be made the ability to monitor the digital audio through the by the host via the serial control bus I2C. DAC as it is being recorded from the A/D. This can Finally, the Video Multiplexor 508 selects be- be done by driving both the A/D and DAC convert tween the RGB-converted video and the RGB from pulses simultaneously, which requires an obvious the high-resolution display controller, on a pixel by change in the logic shown in FIG. 13. This feature 35 pixel basis. This selection is done under control of is a result of the fact that the A/D and DAC share a the KEY signal on line 511 generated by the Color common data bus (ADAT). Key circuit of FIG. 12. The output 512 of the multiplexor 508 directly drives the high-resolution display 600. DIGITAL TV INPUT CIRCUIT 200 40

FIG. 14 shows a typical system for providing Claims the digital video input processed by the rest of the system. The video input can be selected by a 1. In a high resolution display system, the video source select logic 202 from one of several 45 combination comprising: sources under host control through the use of a I2C a high resolution monitor (600); serial control bus. (This bus is standard for control a computer (300) for providing control signals, in- Philips chips and described in Signetics/Philips cluding a high resolution frame buffer (760) for data books as previously referenced). In addition, storing computer graphics images pel by pel, and these sources can be any of a variety of formats 50 reading out said graphics images on a pel by pel including PAL, NTSC, SECAM, SVHS.RGB, etc. basis at a rate controlled by said control signals; This is a virtue of the digital television approach, a TV video controller (100), including a TV frame since these devices have been designed with that buffer which stores TV video at TV speeds and flexibility in mind. After a source is selected, it is reads out TV video on a pel by pel basis at a rate digitized using a conventional video A/D convertor 55 controlled by said control signals from said com- 204. An 8 bit digital output is shown, but again, this puter; and is not a fundamental limitation, and higher resolu- a switching mechanism (500) controlled by said tions provided by future systems can be readily control signals from said computer for selectively

10 19 EP 0 384 257 A2 20 switching between said high resolution frame buffer signals, and video graphics signals; and said TV frame buffer on a pel by pel basis to an input device (200) for receiving standard analog read out said buffers to display the read out video TV signals and converting them to standard digital on said high resolution monitor. TV signals; 2. In a high resolution video display system, 5 a display controller (100) which operates under the combination comprising: control of said control signals from said computer, a high resolution display (600); said display controller including a two port display a computer system (300) for generating control frame buffer, with one of said standard digital TV signals, and including a high resolution frame buff- signal and said video graphics signal being read er (760) for storing video graphics pel by pel for w into the first port at a first rate, and being read out display on said high resolution display, including of the second port pel by pel at a second rate means for converting the video graphics to an controlled by said control signals from said com- analog high resolution graphics signal; puter; and an input device (200) for receiving standard analog an output device (500) including a digital to analog TV signals and converting them to standard digital 75 converter for converting the signal read out of the TV signals; second port of said display frame buffer to an a display controller (100) which operates under analog display signal, for display on said high control of said control signals from said computer, resolution display. said display controller including a two port TV 6. In a high resolution video display system, frame buffer, with said standard digital TV signal 20 the combination comprising: being read into the first port at a TV rate, for a high resolution display; storage, and being read out of the second port on a computer system for generating control signals, a pel by pel basis at a higher speed rate controlled video graphics signals, and digitized audio signals; by said control signals from said computer; and an input device for receiving standard analog TV an output device (500) including a digital to analog 25 signals and converting them to standard digital TV converter (504) for converting the standard digital signals; TV signal read out of the second port to an analog a display controller which operates under control of TV signal, and further including means (508) for said control signals from said computer, said dis- selecting a pel at a time one of said analog high play controller including a display frame buffer resolution graphics signal and said analog TV sig- 30 which includes an on screen portion and an off nal for display on said high resolution display. screen portion, with said standard digital TV signal 3. The combination claimed in claim 1 or 2, and said video graphics signal being read for stor- wherein said display controller includes: age in predetermined locations in said on screen a sync generator (105) responsive to a TV clock portion of said display frame buffer, with said signal, horizontal sync signal and vertical signal 35 digitized audio signals being read for storage in portion of said standard digital TV signal to provide said off screen portion of said display frame buffer, a TV sync signal for reading the data portion of and each being read out in response to said control said standard TV signal into said first port of said signals from said computer; TV frame buffer; and an audio circuit responsive to the digitized audio a serializer (155) operating under control of said 40 signals read out of said display frame buffer, in- control signals from said computer for reading out cluding means for converting the digitized audio to the digital TV data from said second port of said analog audio; and TV frame buffer on a pel by pel basis to provide an output device including a digital to analog con- serial TV data at a high resolution rate; and verter for converting the standard TV signal and the a select network (508) responsive to said control 45 video graphics signals read out of said TV frame signals from said computer for providing a key buffer to an analog TV signal, for display on said signal which when in a first state selects said TV high resolution display. video for display and when in a second state 7. The combination claimed in claim 5 or 6, selects said high resolution graphics video for dis- wherein said frame buffer stores said standard TV play. so signal and said video graphics signal as scanlines, 4. The combination claimed in claim 3, wherein with each scanline being read out twice before the said means for selecting in said output device following scanline is read out. comprises a multiplexer (508) which bases its se- 8. The combination claimed in claim 5, 6 or 7, lection in response to said key signal. including means for reading out said frame buffer 5. In a high resolution video display system, 55 pel by pel such that the image on said high resolu- the combination comprising: tion display comprises either the standard TV sig- a high resolution display (600); nal with at least one window image of video graph- a computer system (300) for generating control ics, or the video graphics with at least one window

11 21 EP 0 384 257 A2 22 image of the TV signal. display data at a high resolution rate to said output 9. The combination claimed in claim 5, 6, 7 or device. 8, wherein said computer system includes: 12. The combination claimed in claim 10 or 11, a high resolution frame buffer (760) for storing wherein said data buffer stores data in the on video graphics, including means for reading out 5 screen portion as scanlines, with each scanline said video graphics at a rate controlled by said being read out twice before the following scanline control signals; and is read out. means for converting the video graphics to an 13. The combination claimed in claim 10, 11 or analog high resolution graphics signal; and 12, including means for reading out said data buff- wherein said output device includes: w er such that the image displayed on said high means for selecting one of said analog high resolu- resolution display comprises either the standard TV tion graphics signal and said analog display signal signals with at least one window image of graphics for display on said high resolution display. data or the graphics data with at least one window 10. In a high resolution video display system, image of the TV signal. the combination comprising: 75 14. The combination claimed in claim 10, 11, a high resolution display; 12 or 13, wherein said computer system includes: a computer system for generating computer control a high resolution frame buffer for storing video signals, and computer data signals which include graphics, including means for reading out said vid- graphics data signals, and digitized audio data sig- eo graphics at a rate controlled by said computer nals; 20 system; an input device for receiving standard analog TV means for converting the video graphics to an signals and converting them to standard digital TV analog high resolution graphics signal; signals; wherein said output device includes: a display controller which operates under control of means for selecting one of said analog high resolu- said computer control signals from said computer, 25 tion graphics signal and said analog display signal said display controller including a two port data for display on said high resolution display. buffer which includes an on screen portion and an 15. In a high resolution video display system, off screen portion, with said standard digital TV the combination comprising: signal and said computer data signals being read a high resolution display; into the first port for storage of the digital TV signal 30 a computer system for generating control signals, and the graphics data signals in predetermined video graphics signals, and first digitized audio locations in said on screen portion of said data signals; buffer, and for storage of said digitized audio data an input device for receiving standard analog TV signals in said off screen portion of said data signals and converting them to standard digital TV buffer, with said digitized audio data signals being 35 signals; read out of said first port under control of said a display controller which operates under control of computer control signals and said digital TV signal said control signals from said computer, said dis- and the graphics data signals being read out of the play controller including a display frame buffer second port at a speed controlled by said com- which includes an on screen portion and an off puter control signals; 40 screen portion, with said standard digital TV signal an audio circuit responsive to the digitized audio and said video graphics signal being read for stor- data signals read out of the first port of said display age in predetermined locations in said on screen frame buffer, including means for converting the portion of said display frame buffer, with said first digitized audio data signals to analog audio; and digitized audio signals being read for storage in an output device including a digital to analog con- 45 said off screen portion of said display frame buffer, verter for converting the standard TV signal and the and each being read out in response to said control graphics data signals read out of the second port signals from said computer; of said data buffer to an analog display signal, for a source of analog audio signals; display on said high resolution display. an audio circuit including means for converting said 11. The combination claimed in claim 10, so analog audio signals to second digitized audio sig- wherein said display controller includes: nals to be read into the off screen portion of said a sync generator responsive to said standard digi- TV frame buffer for storage at predetermined loca- tal TV signal to provide a TV sync signal for tions, and being read out under control of said reading the data portion of said standard TV signal control signals and being responsive to either the into said first port of said data buffer; and 55 first digitized audio signals or the second digitized a serializer operating under control of said com- audio signals read out of said display frame buffer, puter control signals, for reading out display data including means for converting the digitized audio from said second port of said data buffer to provide to analog audio; and

12 23 EP 0 384 257 A2 24 an output device including a digital to analog con- analog audio signals to second digitized audio sig- verter for converting the standard TV signal and the nals to be read into the first port of said data buffer video graphics read out of said TV frame buffer to for storage at predetermined locations of said off an analog TV signal, for display on said high reso- screen portion, and being read out of said first port lution display. s under control of said control signals and being 16. The combination claimed in claim 15, responsive to either the first digitized audio data wherein said frame buffer stores said standard TV signals or the second digitized audio signals read signal and said video graphics signal as scanlines, out of the first port of said display frame buffer, with each scanline being read out twice before the including means for converting the digitized audio following scanline is read out. ?o signals read out of said first port to analog audio; 17. The combination claimed in claim 15 or 16, and including means for reading out said frame buffer an output device including a digital to analog con- such that the image on said high resolution display verter for converting the standard TV signal and the comprises either the standard TV signal with at graphics data signals read out of the second port least one window image of video graphics, or the rs of said data buffer to an analog display signal, for video graphics with at least one window image of display on said high resolution display. the TV signal. 18. The combination claimed in claim 15, 16, or 17, wherein said computer system includes: a high resolution frame buffer for storing video 20 graphics, including means for reading out said vid- eo graphics at a rate controlled by said control signals; and means for converting the video graphics to an analog high resolution graphics signal; and 25 wherein said output device includes: means for selecting one of said analog high resolu- tion graphics signal and said analog display signal for display on said high resolution display. 19. In a high resolution video display system, 30 the combination comprising: a high resolution display; a computer system for generating computer control signals, and computer data signals which include graphics data signals, and first digitized audio data 35 signals; an input device for receiving standard analog TV signals and converting them to standard digital TV signals; a display controller which operates under control of 40 said computer control signals from said computer, said display controller including a two port data buffer which includes an on screen portion and an off screen portion, with said standard digital TV signal and said computer data signals being read 45 into the first port for storage of the digital TV signal and the graphics data signals in predetermined locations in said on screen portion of said data buffer, and for storage of said first digitized audio data signals in said off screen portion of said data so buffer, with said first digitized audio data signals being read out of said first port under control of said computer control signals and said digital TV signal and the graphics data signal being read out of the second port at a speed controlled by said 55 computer control signals; a source of analog audio signals; an audio circuit including means for converting said

13

EP 0 384 257 A2

FIG. 2

700 ) /

1

TO VGA MONITOR "RnDR nCk G nIB

TV RGB HI-RES RGB SWITCH

740

710 720 760

TV SPEED TV HI-RES DIGITAL FRAME BUFFER FRAME BUFFER TV VGA TV MODIFIED SPEED VLSI CHIP SET DISPLAY CONTROLLER CONTROLLER

730-^ 750

/ 1 770

NTSC PC BUS

EP 0 384 257 A2

FIG. 4

SYNC GENERATOR 105

PC DATA

fWs 107 108 » / " /

tTTuc RES — ^ — ^ S0URCE VCHTVUMI CONTROL , nki L0GIC KW TVCK (fig.5) , ^ ^ HCNT

106 .109

AREQ

Aiimn AUODIRr

TIMING -ACTL ^ LR LOGIC FCK EP 0 384 257 A2

FIG. 5

SOURCE CONTROL LOGIC 108

/"4 x no s I

I 1— R *

INX • HCNT " S SREQ

A ' r A(8 B N D ) 11j Nis

PCDATA

X/117 Y 112 S /

— 1 * R A

VCNT @• G -pp}

A 119 1 A(B — ' 1 I B

d L-rJ 113 V118

EP 0 384 257 A2

F I G. 7 FIFO H5

SREQ

^VIDBUS

FIG. 8

MEMORY CONTROLLER ANO ARBITER 125

AUDDIR ^p126 .. — SGNT ACTLi AREQ *-AGNT

arritfr s-PGNT WEC i

WEY_. PCCNTL-

-V8CTRL MOP MEMORY — * CONTROLLER TRQE

RDY DONE

MOP

EP 0 384 257 A2

FIG. 10

VIDEO BUFFER 145

12 V— @SDATO

/ — *-S0AT1

148 512 X 12 A * 1,024 X VIDBUS VIDEO BUFFER 6 1-m VIDEO RAM's / A /

i . n U h t k li '

'9

SC VBADDR

RAS CASO TR/QE CAS1 WEY WEC i i 1 VBCTRL V8CTRL EP 0 384 257 A2

FIG. 11 SERIALIZER 155

SOATO

*— YCOUT

SDAT1

FIG. 12 COLOR KEY 165

168 L q j gy HROAT + ^A COMP / »@ 169-h 1 A

A>R1 -SELECT

KEY R1- „ ^RO

170-

EP 0 384 257 A2

FIG. 14 0!GlTAL TV INPUT CIRCUITRY 200

202 204 206 T ) ) VIN1 — *- DIGITAL 208 V!DE0 V1DE0 8 MULTI- 12 uin9 -^-M VJN2r^ source -— . A/D @YCIN SELECT C0NVERT0R VIN3- DECODER >

^TVHS SYNC 2/ _ ___ SEPARATOR__TKK

I'C 210

FIG. 15 DIGITAL TV OUTPUT CIRCUITRY 500

51K KEY- B 50K 506 X A/B Y' VIOR- Y,C RA 502 VIDEO ) 12 YiC TO VIDG- VIDEO YCOUT GA RGB D/A MULTIPLEXOR C~ VIDB~ CONVERTORS MATRIX RB GB

HRR HRG HRB -510

I2C HRRGB