August 2018 TOPICS
• FPGAs at Intel • Fundamentals of Digital Electronics • FPGA Architecture • Intel® Quartus® Prime Design Software • FPGA Design Flow
Programmable Solutions Group 2 Companion Lab
1. Obtain an FPGA development kit
Search for “DE10-Lite”
2. Download the attached lab manual 3. Download Quartus Prime Lite
To improve download time, only select the device support that matches the device you are using.
4. Run installation while viewing training
Programmable Solutions Group 3 FIELD PROGRAMMABLE GATE ARRAY (FPGA)
• Flexible, multi-functional reprogrammable silicon • Custom hardware functionality • Bare-metal speed and reliability • Truly parallel in nature
ProgrammablePROGRAMMABLE Solutions SOLUTIONS Group GROUP | Intel® Confidential 4 Benefits of FPGA Technology
• Cost • Time to market • Performance • Reliability • Long-Term Maintenance
ProgrammablePROGRAMMABLE Solutions SOLUTIONS Group GROUP | Intel® Confidential Source: http://www.ni.com/white-paper/6984/en/ 5 The BIRTH OF FPGAS
High-density First EPROM; First EPLD; re- CPLD; full erased using programmable subsystems UV light EEPROM CMOS
1971 1983 1984 1988
1970 1975 1983 1985 1989
Altera launches first Integrated First PROM; First PLA; Altera First FPGA; graphic design programmable, limited to sum founded 64 logic blocks environment but permanent of products w/ two three- input LUTs
ProgrammablePROGRAMMABLE Solutions SOLUTIONS Group GROUP | Intel® ConfidentialSOURCE: https://www.altera.com/about/company/history.html 6 Intel’s deep history with fpgas
First First soft First System-in- embedded micro- embedded SoC FPGA Package Founded First PLD RAM processor DSP (SIP)
1983 1984 1995 2000 2002 2012 2016 // // 1968 1971 1984 1994 2013 2015
Intel is founded World’s first Intel and Altera Altera purchases Intel and Altera Intel by Robert microprocessor establish a joint Intel’s PLD start foundry acquires Noyce and marketing business relationship for Altera Gordon Moore agreement 14nm FPGAs and SoCs
ProgrammablePROGRAMMABLE Solutions SOLUTIONS Group GROUP | Intel® Confidential 7 THE RISE OF NEW MARKETS
ProgrammablePROGRAMMABLE Solutions SOLUTIONS Group GROUP | Intel® Confidential 8 Back to the BASICS S A B Z A B Z A B Z 0 0 0 0 0 0 0 0 0 0 0 0 1 0 A Z 0 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1 0 1 1 2:1 MUX Z = (~S & A) | (S & B) 1 1 0 0 1 1 1 1 Inverter OR AND Z = ~A Z = A | B Z = A & B
ProgrammablePROGRAMMABLE Solutions SOLUTIONS Group GROUP | Intel® Confidential 9 Look-Up Table (LUT): THE FOUNDATION
ProgrammablePROGRAMMABLE Solutions SOLUTIONS Group GROUP | Intel® Confidential 10 LOGIC ARRAY (Building) BLOCKS
x 10
ProgrammablePROGRAMMABLE Solutions SOLUTIONS Group GROUP | Intel® Confidential 11 Building the Array
LABs
Row interconnect
Column Segmented interconnect interconnects
ProgrammablePROGRAMMABLE Solutions SOLUTIONS Group GROUP | Intel® Confidential 12 How its Programmed
Row/Column Interconnect Junction
Programming info stored in a external non- volatile device
• Active: programmed automatically at power-on
• Passive: Intelligent host (CPU) controls programming
ProgrammablePROGRAMMABLE Solutions SOLUTIONS Group GROUP | Intel® Confidential 13 Modern FPGAs
ProgrammablePROGRAMMABLE Solutions SOLUTIONS Group GROUP | Intel® ConfidentialSource: https://www.altera.com/products/fpga/cyclone-series/cyclone-v/features.html 14 Describing Electronics .Schematics .Hardware Description Languages (HDLs) –Verilog, VHDL are most popular .Other high level languages –“C” –OpenCL Y = ~(~(~A | (A&B&C))); Z = (~(~A | (A&B&C))) & ((A&B&C) | ~C) & ~C); A Y
B Z
C
Programmable Solutions Group 15 What is IP? • Complex functions that Intel designs for our customers so they don’t have to design it themselves • Sometimes IP is free • The more complex stuff costs since its expensive to develop and make sure it works • Examples: Ethernet Controller, PCIe Controller, soft processor, multiplier functions, etc.
Programmable Solutions Group 16 Intro to Quartus
• Intel® Quartus® Prime Design Software is a tool for FPGA, SOC and CPLD design • Includes synthesis, debug, optimization, verification and simulation • Takes a description of an FPGA (schematic or HDL) and determines how the lookup tables are programmed
• Many formats to program an FPGA –In this class we will use a “.sof” file (SRAM object file) –The .sof file is “volatile” and needs to be reprogrammed every time the board is restarted
Programmable Solutions Group 17 Quartus User Interface
Quartus Prime Software Main Window . Project Navigator shows your project hierarchy, source files, design units, IP and design revisions in your Project Navigator project. Files Window . Tasks window shows the status of the design
and can be used to run or re-run parts of the IP Catalog design flow Tasks Window . Messages window outputs messages from each process of the run. . Files window has tabs for the report browser, Messages Window open design files and any other file opened by the user. . IP Catalog window is open by default and is used to generate IP functions that are to be used in your design.
Programmable Solutions Group 18 Tools Overview
Design Files EDA Analysis & Libraries
Elaboration MAP Functional Synthesis Simulation
Functional Fitter Netlist
Constraints & HW Debug tools settings - Programmer Assembler - SignalTap™ II logic analyzer - SignalProbe Programming & TimeQuest Configuration files Timing Analysis
Gate-Level EDA Netlist Writer Simulation
Post-Fit Simulation Files
Programmable Solutions Group 19 New Project Wizard
1. Name project 2. Set Working Directory & Top-Level Entity 3. Add source files 4. Select Device 5. EDA tool settings
All settings can be modified later. Some steps can be skipped. The top level entity must match the top level module in your design exactly (case sensitive) in order to avoid a compile error.
Programmable Solutions Group 20 Projects, Revisions, Files, Top Level Entity
Project: Lab (Project defines device, common settings)
Revision: Lab (shares settings) Revision: Lab2
Lab1a.v (code) Lab2a.v module lab1 ( … ) module lab1 ( … )
Lab1b.v Lab1b.v module sub1 ( … ) module sub1 ( … )
Top level entity
Programmable Solutions Group 21 DE10-Lite Development Kit – Only $55 !
Programmable Solutions Group 22 HINT: Family & Device Settings
Expand the window so you can see all the fields
Get the part number for your specific device by looking on the chip on your board or the side of the box.
Programmable Solutions Group 23 Pin Planner
Programmable Solutions Group 24 Compile YOUR DESIGN
Warnings shown in blue won’t prevent your design from compiling or being programmed, but they could indicate possible bugs. This lab does not have any design constraints, so the .sdc file is not needed. You will learn how to create one in the timing analysis workshop.
Programmable Solutions Group 25 PROGRAM YOUR FPGA
Programmable Solutions Group 26 TEST YOUR DESIGN
Programmable Solutions Group 27 Next Step: Multiplexer
Circuit Truth Symbol table
The multiplexer can be described by the following Verilog statement:
Programmable Solutions Group 28 KNIGHTRIDER
Programmable Solutions Group FINAL TIPS • When Quartus Prime Lite first starts for the very first time it might ask you about purchasing a license, select Run Quartus, all licenses are free for this lab. • Note that there are two development kits described in the Lab Manual. Be careful to refer to the appropriate development kit. • If things fail to compile, check your Top Level Entity Setting Setting Top Level Entity and make sure that the module
Programmable Solutions Group 30