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RF Power Amplifiers

May 7, 2003 RF IF

Outline

‹ PA Introduction z Power transfer characteristics z Intrinsic PA metrics z Linear and Non-linear amplifiers z PA Architectures ‹ Single-Stage Linear PA z Load-line theory z Transistors size z Input and Output Matching z So why is this so hard? ‹High-efficiency PAs z Class A, AB, B and C amplifiers

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Outline (cont.)

‹Real-World Design Example z Selecting architecture, number of stages z Designing stages z Tuning: inter-stage match and output ‹System specifications z Ruggedness: load mis-match and VSWR z Linearity: spectral mask (ACPR), switching transients z Noise in receive band ‹ Power Control

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PA Transfer characteristics Defining linearity:

linear non-linear (actual)

(dBm) 1

out G P Pout = Pin + G

0 Pin (dBm)

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PA Transfer characteristics Defining linearity:

PMAX P 1dB G -1 (dBm) out Gain (dB) P

Pin (dBm)

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PA Introduction: Intrinsic PA Metrics

‹ P1dB: Output power at which linear gain has compressed by 1dB (measure of linear power handling)

‹ PMAX: Maximum output power (saturated power) ‹ Gain: Generally taken to mean transducer gain Power delivered to load Power available from source

‹ PAE: Power-added Efficiency

Power to load – Power from source Power from supply

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Linear and Non-linear PAs

‹ “Linear PA” generally refers to a PA which operates at constant gain, needs to preserve amplitude information

(dBm) Designed to operate here OUT P

PIN (dBm)

‹ Not necessarily class A (will discuss later …) Peak efficiencies often only 40 to 45 % ‹ Useful for modulation schemes with amplitude modulation (QPSK, 8-PSK, QAM)

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Linear and Non-linear PAs

‹ “Non-linear PA” generally refers to a PA designed to operate

with constant PIN, output power varies by changing gain Designed to operate here: NOT fixed gain! (dBm) POUT adjusted through OUT P bias control

PIN (dBm)

‹ Operation in saturated mode leads to high peak efficiencies > 50%; “backed-off” efficiencies drop quickly ‹ Useful for constant-envelope modulation schemes (GMSK)

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PA Architectures Typical 2-stage (6.012) design

VPOS

50 Ω

IREF

input 50 Ω Max power transfer?

VB2 VB1

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PA Architectures Typical 2-stage RF PA design

VPOS

inductive RF choke allows output to rise

above VPOS, doesn’t dissipate power matching network matching RF input network 50 Ω

L’s and C’s to May require additional transform load RF choke here to isolate impedance input from bias circuit VB2 VB1

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PA Architectures Typical 2-stage RF PA design

VPOS

Additional caps may be required for matching network, harmonic termination matching network matching RF input network 50 Ω

VB2 VB1

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PA Architectures Typical 2-stage RF PA design

VPOS

matching network matching RF input network 50 Ω

bond wires (at least …)

VB2 VB1

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PA Architectures Typical 2-stage RF PA design

VPOS

matching network matching RF input network 50 Ω

VB2 VB1 Consider this …

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PA Architectures

‹ “Gain stage” is one transistor with passive elements ‹ “Active” components often limited to 2 or 3 transistors (gain stages) in signal path ‹ Transistor design very important! z Many parallel transistors – often look like mini-circuits themselves ‹ Passive components just as important as transistors! z Circuits must be tunable to account for uncertainties in determining values a priori (i.e. simulations stink – especially large-signal, RF simulations) z Q and parasitic elements of passives important

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Single-Stage Linear PA

‹ Load-line theory: the maximum power that a given transistor can deliver is determined by the power supply voltage and the maximum current of the transistor

≈ RLOAD,opt. IMAX ⋅ 2 VPOS / IMAX (mA/mm) C or I D I

2*VPOS

VDS or VCE (V) 15 RF IF

Single-Stage Linear PA

‹ Transistor size chosen to deliver required output power ≈ ⋅ POUT IMAX VPOS / 4

RL,opt. IMAX Quiescent point:

(mA/mm) Class A

C IMAX/2, VPOS or I D I

2*VPOS VDS or VCE (V)

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Single-Stage, Linear PA Ω ‹ Design output match to transform 50 load to RL,opt at transistor output; then design input match for gain (complex conjugate) VPOS output input match match

CJC 50 Ω

VB1

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Seems simple, so why is this so hard?

‹ Determining IMAX is not so easy z For BJTs, one reference suggested that “the best way of estimating its value is to build an optimized class A amplifier and observe the dc supply current.”1

z Somewhat easier for depletion-mode GaAs FETs – IMAX often corresponds to VGS = 0V z Values don’t scale linearly with transistor size ‹ Optimal load resistance only a theoretical number z Transmission line effects, parasitic L’s and C’s significant at RF z Common practice is to vary the load of an actual transistor to determine the peak output power: the load-pull measurement (Noticing a distinct pattern of “empirical” design emerging?)

1 RF Power Amplifiers for Wireless Communications, Steve Cripps, Artech House, Boston, 1999.

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Seems simple, so why is this so hard?

‹ Now consider the problem for multiple stages … double the trouble z Typical single-stage gain only 10 – 15 dB z Inter-stage match now required to match input impedance of 2nd stage to desired output impedance of 1st stage. ‹ Problems with matching circuits: z Large matching ratios → high Q circuits for simple L matches z Multi-segment matches use valuable real estate, add cost ‹ Transistor itself maters – a lot! z Many parallel transistor z Ballasting, balancing and layout extremely important

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High-efficiency PAs

‹ Input signal swing turns on transistor – conduction for only part of sinusoidal period

IMAX

(mA/mm) Class A C or I

D Quiescent point: I Class AB to B

VDS or VCE (V)

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High-Efficiency PAs Conduction Angle: C

Class A: or I α π

D = 2 I π 2π 3π ωt C

Class AB: or I α π α π

D < < 2 I π 2π 3π ωt C

Class B: or I α π

D = I π 2π 3π ωt Class C: α < π

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High-Efficiency PAs

‹ Assume output match will filter out non-linearities caused by discontinuous conduction:

output input match match

50 Ω

50Ω transformed

to RL,opt: V All harmonics B1 filtered out

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High-Efficiency PAs

‹ If all harmonics filtered out, then voltage output at load is a pure sinusoid, despite discontinuous conduction OUT V π 2π 3π ωt

IMAX C I

π 2π 3π ωt

‹ Energy stored in reactive elements delivers current to the load during transistor off-portion of cycle

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High-Efficiency PAs

‹ Now consider peak efficiencies Calculate fundamental component of current* α/2 π I + I cos(ωt) dωt Idc = (1/2 )∫ Q pk −α/2 α/2 π I cos(ωt) cos(nωt) dωt In = (1/ ) ∫ pk −α/2

IMAX − Ipk = IMAX IQ C I

IQ

2π ωt α/2 * There are many texts which cover reduced-conduction angle calculations. See for example Principles Of Power Electronics, Kassakian, Schelcht and Verghese, Ch. 3.

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High-Efficiency PAs α − − From phasor plot: cos( /2) = IQ / Ipk = IQ / (IMAX –IQ) Put it all together and do the math, you get:

I 2sin(α/2) – αcos(α/2) I = MAX dc 2π 1 – cos(α/2) I α – sinα I = MAX 1,0-p 2π 1 – cos(α/2)

Assume VOUT the same for all classes:

V1,0-p = VPOS

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High-Efficiency PAs

‹ Summary of PA “ideal” peak efficiencies

P (I /2) /√2 ⋅ V /√2 Class A: 1 ==MAX POS 50 % ⋅ Pdc (IMAX /2) VPOS P (I /2) /√2 ⋅ V /√2 Class B: 1 ==MAX POS 78 % π ⋅ Pdc (IMAX / ) VPOS

Class C: Ideally can go to 100%, but P1 drops steadily beyond α=π, goes to 0 at 100%!

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High-Efficiency PAs

‹ What happened to our load line?

z For class B fundamental RL,opt = VPOS/(IMAX/2) – Didn’t change

IMAX

(mA/mm) Class A C or I D

I ?

VPOS 2VPOS

Class B is here! VDS or VCE (V)

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High-Efficiency PAs

‹ What happened to our load line?

z For class B fundamental RL,opt = VPOS/(IMAX/2) – Didn’t change

quasi-static In quasi-static picture, resistance I MAX presented to

(mA/mm) Class A transistor output cut C I /2 in half. But average MAX resistance is the or I

D same for class A I

VPOS 2VPOS

Class B is here! VDS or VCE (V)

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High-Efficiency PAs

‹ Now consider “linearity” z Clearly the current waveforms are far from linear BUT …

z Overall POUT vs. PIN transfer function can still be quite linear, especially for true Class B where output current waveform is symmetrical with respect to input waveform C or I D I π 2π 3π ωt Because conduction angle is constant,

POUT changes proportional to PIN

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Real-World Design Example

‹ IDEAL: Design each stage independently z Determine required gain – number of stages

z Determine POUT for each stage

z Determine RL,opt for each stage z Determine input impedance for each stage z Design matching networks for inter-stage, load and input ‹ REALITY:

z IMAX doesn’t scale nicely with transistor size. Without good IMAX numbers, can’t determine RL,opt. Need to do load-pull. z Even load pull measurements have limited accuracy for very large transistors z Designs are very empirically driven!

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Real-World Design Example GSM 900 MHz, GaAs HBT PA Design

‹ POUT = 33 dBm (linear) = 2 W

VCC = 3.5V 2 Ω RLOAD = VCC / 2*POUT = 3

IMAX = 2*VCC /RLOAD = 2.33 A (Note: expect saturated power to be ~ 35 dBm) ‹ Input power: constant-envelope +5 dBm

‹ Gain = POUT –PIN = 27 dB. ‹ Expect roughly 10 dB per stage

3 STAGE DESIGN

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Real-World Design Example → ‹ Stage 1: Gain = 10 dB POUT = 15 dBm 2 Ω z RL1 = VCC / 2*POUT = 194

z IMAX = 2*VCC /RLOAD = 36 mA

z Chose class A: IDC = IMAX/2 = 18 mA (18 mA insignificant compared to 2.33 A) → ‹ Stage 2: Gain = 10 dB POUT = 25 dBm Ω z RL2 = 19.4

z IMAX = 360 mA

z Still probably class A (maybe AB): IDC = IMAX/2 = 180 mA → ‹ Stage 3: Gain = 7 dB POUT = 33 dBm Ω, z RL2 = 3 IMAX = 2.33 A π z Class B: IDC = IMAX/ = 742 mA

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Real-World Design Example A note on “Gain” ‹ Taking a very simplistic view of common emitter stages:

z gm1 = IC / VTh = 18 mA / 0.025 V = 0.696 S ⋅ → z gm1RL1 = 0.696 194 = 135 NOT 10 dB! BUT … Ω z re1 = 1/gm1 = 1.44 Ω z re2 = 1/gm2 = 0.144 Ω z re3 = 1/gm3 = 0.035

1. Remember it’s power gain, not voltage gain. Can lose voltage at input match. 2. It’s pretty tough not to get significant degeneration!

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Real-World Design Example

‹ Efficiency calculations:

z IDC1 = 18 mA, IDC2 = 180 mA, IDC3 = 742 mA z Total DC Current: 940 mA

P (I /2) /√2 ⋅ V /√2 1 ==MAX POS 62 % ⋅ Pdc IDC VPOS

z Realistically may get as high as 55%

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Real-World Design Example: Load-Pull

‹ After initial “guesses” at transistor sizes, load-pull to determine actual target load for matching circuits

Load pull: Vary ZL Plot contours of constant power RF input PMAX

P – 1dB ZL MAX

PMAX – 2dB

VB

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Real-World Design Example: Load-pull Notes on load-pulling: ‹ Most accurate on probe station, but insertion loss of probes prevents it from being useful for large transistors (“Insertion loss” is RF code word for resistance) ‹ Bonded devices on evaluation board must be carefully de- embedded ‹ Even using electronic tuners, accuracy is poor for very large transistor (i.e. for loads in the 2 – 5 Ω range)

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Real-World Design Example: The Circuit

VPOS

GaAs die

RF input 50 Ω

VB2 VB2 VB1

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Real-World Design Example: The Circuit

VPOS

Inter-stage match

RF input 50 Ω

VB2 VB2 VB1

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Real-World Design Example

VPOS

printed L inductor L BOND BOND + TL + TL LBOND RF input 50 Ω

Lparasitic + LVIA VB2 VB2 VB1

LBOND + LVIA 39 RF IF

Real-World Design Example

VPOS

may need to add feedback for stability

RF input 50 Ω

VB2 VB2 VB1

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Real-World Design Example: Tuning

‹ Example of inter-stage match, 1st to 2nd stage Ω RL1 = 194 (?) Both are really ZIN2 = 30 – j10 (?) just guesses

Transmission line

Bond wire

Z RL1 IN2

* Go to Winsmith: test

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Real-World Design Example: Tuning

‹ Example of inter-stage match, 2nd to 3rd stage Ω RL2 = 19.4

ZIN3 = 2 – j2

Transmission line

Bond wire Off-chip

R ZIN3 L2 Bond wires * Go to Winsmith: test2

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System Specifications

‹ Ruggedness z 50 Ω load is for antenna in free space. Place antenna on a metal plate and can easily get VSWR of 4:1 z Typical PA specs are: don’t oscillate at up to 4:1, survive up to 10:1 (!) − Γ⋅ + V1 = V1 + V1 V1 V1 t = t1 z − V1 t t = t2

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System Specifications

‹ Linearity z For linear PAs, Adjacent Channel Power Ratio (ACPR) is very important raised cosine filter

ch. ch. B ch. C A (dBm/Hz) Density (PSD) Power Spectral −∆ ∆ fc f fc fc+ f

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System Specifications

‹ Linearity z For linear PAs, Adjacent Channel Power Ratio (ACPR) is very important 3rd order distortion

ch. ch. B ch. C A (dBm/Hz) Density (PSD) Power Spectral −∆ ∆ fc f fc fc+ f

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System Specifications

‹ Linearity z For linear PAs, Adjacent Channel Power Ratio (ACPR) is very important

ch. ch. B ch. C A (dBm/Hz) th 5th order 3rd order 3rd order 5 order Density (PSD) Power Spectral distortion distortion distortion distortion −∆ ∆ fc f fc fc+ f

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System Specifications

‹ Linearity z For linear PAs, Adjacent Channel Power Ratio (ACPR) is very important ∆f 30 kHz Pwr. Ch. B ACPR = Pwr. Ch. A (dBm/Hz) Density (PSD) Power Spectral −∆ ∆ fc f fc fc+ f

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System Specifications

‹ Linearity z For non-linear PA in TDMA systems, harmonic spurs and switching transients are most common measure of linearity

Signal ramping µ profile must fall (dBm) 577 s within time mask GSM burst OUT P time

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System Specifications

‹ Noise in receive band: z Obvious spec. in systems where Tx and Rx are operating at the same time (FDD)

30 kHz 30 kHz

45 MHz (dBm/Hz) Density (PSD) Power Spectral Tx Rx

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System Specifications

‹ Noise in receive band: z Obvious spec. in systems where Tx and Rx are operating at the same time (FDD) z Not so obvious spec in TDD system. Problem primarily of ω ω ω ω mixing by the PA (2 2 – 1 or 2 – 1 )

45 MHz (dBm/Hz) Density (PSD) Power Spectral Tx Rx

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Power Control

‹ For linear PA, expected to operate at constant gain. Power

control is therefore a function of PIN.

‹ Role of bias circuitry is to maintain constant gain over PIN, temperature (PTAT?).

Power transistor

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Power Control

‹ For non-linear PA, expected to operate at constant PIN. Power control is achieved by varying gain.

External control signal VAPC

On-chip bias circuitry Power transistor

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