Jitter vs SNR for ADCs TIPL 4704
Created by Thomas Neu Presented by Thomas Neu
1 Sampling Theory
High-speed ADC uses external clock Higher input frequencies are more input to sample the analog input signal. susceptible to timing uncertainty Sampling Clock Jitter
Sampling jitter is combination of: 2 2 TJitter TJitter,ext TAperture _ ADC • External jitter • Internal ADC aperture jitter
ADC Aperture Jitter Clock amplitude dependent SNR Impact of Jitter (1)
The ADC SNR degradation due to jitter (external + internal ADC aperture) can be calculated as:
SNRJitterdBc 20log(2 fin TJitter)
110 0.05 ps 0.1 ps 100 0.2 ps 0.4ps
90
80 SNR (dBc) SNR 70
60
50 10 100 1000 Fin (MHz) SNR Impact of Jitter (2)
The ADC noise floor (SNR) is basically set by 3 different contributors: 1. ADC Quantization Noise 2 2 2 SNR SNR SNR Quantizatoin Noise Thermal Noise Jitter 2. ADC Thermal Noise 20 20 20 SNRADC dBc 20 log 10 10 10 3. Jitter degradation
100
90
80
SNR (dBc) 70
60
50 10 100 1000 Fin (MHz) Calculating the jitter magnitude (1)
The clock jitter is calculated by integrating the phase noise of the clock signal.
Clock Frequency = 122.88MHz Lower integration limit: 0 60Hz to 40MHz Typically application specific. -20 Tj = 350fs -40 500Hz to 40MHz -60 Tj = 50fs
-80
-100
-120
-140
-160
-180 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 Offset Frequency (Hz) Calculating the jitter magnitude (2) Clock Frequency = 122.88MHz
Upper integration limit: The upper limit is set by factors like • Clock filter bandwidth • ADC clock input bandwidth • ADC sampling rate
ADS54RF63 @ Fin = 1GHz, Fs = 122.88Msps with added noise on clock input
0 No LPF 300MHz LPF -20 100MHz LPF 1MHz LPF -40
-60
-80
-100
-120 0 102030405060 SNR impact in frequency domain
During the sampling process the clock signal phase noise gets added to the input signal.
• The higher the input signal the larger the phase noise amplitude (scales by 20log (FIN/FS)) • The larger (worse) the clock phase noise, the worse the ADC noise floor degradation
Input signal Clock jitter (phase noise)
ADC thermal noise
Higher input frequency & larger jitter amount Why is clock jitter/phase noise so critical?
A typical receiver use case is performance in a ‘blocking condition’ • The receiver needs to detect a small wanted signal • There is a large in-band interferer that can’t be filtered out.
Wanted Signal Interferer
Clock Phase Noise
ADC thermal noise How to maximize the jitter performance?
There are several steps the system designer can take in order to maximize the SNR performance of a given ADC: • Use low jitter/phase noise clock source • Use bandpass filter with low insertion loss to limit broad band noise degradation • Ensure clock amplitude is sufficient and doesn’t degrade ADC aperture jitter © Copyright 2017 Texas Instruments Incorporated. All rights reserved.
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