COP880C

COP880C

Literature Number: SNOS568B O80 Microcontrollers COP880C

August 1996

COP880C Microcontrollers General Description n High current outputs (8 pins) n Schmitt trigger inputs on Port G The following part numbers are pin count and tempera- n MICROWIRE PLUS serial I/O ture variations of the COP880C: COP680C/COP681C/ COP682C/COP881C /COP882C/COP980C/ n Packages: COP981C/COP982C. — 20 DIP/SO with 16 I/O pins — 28 DIP/SO with 24 I/O pins The COP880C devices are members of the COP8 microcon- — 40 DIP, 36 I/O pins troller family. They are fully static parts, fabricated using — 44 PLCC, 36 I/O pins double-metal silicon gate microCMOS technology. This low cost is a complete containing all system timing, interrupt logic, ROM, RAM, and I/O nec- CPU/Instruction Set Features essary to implement dedicated control functions in a variety n 1 µs instruction cycle time of applications. Features include an 8-bit memory mapped n Three multi-source interrupts servicing architecture, MICROWIRE/PLUS™ serial I/O, a 16-bit timer/ — External interrupt with selectable edge counter with capture register and a multi-sourced interrupt. — Timer interrupt Each I/O pin has software selectable options to adapt the — Software interrupt device to the specific application. The part operates over a n Versatile and easy to use instruction set voltage range of 2.5 to 6.0V. High throughput is achieved n 8-bit Stack Pointer (SP) — stack in RAM with an efficient, regular instruction set operating at a 1 n Two 8-bit Register Indirect Data Memory Pointers microsecond per instruction rate. (B and X) Key Features Fully Static CMOS n — 16-bit multi-function timer supporting n Low current drain (typically < 1 µA) — PWM mode n Single supply operation: 2.5V to 6.0V — External event counter mode — Input capture mode n Temperature ranges: 0˚ to 70˚C, −40˚C to +85˚C, −55˚C to +125˚C. n 4 kbytes of ROM n 128 bytes of RAM Development Support I/O Features n Emulation and OTP devices n Real time emulation and full program debug offered by n Memory mapped I/O MetaLink’s development system n Software selectable I/O options (TRI-STATE®, Push-Pull, Weak Pull-Up Input, High Impedance Input)

TRI-STATE® is a registered trademark of National Semiconductor Corporation. COPS™, HPC™, MICROWIRE™ and MICROWIRE/PLUS™ are trademarks of National Semiconductor Corporation. iceMASTER™ is a trademark of MetaLink Corporation. PC-XT® and PC-AT® are registered trademarks of International Business Machines Corporation.

© 2001 National Semiconductor Corporation DS010802 www.national.com Block Diagram COP880C

DS010802-1 FIGURE 1.

www.national.com 2 COP880C Connection Diagrams

Dual-In-Line Package Dual-In-Line Package (N) and 28 Wide SO (WM)

DS010802-23 Top View Order Number COP882C-XXX/N, COP982C-XXX/N, COP882C-XXX/WM, COP982C-XXX/WM, DS010802-5 COP982C-XXX/N or COP982CH-XXX/WM Top View Order Number COP881C-XXX/N, COP981C-XXX/N, COP881C-XXX/WM, COP981C-XXX/WM, COP981CH-XXX/N or COP981CH-XXX/WM Dual-In-Line Package Plastic Chip Carrier

DS010802-3 DS010802-4 Top View Top View Order Number COP680C-XXX/V, COP880C-XXX/V, Order Number COP680C-XXX/N, COP880C-XXX/N, COP980C-XXX/V or COP980CH-XXX/V COP980C-XXX/N or COP980CH-XXX/N FIGURE 2. Connection Diagrams

3 www.national.com COP980C/COP981C/COP982C

Absolute Maximum Ratings (Note 1) Total Current into VCC Pin (Source) 50 mA COP880C If Military/Aerospace specified devices are required, Total Current out of GND Pin (Sink) 60 mA please contact the National Semiconductor Sales Office/ Storage Temperature Range −65˚C to +140˚C Distributors for availability and specifications. Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured Supply Voltage (VCC)7Vwhen operating the device at absolute maximum ratings.

Voltage at any Pin −0.3V to VCC + 0.3V

DC Electrical Characteristics ≤ ≤ COP98xC; 0˚C TA +70˚C unless otherwise specified Parameter Condition Min Typ Max Units Operating Voltage 98XC 2.3 4.0 V 98XCH 4.0 6.0 V

Power Supply Ripple (Note 2) Peak to Peak 0.1 VCC V Supply Current

CKI = 10 MHz VCC = 6V, tc = 1 µs 6.0 mA

CKI = 4 MHz VCC = 6V, tc = 2.5 µs 4.4 mA

CKI = 4 MHz VCC = 4.0V, tc = 2.5 µs 2.2 mA

CKI = 1 MHz VCC = 4.0V, tc = 10 µs 1.4 mA (Note 3)

HALT Current VCC = 6V, CKI = 0 MHz <0.7 8 µA

(Note 4) VCC = 4.0V, CKI = 0 MHz <0.4 5 µA Input Levels RESET, CKI

Logic High 0.9 VCC V

Logic Low 0.1 VCC V All Other Inputs

Logic High 0.7 VCC V

Logic Low 0.2 VCC V

Hi-Z Input Leakage VCC = 6.0V −1.0 +1.0 µA

Input Pullup Current VCC = 6.0V, VIN = 0V −40 −250 µA

G Port Input Hysteresis 0.35 VCC V Output Current Levels D Outputs

Source VCC = 4.5V, VOH = 3.8V −0.4 mA

VCC = 2.3V, VOH = 1.6V −0.2 mA

Sink VCC = 4.5V, VOL = 1.0V 10 mA

VCC = 2.3V, VOL = 0.4V 2 mA All Others

Source (Weak Pull-Up) VCC = 4.5V, VOH = 3.2V −10 −110 µA

VCC = 2.3V, VOH = 1.6V −2.5 −33 µA

Source (Push-Pull Mode) VCC = 4.5V, VOH = 3.8V −0.4 mA

VCC = 2.3V, VOH = 1.6V −0.2

Sink (Push-Pull Mode) VCC = 4.5V, VOL = 0.4V 1.6 mA

VCC = 2.3V, VOL = 0.4V 0.7

TRI-STATE Leakage VCC = 6.0V −1.0 +1.0 µA Allowable Sink/Source Current Per Pin D Outputs (Sink) 15 mA All Others 3mA

www.national.com 4 COP880C

DC Electrical Characteristics (Continued) ≤ ≤ COP98xC; 0˚C TA +70˚C unless otherwise specified Parameter Condition Min Typ Max Units Maximum Input Current (Note 5) Without Latchup (Room Temp) Room Temp ±100 mA RAM Retention Voltage, Vr 500 ns Rise and (Note 6) Fall Time (Min) 2.0 V Input Capacitance 7pF Load Capacitance on D2 1000 pF COP980C/COP981C/COP982C Note 2: Rate of voltage change must be less than 0.5V/ms. Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.

Note 4: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to VCC, L, C and G ports TRI-STATE and tied to ground, all outputs low and tied to ground.

Note 5: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCC and the pins will have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typ). These two pins will not latch up. The voltage at the pins must be limited to less than 14V. Note 6: To maintain RAM integrity, the voltage must not be dropped or raised instantaneously. AC Electrical Characteristics ≤ ≤ 0˚C TA +70˚C unless otherwise specified Parameter Condition Min Typ Max Units Instruction Cycle Time (tc) ≥ Crystal/Resonator or External VCC 4.0V 1 DC µs ≤ ≤ (Div-by 10) 2.3V VCC 4.0V 2.5 DC µs ≥ R/C Oscillator Mode VCC 4.0V 3 DC µs ≤ ≤ (Div-by 10) 2.3V VCC 4.0V 7.5 DC µs CKI Clock Duty Cycle (Note 7) fr = Max 40 60 % Rise Time (Note 7) fr = 10 MHz Ext Clock 12 ns Fall Time (Note 7) fr = 10 MHz Ext Clock 8 ns Inputs ≥ tSETUP VCC 4.0V 200 ns ≤ ≤ 2.3V VCC 4.0V 500 ns ≥ tHOLD VCC 4.0V 60 ns ≤ ≤ 2.3V VCC 4.0V 150 ns Ω Output Propagation Delay CL = 100 pF, RL = 2.2 k tPD1,tPD0 ≥ SO, SK VCC 4.0V 0.7 µs ≤ ≤ 2.3V VCC 4.0V 1.75 µs ≥ All Others VCC 4.0V 1 µs ≤ ≤ 2.3V VCC 4.0V 2.5 µs

MICROWIRE™ Setup Time (tUWS) 20 ns

MICROWIRE Hold Time (tUWH) 56 ns MICROWIRE Output

Propagation Delay (tUPD) 220 ns Input Pulse Width

Interrupt Input High Time tC

Interrupt Input Low Time tC

Timer Input High Time tC

Timer Input Low Time tC Reset Pulse Width 1.0 µs

Note 7: Parameter characterized but not production tested.

5 www.national.com COP880C/COP881C/COP882C

Absolute Maximum Ratings (Note 8) Total Current into VCC Pin (Source) 50 mA COP880C If Military/Aerospace specified devices are required, Total Current out of GND Pin (Sink) 60 mA please contact the National Semiconductor Sales Office/ Storage Temperature Range −65˚C to +140˚C Distributors for availability and specifications. Note 8: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured Supply Voltage (VCC)7Vwhen operating the device at absolute maximum ratings.

Voltage at any Pin −0.3V to VCC + 0.3V

DC Electrical Characteristics ≤ ≤ COP88xC; −40˚C TA +85˚C unless otherwise specified Parameter Condition Min Typ Max Units Operating Voltage 2.5 6.0 V

Power Supply Ripple (Note 9) Peak to Peak 0.1 VCC V Supply Current

CKI = 10 MHz VCC = 6V, tc = 1 µs 6.0 mA

CKI = 4 MHz VCC = 6V, tc = 2.5 µs 4.4 mA

CKI = 4 MHz VCC = 4.0V, tc = 2.5 µs 2.2 mA

CKI = 1 MHz VCC = 4.0V, tc = 10 µs 1.4 mA (Note 10)

HALT Current VCC = 6V, CKI = 0 MHz <110µA

(Note 11) VCC = 3.5V, CKI = 0 MHz <0.5 6 µA Input Levels RESET, CKI

Logic High 0.9 VCC V

Logic Low 0.1 VCC V All Other Inputs

Logic High 0.7 VCC V

Logic Low 0.2 VCC V

Hi-Z Input Leakage VCC = 6.0V −2 +2 µA

Input Pullup Current VCC = 6.0V, VIN = 0V −40 −250 µA

G Port Input Hysteresis 0.35 VCC V Output Current Levels D Outputs

Source VCC = 4.5V, VOH = 3.8V −0.4 mA

VCC = 2.5V, VOH = 1.8V −0.2 mA

Sink VCC = 4.5V, VOL = 1.0V 10 mA

VCC = 2.5V, VOL = 0.4V 2 mA All Others

Source (Weak Pull-Up) VCC = 4.5V, VOH = 3.2V −10 −110 µA

VCC = 2.5V, VOH = 1.8V −2.5 −33 µA

Source (Push-Pull Mode) VCC = 4.5V, VOH = 3.8V −0.4 mA

VCC = 2.5V, VOH = 1.8V −0.2

Sink (Push-Pull Mode) VCC = 4.5V, VOL = 0.4V 1.6 mA

VCC = 2.5V, VOL = 0.4V 0.7

TRI-STATE Leakage VCC = 6.0V −2.0 +2.0 µA Allowable Sink/Source Current Per Pin D Outputs (Sink) 15 mA All Others 3mA Maximum Input Current (Note 12) Without Latchup (Room Temp) Room Temp ±100 mA

www.national.com 6 COP880C

DC Electrical Characteristics (Continued) ≤ ≤ COP88xC; −40˚C TA +85˚C unless otherwise specified Parameter Condition Min Typ Max Units RAM Retention Voltage, Vr 500 ns Rise and (Note 13) Fall Time (Min) 2.0 V Input Capacitance 7pF Load Capacitance on D2 1000 pF COP880C/COP881C/COP882C Note 9: Rate of voltage change must be less than 0.5V/ms. Note 10: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.

Note 11: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to VCC, L, C and G ports TRI-STATE and tied to ground, all outputs low and tied to ground.

Note 12: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCC and the pins will have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typ). These two pins will not latch up. The voltage at the pins must be limited to less than 14V. Note 13: To maintain RAM integrity, the voltage must not be dropped or raised instantaneously. AC Electrical Characteristics ≤ ≤ −40˚C TA +85˚C unless otherwise specified Parameter Condition Min Typ Max Units Instruction Cycle Time (tc) ≥ Crystal/Resonator or External VCC 4.5V 1 DC µs ≤ (Div-by 10) 2.5V VCC < 4.5V 2.5 DC µs ≥ R/C Oscillator Mode VCC 4.5V 3 DC µs ≤ (Div-by 10) 2.5V VCC < 4.5V 7.5 DC µs CKI Clock Duty Cycle (Note 14) fr = Max 40 60 % Rise Time (Note 14) fr = 10 MHz Ext Clock 12 ns Fall Time (Note 14) fr = 10 MHz Ext Clock 8 ns Inputs ≥ tSETUP VCC 4.5V 200 ns ≤ 2.5V VCC < 4.5V 500 ns ≥ tHOLD VCC 4.5V 60 ns ≤ 2.5V VCC < 4.5V 150 ns Ω Output Propagation Delay CL = 100 pF, RL = 2.2 k tPD1,tPD0 ≥ SO, SK VCC 4.5V 0.7 µs ≤ 2.5V VCC < 4.5V 1.75 µs ≥ All Others VCC 4.5V 1 µs ≤ 2.5V VCC < 4.5V 2.5 µs

MICROWIRE Setup Time (tUWS) 20 ns

MICROWIRE Hold Time (tUWH) 56 ns MICROWIRE Output

Propagation Delay (tUPD) 220 ns Input Pulse Width

Interrupt Input High Time tC

Interrupt Input Low Time tC

Timer Input High Time tC

Timer Input Low Time tC Reset Pulse Width 1.0 µs

Note 14: Parameter characterized but not production tested.

7 www.national.com Timing Diagram COP880C

DS010802-2 FIGURE 3. MICROWIRE/PLUS Timing COP680C/COP681C/COP682C

Absolute Maximum Ratings (Note 16) Total Current into VCC Pin (Source) 40 mA If Military/Aerospace specified devices are required, Total Current Out of GND Pin (Sink) 48 mA please contact the National Semiconductor Sales Office/ Storage Temperature Range −65˚C to +140˚C Distributors for availability and specifications. Note 15: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured Supply Voltage (VCC)6Vwhen operating the device at absolute maximum ratings.

Voltage at Any Pin −0.3V to VCC + 0.3V

DC Electrical Characteristics ≤ ≤ COP68xC: −55˚C TA +125˚C unless otherwise specified Parameter Condition Min Typ Max Units Operating Voltage 4.5 5.5 V

Power Supply Ripple (Note 17) Peak to Peak 0.1 VCC V Supply Current (Note 18)

CKI = 10 MHz VCC = 5.5V, tc = 1 µs 8.0 mA

CKI = 4 MHz VCC = 5.5V, tc = 2.5 µs 4.4 mA

HALT Current (Note 19) VCC = 5.5V, CKI = 0 MHz <10 30 µA Input Levels RESET, CKI

Logic High 0.9 VCC V

Logic Low 0.1 VCC V All Other Inputs

Logic High 0.7 VCC V

Logic Low 0.2 VCC V

Hi-Z Input Leakage VCC = 5.5V −5 +5 µA

Input Pullup Current VCC = 5.5V, VIN = 0V −35 −300 µA

G Port Input Hysteresis 0.35 VCC V Output Current Levels D Outputs

Source VCC = 4.5V, VOH = 3.8V −0.35 mA

Sink VCC = 4.5V, VOL = 1.0V 9 mA All Others

Source (Weak Pull-Up) VCC = 4.5V, VOH = 3.2V −9 −120 µA

Source (Push-Pull Mode) VCC = 4.5V, VOH = 3.2V −0.35 mA

Sink (Push-Pull Mode) VCC = 4.5V, VOL = 0.4V 1.4 mA

TRI-STATE Leakage VCC = 5.5V −5.0 +5.0 µA Allowable Sink/Source Current per Pin D Outputs (Sink) 12 mA All Others 2.5 mA

www.national.com 8 COP880C

DC Electrical Characteristics (Continued) ≤ ≤ COP68xC: −55˚C TA +125˚C unless otherwise specified Parameter Condition Min Typ Max Units Maximum Input Current (Room Temp) without Latchup (Note 20) Room Temp ±100 mA RAM Retention Voltage, Vr (Note 21) 500 ns Rise and Fall Time (Min) 2.5 V Input Capacitance 7pF Load Capacitance on D2 1000 pF

Note 16: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings. Note 17: Rate of voltage change must be less than 0.5V/ms. Note 18: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.

Note 19: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to VCC, L and G ports TRI-STATE and tied to ground, all outputs low and tied to ground.

Note 20: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCC and the pins will have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V. Note 21: To maintain RAM integrity, the voltage must not be dropped or raised instantaneously. COP680C/COP681C/COP682C AC Electrical Characteristics ≤ ≤ −55˚C TA +125˚C unless otherwise specified Parameter Condition Min Typ Max Units Instruction Cycle Time (tc) ≥ Ext. or Crystal/Resonant VCC 4.5V 1 DC µs (Div-by 10) CKI Clock Duty Cycle fr = Max 40 60 % (Note 22) Rise Time (Note 22) fr = 10 MHz Ext Clock 12 ns Fall Time (Note 22) fr = 10 MHz Ext Clock 8 ns

MICROWIRE Setup Time (tUWS)20ns

MICROWIRE Hold Time (tUWH)56ns MICROWIRE Output Valid 220 ns

Time (tUPD) Input Pulse Width

Interrupt Input High Time tC

Interrupt Input Low Time tC

Timer Input High Time tC

Timer Input Low Time tC Reset Pulse Width 1 µs

Note 22: Parameter characterized but not production tested.

9 www.national.com ≤ ≤ Typical Performance Characteristics (−40˚C TA +85˚C)

Hall — IDD Dynamic — IDD (Crystal Clock Option) COP880C

DS010802-16 DS010802-17

Port L/C/G Weak Pull-Up Port L/C/G Push-Pull Source Current

DS010802-18 DS010802-19

Port L/C/G Push-Pull Sink Current Port D Source Current

DS010802-20 DS010802-21

www.national.com 10 COP880C

≤ ≤ Typical Performance Characteristics (−40˚C TA +85˚C) (Continued)

Port D Sink Current

DS010802-22

Pin Descriptions Con- Data Port G Setup

VCC and GND are the power supply pins. fig. CKI is the clock input. This can come from an external 0 0 Hi-Z Input (TRI-STATE Output) source, a R/C generated oscillator or a crystal (in conjunc- 0 1 Input with Pull-Up (Weak One Output) tion with CKO). See Oscillator description. 1 0 Push-Pull Zero Output RESET is the master reset input. See Reset description. PORT I is an 8-bit Hi-Z input port. The 28-pin device does not 1 1 Push-Pull One Output have a full complement of Port I pins. The unavailable pins Since G6 and G7 are input only pins, any attempt by the user are not terminated i.e., they are floating. A read operation for to configure them as outputs by writing a one to the configu- these unterminated pins will return unpredictable values. ration register will be disregarded. Reading the G6 and G7 The user must ensure that the software takes this into ac- configuration bits will return zeros. The device will be placed count by either masking or restricting the accesses to bit in the HALT mode by writing to the G7 bit in the G-port data operations. The unterminated Port I pins will draw power register. only when addressed. Six pins of Port G have alternate features: PORT L is an 8-bit I/O port. G0 INTR (an external interrupt) PORT C is a 4-bit I/O port. G3 TIO (timer/counter input/output) Three memory locations are allocated for the L, G and C G4 SO (MICROWIRE serial data output) ports, one each for data register, configuration register and G5 SK (MICROWIRE clock I/O) the input pins. Reading bits 4–7 of the C-Configuration reg- ister, data register, and input pins returns undefined data. G6 SI (MICROWIRE serial data input) There are two registers associated with the L and C ports: a G7 CKO crystal oscillator output (selected by mask option) data register and a configuration register. Therefore, each L or HALT restart input (general purpose input) and C I/O bit can be individually configured under software Pins G1 and G2 currently do not have any alternate func- control as shown below: tions. PORT D is an 8-bit output port that is preset high when Con- Data Ports L and C Setup RESET goes low. Care must be exercised with the D2 pin fig. operation. At RESET, the external loads on this pin must

0 0 Hi-Z Input (TRI-STATE Output) ensure that the output voltages stay above 0.9 VCC to pre- 0 1 Input with Pull-Up (Weak One Output) vent the chip from entering special modes. Also, keep the external loading on D2 to less than 1000 pF. 1 0 Push-Pull Zero Output 1 1 Push-Pull One Output Functional Description On the 28-pin part, it is recommended that all bits of Port C Figure 1 shows the block diagram of the internal architec- be configured as outputs. ture. Data paths are illustrated in simplified form to depict PORT G is an 8-bit port with 6 I/O pins (G0–G5) and 2 input how the various logic elements communicate with each pins (G6, G7). All eight G-pins have Schmitt Triggers on the other in implementing the instruction set of the device. inputs. There are two registers associated with the G port: a data ALU AND CPU REGISTERS register and a configuration register. Therefore, each G port The ALU can do an 8-bit addition, subtraction, logical or shift bit can be individually configured under software control as operation in one cycle time. shown below: There are five CPU registers: A is the 8-bit Accumulator register PU is the upper 7 bits of the (PC) PL is the lower 8 bits of the program counter (PC)

11 www.national.com Functional Description (Continued) B is the 8-bit address register, can be auto incremented or

COP880C decremented. X is the 8-bit alternate address register, can be incremented or decremented. SP is the 8-bit stack pointer, points to subroutine stack (in RAM). B, X and SP registers are mapped into the on chip RAM. The DS010802-6 ≥ B and X registers are used to address the on chip RAM. The RC 5X Power Supply Rise Time SP register is used to address the stack in RAM during FIGURE 4. Recommended Reset Circuit subroutine calls and returns.

PROGRAM MEMORY OSCILLATOR CIRCUITS Program memory consists of 4096 bytes of ROM. These Figure 5 shows the three clock oscillator configurations. bytes may hold program instructions or constant data. The A. CRYSTAL OSCILLATOR program memory is addressed by the 15-bit program counter (PC). ROM can be indirectly read by the LAID in- The device can be driven by a crystal clock. The crystal struction for table lookup. network is connected between the pins CKI and CKO. Table 1 shows the component values required for various DATA MEMORY standard crystal values. The data memory address space includes on chip RAM, I/O and registers. Data memory is addressed directly by the B. EXTERNAL OSCILLATOR instruction or indirectly by the B, X and SP registers. CKI can be driven by an external clock signal. CKO is The device has 128 bytes of RAM. Sixteen bytes of RAM are available as a general purpose input and/or HALT restart mapped as “registers” that can be loaded immediately, dec- control. remented or tested. Three specific registers: B, X and SP are mapped into this space, the other bytes are available for C. R/C OSCILLATOR general usage. CKI is configured as a single pin RC controlled Schmitt The instruction set permits any bit in memory to be set, reset trigger oscillator. CKO is available as a general purpose or tested. All I/O and registers (except the A & PC) are input and/or HALT restart control. memory mapped; therefore, I/O bits and register bits can be Table 2 shows the variation in the oscillator frequencies as directly and individually set, reset and tested. A is not functions of the component (R and C) values. memory mapped, but bit operations can be still performed on it. Note: RAM contents are undefined upon power-up.

RESET The RESET input when pulled low initializes the microcon- troller. Initialization will occur whenever the RESET input is pulled low. Upon initialization, the ports L, G and C are placed in the TRI-STATE mode and the Port D is set high. The PC, PSW and CNTRL registers are cleared. The data and configuration registers for Ports L, G and C are cleared. The external RC network shown in Figure 4 should be used to ensure that the RESET pin is held low until the power supply to the chip stabilizes.

DS010802-7 FIGURE 5. Crystal and R-C Connection Diagrams OSCILLATOR MASK OPTIONS The device can be driven by clock inputs between DC and 10 MHz.

TABLE 1. Crystal Oscillator Configuration, TA = 25˚C

R1 R2 C1 C2 CKI Freq Conditions (kΩ)(MΩ) (pF) (pF) (MHz)

0 1 30 30–36 10 VCC =5V

0 1 30 30–36 4 VCC = 2.5V

5.6 1 200 100–150 0.455 VCC =5V

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Functional Description (Continued)

TABLE 2. RC Oscillator Configuration, TA = 25˚C

R C CKI Freq. Instr. Cycle Conditions (kΩ) (pF) (MHz) (µs)

3.3 82 2.2 to 2.7 3.7 to 4.6 VCC =5V

5.6 100 1.1 to 1.3 7.4 to 9.0 VCC =5V

6.8 100 0.9 to 1.1 8.8 to 10.8 VCC =5V Note 23: (R/C Oscillator Configuration): 3k ≤ R ≤ 200k, 50 pF ≤ C ≤ 200 pF. The device has three mask options for configuring the clock ENI and ENTI bits select external and timer interrupt respec- input. The CKI and CKO pins are automatically configured tively. Thus the user can select either or both sources to upon selecting a particular option. interrupt the microcontroller when GIE is enabled. • Crystal (CKI/10); CKO for crystal configuration IEDG selects the external interrupt edge (0 = rising edge, • External (CKI/10); CKO available as G7 input 1 = falling edge). The user can get an interrupt on both rising and falling edges by toggling the state of IEDG bit after each • R/C (CKI/10); CKO available as G7 input interrupt. G7 can be used either as a general purpose input or as a IPND and TPND bits signal which interrupt is pending. After control input to continue from the HALT mode. interrupt is acknowledged, the user can check these two bits to determine which interrupt is pending. This permits the HALT MODE interrupts to be prioritized under software. The pending flags The device supports a power saving mode of operation: have to be cleared by the user. Setting the GIE bit high HALT. The controller is placed in the HALT mode by setting inside the interrupt subroutine allows nested interrupts. the G7 data bit, alternatively the user can stop the clock The software interrupt does not reset the GIE bit. This input. In the HALT mode all internal processor activities means that the controller can be interrupted by other inter- including the clock oscillator are stopped. The fully static rupt sources while servicing the software interrupt. architecture freezes the state of the controller and retains all information until continuing. In the HALT mode, power re- INTERRUPT PROCESSING quirements are minimal as it draws only leakage currents The interrupt, once acknowledged, pushes the program and output current. The applied voltage (VCC) may be de- creased down to Vr (minimum RAM retention voltage) with- counter (PC) onto the stack and the stack pointer (SP) is out altering the state of the machine. decremented twice. The Global Interrupt Enable (GIE) bit is reset to disable further interrupts. The microcontroller then There are two ways to exit the HALT mode: via the RESET vectors to the address 00FFH and resumes execution from or by the CKO pin. A low on the RESET line reinitializes the that address. This process takes 7 cycles to complete. At the microcontroller and starts executing from the address end of the interrupt subroutine, any of the following three 0000H. A low to high transition on the CKO pin (only if the instructions return the processor back to the main program: external or R/C clock option selected) causes the microcon- RET, RETSK or RETI. Either one of the three instructions will troller to continue with no reinitialization from the address pop the stack into the program counter (PC). The stack following the HALT instruction. This also resets the G7 data pointer is then incremented twice. The RETI instruction ad- bit. ditionally sets the GIE bit to re-enable further interrupts. INTERRUPTS Any of the three instructions can be used to return from a hardware interrupt subroutine. The RETSK instruction There are three interrupt sources, as shown below. should be used when returning from a software interrupt A maskable interrupt on external G0 input (positive or nega- subroutine to avoid entering an infinite loop. tive edge sensitive under software control) Note: There is always the possibility of an interrupt occurring during an A maskable interrupt on timer underflow or timer capture instruction which is attempting to reset the GIE bit or any other inter- A non-maskable software/error interrupt on opcode zero rupt enable bit. If this occurs when a single cycle instruction is being used to reset the interrupt enable bit, the interrupt enable bit will be reset but an interrupt may still occur. This is because interrupt process- INTERRUPT CONTROL ing is started at the same time as the interrupt bit is being reset. To The GIE (global interrupt enable) bit enables the interrupt avoid this scenario, the user should always use a two, three or four function. This is used in conjunction with ENI and ENTI to cycle instruction to reset interrupt enable bits. select one or both of the interrupt sources. This bit is reset when interrupt is acknowledged.

13 www.national.com Functional Description (Continued) COP880C

DS010802-8 FIGURE 6. Interrupt Block Diagram DETECTION OF ILLEGAL CONDITIONS where,

The device contains a hardware mechanism that allows it to tC is the instruction cycle clock. detect illegal conditions which may occur from coding errors, noise and “brown out” voltage drop situations. Specifically it MICROWIRE/PLUS OPERATION detects cases of executing out of undefined ROM area and Setting the BUSY bit in the PSW register causes the unbalanced stack situations. MICROWIRE/PLUS arrangement to start shifting the data. It Reading an undefined ROM location returns 00 (hexadeci- gets reset when eight data bits have been shifted. The user mal) as its contents. The opcode for a software interrupt is may reset the BUSY bit by software to allow less than 8 bits also “00”. Thus a program accessing undefined ROM will to shift. The devoce may enter the MICROWIRE/PLUS cause a software interrupt. mode either as a Master or as a Slave. Figure 8 shows how Reading an undefined RAM location returns an FF (hexa- two COP880C microcontrollers and several peripherals may decimal). The subroutine stack grows down for each subrou- be interconnected using the MICROWIRE/PLUS arrange- tine call. By initializing the stack pointer to the top of RAM, ment. the first unbalanced return instruction will cause the stack pointer to address undefined RAM. As a result the program Master MICROWIRE/PLUS Operation will attempt to execute from FFFF (hexadecimal), which is an In the MICROWIRE/PLUS Master mode of operation the undefined ROM location and will trigger a software interrupt. shift clock (SK) is generated internally. The MICROWIRE/ PLUS Master always initiates all data exchanges. (See Fig- MICROWIRE/PLUS ure 8). The MSEL bit in the CNTRL register must be set to MICROWIRE/PLUS is a serial synchronous bidirectional enable the SO and SK functions onto the G Port. The SO communications interface. The MICROWIRE/PLUS capabil- and SK pins must also be selected as outputs by setting ity enables the device to interface with any of National appropriate bits in the Port G configuration register. Table 4 Semiconductor’s MICROWIRE peripherals (i.e. A/D convert- summarizes the bit settings required for Master mode of ers, display drivers, EEPROMS, etc.) and with other micro- operation. controllers which support the MICROWIRE/PLUS interface. It consists of an 8-bit serial shift register (SIO) with serial SLAVE MICROWIRE/PLUS OPERATION data input (SI), serial data output (SO) and serial shift clock In the MICROWIRE/PLUS Slave mode of operation the SK (SK). Figure 7 shows the block diagram of the MICROWIRE/ clock is generated by an external source. Setting the MSEL PLUS interface. bit in the CNTRL register enables the SO and SK functions The shift clock can be selected from either an internal source onto the G Port. The SK pin must be selected as an input or an external source. Operating the MICROWIRE/PLUS and the SO pin is selected as an output pin by appropriately interface with the internal clock source is called the Master setting up the Port G configuration register. Table 4 summa- mode of operation. Similarly, operating the MICROWIRE/ rizes the settings required to enter the Slave mode of opera- PLUS interface with an external shift clock is called the Slave tion. mode of operation. The user must set the BUSY flag immediately upon entering The CNTRL register is used to configure and control the the Slave mode. This will ensure that all data bits sent by the MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS, Master will be shifted properly. After eight clock pulses the the MSEL bit in the CNTRL register is set to one. The SK BUSY flag will be cleared and the sequence may be re- clock rate is selected by the two bits, SL0 and SL1, in the peated. (See Figure 8.) CNTRL register. Table 3 details the different clock rates that may be selected.

TABLE 3. SL1 SL0 SK Cycle Time

00 2tC

01 4tC

1x 8tC

www.national.com 14 COP880C

Functional Description (Continued)

TABLE 4.

G4 G5 G4 G5 G6 Config. Config. Fun. Fun. Fun. Operation Bit Bit 1 1 SO Int. SI MICROWIRE SK Master 0 1 TRI-STATE Int. SI MICROWIRE SK Master 1 0 SO Ext. SI MICROWIRE SK Slave 0 0 TRI-STATE Ext. SI MICROWIRE SK Slave DS010802-9 TIMER/COUNTER FIGURE 7. MICROWIRE/PLUS Block Diagram The device has a powerful 16-bit timer with an associated 16-bit register enabling them to perform extensive timer MODE 1. TIMER WITH AUTO-LOAD REGISTER functions. The timer T1 and its register R1 are each orga- nized as two 8-bit read/write registers. Control bits in the In this mode of operation, the timer T1 counts down at the register CNTRL allow the timer to be started and stopped instruction cycle rate. Upon underflow the value in the reg- under software control. The timer-register pair can be oper- ister R1 gets automatically reloaded into the timer which ated in one of three possible modes. Table 5 details various continues to count down. The timer underflow can be pro- timer operating modes and their requisite control settings. grammed to interrupt the microcontroller. A bit in the control register CNTRL enables the TIO (G3) pin to toggle upon timer underflows. This allow the generation of square-wave outputs or pulse width modulated outputs under software control. (See Figure 9.)

MODE 2. EXTERNAL COUNTER In this mode, the timer T1 becomes a 16-bit external event counter. The counter counts down upon an edge on the TIO pin. Control bits in the register CNTRL program the counter to decrement either on a positive edge or on a negative edge. Upon underflow the contents of the register R1 are automatically copied into the counter. The underflow can also be programmed to generate an interrupt. (See Figure 9)

MODE 3. TIMER WITH CAPTURE REGISTER Timer T1 can be used to precisely measure external fre- quencies or events in this mode of operation. The timer T1 counts down at the instruction cycle rate. Upon the occur- rence of a specified edge on the TIO pin the contents of the timer T1 are copied into the register R1. Bits in the control register CNTRL allow the trigger edge to be specified either as a positive edge or as a negative edge. In this mode the user can elect to be interrupted on the specified trigger edge. (See Figure 10.)

15 www.national.com Functional Description (Continued) COP880C

DS010802-10 FIGURE 8. MICROWIRE/PLUS Application

TABLE 5. Timer Operating Modes CNTRL Timer Bits Operation Mode T Interrupt Counts 765 On 0 0 0 External Counter W/Auto-Load Reg. Timer Underflow TIO Pos. Edge 0 0 1 External Counter W/Auto-Load Reg. Timer Underflow TIO Neg. Edge 0 1 0 Not Allowed Not Allowed Not Allowed 0 1 1 Not Allowed Not Allowed Not Allowed

1 0 0 Timer W/Auto-Load Reg. Timer Underflow tC

1 0 1 Timer W/Auto-Load Reg./Toggle TIO Out Timer Underflow tC

1 1 0 Timer W/Capture Register TIO Pos. Edge tC

1 1 1 Timer W/Capture Register TIO Neg. Edge tC

DS010802-12 DS010802-11 FIGURE 9. Timer/Counter Auto FIGURE 10. Timer Capture Mode Block Diagram Reload Mode Block Diagram TIMER PWM APPLICATION Figure 11 shows how a minimal component D/A converter can be built out of the Timer-Register pair in the Auto-Reload mode. The timer is placed in the “Timer with auto reload” mode and the TIO pin is selected as the timer output. At the outset the TIO pin is set high, the timer T1 holds the on time and the register R1 holds the signal off time. Setting TRUN bit starts the timer which counts down at the instruction cycle rate. The underflow toggles the TIO output and copies the off

www.national.com 16 COP880C

Functional Description (Continued) DIRECT The instruction contains an 8-bit address field that directly time into the timer, which continues to run. By alternately points to the data memory for the operand. loading in the on time and the off time at each successive interrupt a PWM frequency can be easily generated. IMMEDIATE The instruction contains an 8-bit immediate field as the operand.

REGISTER INDIRECT (AUTO INCREMENT AND DECREMENT) This is a register indirect mode that automatically increments or decrements the B or X register after executing the instruc- tion.

RELATIVE This mode is used for the JP instruction, the instruction field is added to the program counter to get the new program DS010802-13 location. JP has a range of from −31 to +32 to allow a one FIGURE 11. Timer Application byte relative jump (JP + 1 is implemented by a NOP instruc- tion). There are no “pages” when using JP, all 15 bits of PC Control Registers are used.

CNTRL REGISTER (ADDRESS X’00EE) Memory Map The Timer and MICROWIRE/PLUS control register contains All RAM, ports and registers (except A and PC) are mapped the following bits: into data memory address space. SL1 & SL0 Select the MICROWIRE/PLUS clock divide-by Address Contents IEDG External interrupt edge polarity select 00 to 6F On Chip RAM Bytes (0 = rising edge, 1 = falling edge) 70 to 7F Unused RAM Address Space (Reads as all Ones) MSEL Enable MICROWIRE/PLUS functions SO and 80 to BF Expansion Space for future use SK C0 to Expansion Space for I/O and Registers TRUN Start/Stop the Timer/Counter (1 = run, 0 = stop) CF TC3 Timer input edge polarity select (0 = rising D0 to On Chip I/O and Registers edge, 1 = falling edge) DF TC2 Selects the capture mode D0 Port L Data Register TC1 Selects the timer mode D1 Port L Configuration Register D2 Port L Input Pins (Read Only) TC1 TC2 TC3 TRUN MSEL IEDG SL1 SL0 D3 Reserved for Port L BIT BIT D4 Port G Data Register 7 0 D5 Port G Configuration Register D6 Port G Input Pins (Read Only) PSW REGISTER (ADDRESS X’00EF) D7 Port I Input Pins (Read Only) The PSW register contains the following select bits: D8 Port C Data Register GIE Global interrupt enable D9 Port C Configuration Register ENI External interrupt enable DA Port C Input Pins (Read Only) BUSY MICROWIRE/PLUS busy shifting DB Reserved for Port C IPND External interrupt pending DC Port D Data Register ENTI Timer interrupt enable DD–DF Reserved for Port D TPND Timer interrupt pending E0 to EF On Chip Functions and Registers C E0–E7 Reserved for Future Parts HC Half carry Flag E8 Reserved HC C TPND ENTI IPND BUSY ENI GIE E9 MICROWIRE/PLUS Shift Register EA Timer Lower Byte BIT BIT EB Timer Upper Byte 7 0 EC Timer Autoload Register Lower Byte Addressing Modes ED Timer Autoload Register Upper Byte EE CNTRL Control Register REGISTER INDIRECT EF PSW Register This is the “normal” mode of addressing. The operand is the F0 to FF On Chip RAM Mapped as Registers memory addressed by the B register or X register. FC X Register FD SP Register

17 www.national.com Memory Map (Continued) PU upper 7 bits of PC PL lower 8 bits of PC Address Contents C 1-bit of PSW register for carry COP880C FE B Register HC Half Carry GIE 1-bit of PSW register for global interrupt enable Reading unused memory locations below 7FH will return all ones. Reading other unused memory locations will return Symbols undefined data. [B] Memory indirectly addressed by B register Instruction Set [X] Memory indirectly addressed by X register Mem Direct address memory or [B] REGISTER AND SYMBOL DEFINITIONS MemI Direct address memory or [B] or Immediate data Imm 8-bit Immediate data Registers Reg Register memory: addresses F0 to FF (Includes B, X A 8-bit Accumulator register and SP) B 8-bit Address register Bit Bit number (0 to 7) X 8-bit Address register ← Loaded with SP 8-bit Stack pointer register ↔ Exchanged with PC 15-bit Program counter register

Instruction Set

ADD add A ← A + MemI ADC add with carry A ← A+MemI+C,C←Carry HC ← Half Carry SUBC subtract with carry A ← A + MemI +C, C ← Carry HC ← Half Carry AND Logical AND A ← A and MemI OR Logical OR A ← A or MemI XOR Logical Exclusive-OR A ← A xor MemI IFEQ IF equal Compare A and MemI, Do next if A = MemI IFGT IF greater than Compare A and MemI, Do next if A > MemI IFBNE IF B not equal Do next if lower 4 bits of B ≠ Imm DRSZ Decrement Reg. ,skip if zero Reg ← Reg − 1, skip if Reg goes to 0 SBIT Set bit 1 to bit, Mem (bit= 0 to 7 immediate) RBIT Reset bit 0 to bit, Mem IFBIT If bit If bit, Mem is true, do next instr. X Exchange A with memory A ↔ Mem LD A Load A with memory A ← MemI LD mem Load Direct memory Immed. Mem ← Imm LD Reg Load Register memory Immed. Reg ← Imm X Exchange A with memory [B] A ↔ [B] (B ← B±1) X Exchange A with memory [X] A ↔ [X] (X ← X±1) LD A Load A with memory [B] A ← [B] (B ← B±1) LD A Load A with memory [X] A ← [X] (X ← X±1) LD M Load Memory Immediate [B] ← Imm (B ← B±1) CLRA Clear A A ← 0 INCA Increment A A ← A+1 DECA Decrement A A ← A−1 LAID Load A indirect from ROM A ← ROM(PU,A) DCORA DECIMAL CORRECT A A ← BCD correction (follows ADC, SUBC) RRCA ROTATE A RIGHT THRU C C → A7 → … → A0 → C

www.national.com 18 COP880C

Instruction Set (Continued) Instruction Set (Continued) SWAPA Swap nibbles of A A7 … A4 ↔ A3…A0 SC Set C C ← 1, HC ← 1 RC Reset C C ← 0, HC ← 0 IFC If C If C is true, do next instruction IFNC If not C If C is not true, do next instruction JMPL Jump absolute long PC ← ii (ii = 15 bits, 0 to 32k) JMP Jump absolute PC11..0 ← i (i = 12 bits) JP Jump relative short PC ← PC+r(ris−31to+32, not 1) JSRL Jump subroutine long [SP] ← PL,[SP-1] ← PU,SP-2,PC ← ii JSR Jump subroutine [SP] ← PL,[SP-1] ← PU,SP-2,PC11.. 0 ← i JID Jump indirect PL ← ROM(PU,A) RET Return from subroutine SP+2,PL ← [SP],PU ← [SP-1] RETSK Return and Skip SP+2,PL ← [SP],PU ← [SP-1],Skip next instruction RETI Return from Interrupt SP+2,PL ← [SP],PU ← [SP-1],GIE ← 1 INTR Generate an interrupt [SP] ← PL,[SP−1] ← PU,SP-2,PC ← 0FF NOP No operation PC ← PC+1

19 www.national.com Instruction Set (Continued)

COP880C is3–0 Bits JP+27 JP+11 A JP+25 JP+9 8 JP+24 JP+8 7 JP+23 JP+7 6 JP+32 JP+16 F JP+28 JP+12 B JP+29 JP+13 C JP+26 JP+10 9 JP+31 JP+15 E JP+30 JP+14 D JP+22 JP+6 5 JP+20 JP+4 3 JP+21 JP i 5 4 JP+18 JP+2 1 JP+19 JP+3 2 JP+17 INTR 0 JMP JMP JMP JMP JMP JMP JMP JMP JMP JMP JMP JMP JMP JMP JMP JMP 0800–08FF 0700–07FF 0600–06FF 0900–09FF 0500–05FF 0300–03FF 0500–05FF 0100–01FF 0200–02FF 0000–00FF 0F00–0FFF 0A00–0AFF 0B00–0BFF 0E00–0EFF 0C00–0CFF 0D00–0DFF 0800–08FF 0700–07FF 0600–06FF 0900–09FF 0500–05FF 0400–04FF 0300–03FF 0200–02FF 0100–01FF 0000–00FF 0F00–0FFF 0A00–0AFF 0B00–0BFF 0E00–0EFF 0C00–0CFF 0D00–0DFF IFBNE 7 JSR IFBNE 6 JSR IFBNE 9 JSR IFBNE 5 JSR IFBNE 4 JSR IFBNE 3 JSR IFBNE 2 JSR IFBNE 1 JSR IFBNE 0 JSR IFBNE 0B JSR LD LD 0D #0F #0E B,#08 B,#09 B,#06 B,#04 B,#0A B,#0B B,#0C LD B, 7 IFBNE 8 JSR LD B, 3 IFBNE 0C JSR LD B, 5 IFBNE 0A JSR LD B, 0 IFBNE 0F JSR LD B, 2 IFBNE 0D JSR LD B, 1 IFBNE 0E JSR *LD *LD *LDB, *LDB, *LDB, 1,[B] 0,[B] 4,[B] 3,[B] 2,[B] 7,[B] 5,[B] 6,[B] RBIT RBIT RBIT RBIT RBIT RBIT RBIT RBIT CLRA LD DCORA LD SWAPA LD 7,[B] 1,[B] 0,[B] 6,[B] 4,[B] 3,[B] 2,[B] 3,[B] 2,[B] 7,[B] 5,[B] 4,[B] 5,[B] 6,[B] 1, [B] 0, [B] IFBIT IFBIT IFBIT IFBIT IFBIT IFBIT IFBIT IFBIT Bits 7–4 RET SBIT ADD AND ADC A,[B] XOR A,[B] A,[B] A,[B] A,[B] A,[B] IFGT IFEQ INCA SBIT A, [B] A, [B] DECA SBIT SUBC RETSK SBIT LD LD LD A,#i A,#i A,#i A,#i A,#i A, #i A, #i XOR IFGT [B],#i A,Md IFEQ [B−],#i [B+],#i X X LD LD LD A,[B] A,[B] JMPL X A,Md * SBIT A,[B−] A,[B+] A,[B+] A,[B−] * * * IFNC SBIT * * OR A,#i OR * * * RETI SBIT * LAID* ADD JID AND * SC SUBC X X LD LD LD LD DIR JSRL LD NOP * LD A,#i IFC SBIT A,[X] Md,#i A,[X−] A,[X+] A,[X+] A,[X−] RRCA RC ADC X A,[X] X 0F9 0F8 0F7 0F6 0F4 0F5 0F2 0F3 0F1 0F0 0FF 0FB 0FA 0FE 0FC 0FD F E D C BA9 876 5 4 3 2 10 Where, i is the immediate data Md is a directly addressed memory location * is an unused opcode (see following table) JP−4 JP−20 LD 0FB, #i DRSZ JP−6 JP−22 LD 0F9, #i DRSZ JP−7 JP−23 LD 0F8, #i DRSZ JP−8 JP−24 LD 0F7, #i DRSZ JP−3 JP−19 LDJP−2 0FC, #i JP−18 DRSZ LD 0FD, #i DRSZ JP−5 JP−21 LD 0FA, #i DRSZ JP−0 JP−16 LD 0FF, #i DRSZ JP−1 JP−17 LD 0FE, #i DRSZ JP−9 JP−25 LD 0F6, #i DRSZ JP−11 JP−27 LD 0F4,JP−10 #i JP−26 DRSZ LD 0F5, #i DRSZ JP−13 JP−29 LD 0F2,JP−12 #i JP−28 DRSZ LD 0F3, #i DRSZ JP−14 JP−30 LD 0F1, #i DRSZ JP−15 JP−31 LD 0F0, #i DRSZ Opcode List

www.national.com 20 COP880C Instruction Execution Time See the BYTES and CYCLES per INSTRUCTION table for details. Most instructions are single byte (with immediate addressing mode instruction taking two bytes). BYTES and CYCLES per Most single instructions take one cycle time to execute. Skipped instructions require x number of cycles to be INSTRUCTION skipped, where x equals the number of bytes in the skipped The following table shows the number of bytes and cycles for instruction opcode. each instruction in the format of byte/cycle. Arithmetic and Logic Instructions [B] Direct Immed. ADD 1/1 3/4 2/2 ADC 1/1 3/4 2/2 SUBC 1/1 3/4 2/2 AND 1/1 3/4 2/2 OR 1/1 3/4 2/2 XOR 1/1 3/4 2/2 IFEQ 1/1 3/4 2/2 IFGT 1/1 3/4 2/2 IFBNE 1/1 DRSZ 1/3 SBIT 1/1 3/4 RBIT 1/1 3/4 IFBIT 1/1 3/4

Memory Transfer Instructions Register Register Indirect Indirect Direct Immed. Auto Incr & Decr [B] [X] [B+, B−] [X+, X−] X A, (Note 24) 1/1 1/3 2/3 1/2 1/3 LD A, (Note 24) 1/1 1/3 2/3 2/2 1/2 1/3 LD B,Imm 1/1 (If B < 16) LD B,Imm 2/3 (If B > 15) LD Mem,Imm 2/2 3/3 2/2 LD Reg,Imm 2/3

Note 24: => Memory location addressed by B or X or directly.

Instructions UsingA&C JMP 2/3 CLRA 1/1 JP 1/3 INCA 1/1 JSRL 3/5 DECA 1/1 JSR 2/5 LAID 1/3 JID 1/3 DCORA 1/1 RET 1/5 RRCA 1/1 RETSK 1/5 SWAPA 1/1 RETI 1/5 SC 1/1 INTR 1/7 RC 1/1 NOP 1/1 IFC 1/1 The following table shows the instructions assigned to un- used opcodes. This table is for information only. The opera- IFNC 1/1 tions performed are subject to change without notice. Do not use these opcodes. Transfer of Control Instructions JMPL 3/4

21 www.national.com BYTES and CYCLES per • OTP/EPROM Programmer Support: Covering needs from engineering prototype, pilot production to full pro- INSTRUCTION (Continued) duction environments. COP880C Unused Instruction Unused Instruction iceMASTER (IM) IN-CIRCUIT EMULATION Opcode Opcode The iceMASTER IM-COP8/400 is a full feature, PC based, in-circuit emulation tool developed and marketed by Met- 60 NOP A9 NOP aLink Corporation to support the whole COP8 family of 61 NOP AF LD A, [B] products. National is a resale vendor for these products. 62 NOP B1 C → HC See Figure 12 for configuration. 63 NOP B4 NOP The iceMASTER IM-COP8/400 with its device specific 67 NOP B5 NOP COP8 Probe provides a rich feature set for developing, testing and maintaining product: 8C RET B7 X A, [X] • Real-time in-circuit emulation; full 2.4V–5.5V operation 99 NOP B9 NOP range, full DC-10 MHz clock. Chip options are program- 9F LD [B], #i BF LDA,[X] mable or jumper selectable. A7 X A, [B] • Direct connection to application board by package com- A8 NOP patible socket or surface mount assembly. • Full 32 kbyte of loadable programming space that over- Option List lays (replaces) the on-chip ROM or EPROM. On-chip RAM and I/O blocks are used directly or recreated on the The mask programmable options are listed out below. The probe as necessary. options are programmed at the same time as the ROM • Full 4k frame synchronous trace memory. Address, in- pattern to provide the user with hardware flexibility to use a struction, and 8 unspecified, circuit connectable trace variety of oscillator configuration. lines. Display can be HLL source (e.g., C source), as- OPTION 1: CKI INPUT sembly or mixed. = 1 Crystal (CKI/10) CKO for crystal configuration • A full 64k hardware configurable break, trace on, trace off control, and pass count increment events. = 2 External (CKI/10) CKO available as G7 input • Tool set integrated interactive symbolic = 3 R/C (CKI/10) CKO available as G7 input debugger — supports both assembler (COFF) and C Compiler (.COD) linked object formats. OPTION 2: BONDING • Real time performance profiling analysis; selectable = 1 44-Pin PLCC bucket definition. = 2 40-Pin DIP • Watch windows, content updated automatically at each = 3 28-Pin SO execution break. = 4 28-Pin DIP • Instruction by instruction memory/register changes dis- The following option information is to be sent to National played on source window when in single step operation. along with the EPROM. • Single base unit and debugger software reconfigurable to support the entire COP8 family; only the probe personal- Option Data ity needs to change. Debugger software is processor Option 1 Value__is: CKI Input customized, and reconfigured from a master model file. Option 2 Value__is: COP Bonding • Processor specific symbolic display of registers and bit level assignments, configured from master model file. Development Support • Halt/Idle mode notification. • On-line HELP customized to specific processor using SUMMARY master model file. • iceMASTER™ : IM-COP8/400 — Full feature in-circuit • Includes a copy of COP8-DEV-IBMA assembler and emulation for all COP8 products. A full set of COP8 Basic linker SDK. and Feature Family device and package specific probes are available. • COP8 Debug Module: Moderate cost in-circuit emulation and development programming unit. • COP8 Evaluation and Programming Unit: EPU-COP880C — low cost In-circuit simulation and de- velopment programming unit. • Assembler: COP8-DEV-IBMA. A DOS installable cross development Assembler, Linker, Librarian and Utility Soft- ware Development Tool Kit. • C Compiler: COP8C. A DOS installable cross develop- ment Software Tool Kit.

www.national.com 22 COP880C

Development Support (Continued) iceMASTER Probe IM Order Information MHW-880C20DWPC 20 DIP MHW-880C28DWPC 28 DIP Base Unit MHW-880CJ40DWPC 40 DIP IM-COP8/400-1 iceMASTER base unit, MHW-880CJ44PWPC 44 PLCC 110V power supply DIP to SO Adapters IM-COP8/400-2 iceMASTER base unit, MHW-SOIC20 20 SO 220V power supply MHW-SOIC28 28 DIP

DS010802-24 FIGURE 12. COP8 iceMASTER Environment

23 www.national.com Development Support (Continued) • Debugger software is processor customized, and recon- figured from a master model file. iceMASTER DEBUG MODULE (DM) • Processor specific symbolic display of registers and bit COP880C The iceMASTER Debug Module is a PC based, combination level assignments, configured from master model file. in-circuit emulation tool and COP8 based OTP/EPROM pro- • Halt/Idle mode notification. gramming tool developed and marketed by MetaLink Corpo- • Programming menu supports full product line of program- ration to support the whole COP8 family of products. Na- mable OTP and EPROM COP8 products. Program data tional is a resale vendor for these products. is taken directly from the overlay RAM. See Figure 13 for configuration. • Programming of 44 PLCC and 68 PLCC parts requires The iceMASTER Debug Module is a moderate cost devel- external programming. adapters. opment tool. It has the capability of in-circuit emulation for a • Includes wallmount power supply. specific COP8 microcontroller and in addition serves as a programming tool for COP8 OTP and EPROM product fami- • On-board VPP generator from 5V input or connection to lies. Summary of features is as follows: external supply supported. Rquires VPP level adjustment per the family programming specification (correct level is • Real-time in-circuit emulation; full operating voltage provided on an on-screen pop-down display). range operation, full DC-10 MHz clock. • On-line HELP customized to specific processor using • All processor I/O pins can be cabled to an application master model file. development board with package compatible cable to socket and surface mount assembly. • Includes a copy of COP8-DEV-IBMA assembler and linker SDK. • Full 32 kbyte of loadable programming space that over- lays (replaces) the on-chip ROM or EPROM. On-chip RAM and I/O blocks are used directly or recreated as DM Order Information necessary. • 100 frames of synchronous trace memory. The display Debug Model Unit can be HLL source (C source), assembly or mixed. The COP8-DM/880C most recent history prior to a break is available in the Cable Adapters trace memory. DM-COP8/20D 20 DIP • Configured break points; uses INTR instruction which is modestly intrusive. DM-COP8/28D 28 DIP • Software — only supported features are selectable. DM-COP8/40D 40 DIP • Tool set integrated interactive symbolic DM-COP8/44P 44 PLCC debugger — supports both assembler (COFF) and C DIP to SO Adapters Compiler (.COD) SDK linked object formats. DM-COP8/20D-SO 20 SO • Instruction by instruction memory/register changes dis- DM-COP8/28D-SO 28 SO played when in single step operation.

DS010802-25 FIGURE 13. COP8-DM Environment

www.national.com 24 COP880C

Development Support (Continued) • Tool set integrated interactive symbolic debugger — supports both assembler (COFF) and C iceMASTER EVALUATION PROGRAMMING UNIT (EPU) Compiler (.COD) SDK linked object formats. The iceMASTER EPU-COP880C is a PC based, in-circuit • Instruction by instruction memory/register changes dis- simulation tool to support the feature family COP8 products. played when in single step operation. See Figure 14 for configuration. • Processor specific symbolic display of registers and bit The simulation capability is a very low cost means of evalu- level assignments, configured from master model file. ating the general COP8 architecture. In addition, the EPU • Halt/Idle mode notification. Restart requires special han- has programming capability, with added adapters, for pro- dling. gramming the whole COP8 product family of OTP and • Programming menu supports full product line of program- EPROM products. The product includes the following fea- mable OTP and EPROM COP8 products. Only a 40 ZIF tures: socket is available on the EPU unit. Adapters are avail- • Non-real-time in-circuit simulation. Program overlay able for other part package configurations. memory is PC resident; instructions are downloaded over • Integral wall mount power supply provides 5V and devel- RS-232 as executed. Approximate performance is ops the required VPP to program parts. 20 kHz. • Includes a copy of COP8-DEV-IBMA assembler, linker • Includes a 40 pin DIP cable adapter. Other target pack- SDK. ages are not supported. All processor I/O pins are cabled to the application development environment. • Full 32 kbyte of loadable programmable space that over- EPU Order Information lays (replaces) the on-chip ROM or EPROM. On-chip Evaluation Programming Unit RAM and I/O blocks are used directly or recreated as necessary. EPU-COP880C Evaluation Programming Unit • On-chip timer and WATCHDOG execution are not well with debugger and programmer synchronized to the instruction simulation. control software with 40 ZIF • 100 frames of synchronous trace memory. The display programming socket. can be HLL source (e.g., C source), assembly or mixed. General Programming Adapters The most recent history prior to a break is available in the COP8-PGMA-DS 28 and 20 DIP and SOIC adapter trace memory. COP8-PGMA-DS44P 28 and 20 DIP and SOIC plus 44 Up to eight software configured break points; uses INTR • PLCC adapter instruction which is modestly intrusive. • Common look-feel debugger software across all Met- aLink products — only supported features are selectable.

DS010802-26 FIGURE 14. EPU-COP8 Tool Environment

25 www.national.com Development Support (Continued) COP8 C COMPILER A C Compiler is developed and marketed by Byte Craft COP8 ASSEMBLER/LINKER SOFTWARE Limited. The COP8C compiler is a fully integrated develop-

COP880C DEVELOPMENT TOOL KIT ment tool specifically designed to support the compact em- National Semiconductor offers a relocateable COP8 macro bedded configuration of the COP8 family of products. cross assembler, linker, librarian and utility software devel- Features are summarized as follows: opment tool kit. Features are summarized as follows: • ANSI C with some restrictions and extensions that opti- • Basic and Feature Family instruction set by “device” type. mize development for the COP8 embedded application. • Nested macro capability. • BITS data type extension. Register declaration #pragma • Extensive set of assembler directives. with direct bit level definitions. • Supported on PC/DOS platform. • C language support for interrupt routines. • Generates National standard COFF output files. • Expert system, rule based code geration and optimiza- • Integrated Linker and Librarian. tion. • Integrated utilities to generate ROM code file outputs. • Performs consistency checks against the architectural definitions of the target COP8 device. • DUMPCOFF utility. • Generates program memory code. This product is integrated as a part of MetaLink tools as a development kit, fully supported by the MetaLink debugger. • Supports linking of compiled object or COP8 assembled It may be ordered separately or it is bundled with the Met- object formats. aLink products at no additional cost. • Global optimization of linked code. • Symbolic debug load format fully sourced level supported Order Information by the MetaLink debugger. Assembler SDK: INDUSTRY WIDE OTP/EPROM PROGRAMMING SUPPORT COP8-DEV-IBMA Assembler SDK on installable 3.5" Programming support, in addition to the MetaLink develop- PC/DOS Floppy Disk Drive format. ment tools, is provided by a full range of independent ap- Periodic upgrades and most recent proved vendors to meet the needs from the engineering version is available on National’s laboratory to full production. BBS and Internet. Approved List Manufacturer North Europe Asia America BP (800) 225-2102 +49-8152-4183 +852-234-16611 Microsystems (713) 688-4600 +49-8856-932616 +852-2710-8121 Fax: (713) 688-0920 Data I/O (800) 426-1045 +44-0734-440011 Call (206) 881-6444 North America Fax: (206) 882-1043 HI–LO (510) 623-8860 Call Asia +886-2-764-0215 Fax: +886-2-756-6403 ICE (800) 624-8949 +44-1226-767404 Technology (919) 430-7915 Fax: 0-1226-370-434 MetaLink (800) 638-2423 +49-80 9156 96-0 +852-737-1800 (602) 926-0797 Fax: +49-80 9123 86 Fax: (602) 693-0681 Systems (408) 263-6667 +41-1-9450300 +886-2-917-3005 General Fax: +886-2-911-1283 Needhams (916) 924-8037 Fax: (916) 924-8065

www.national.com 26 COP880C

Development Support (Continued) DIAL-A-HELPER via FTP AVAILABLE LITERATURE ftp nscmicro.nsc.com For more information, please see the COP8 Basic Family user: anonymous User’s Manual, Literature Number 620895, COP8 Feature password: [email protected] Family User’s Manual, Literature Number 620897 and Na- tional’s Family of 8-bit Microcontrollers COP8 Selection DIAL-A-HELPER via WorldWide Web Browser Guide, Literature Number 630009. ftp://nscmicro.nsc.com

DIAL-A-HELPER SERVICE National Semiconductor on the WorldWide Web Dial-A-Helper is a service provided by the Microcontroller See us on the WorldWide Web at: http://www.national.com Applications group. The Dial-A-Helper is an Electronic Infor- mation System that may be accessed as a Bulletin Board CUSTOMER RESPONSE CENTER System (BBS) via data modem, as an FTP site on the Complete product information and technical support is avail- Internet via standard FTP client application or as an FTP site able from National’s customer response centers. on the Internet using a standard Internet browser such as Netscape or Mosaic. CANADA/U.S.: Tel: (800)272-9959 The Dial-A-Helper system provides access to an automated email: [email protected] information storage and retrieval system . The system capa- EUROPE: email: [email protected] bilities include a MESSAGE SECTION (electronic mail, Deutsch Tel: +49 (0) 180-530 85 85 when accessed as a BBS) for communications to and from English Tel: +49 (0) 180-532 78 32 the Microcontroller Applications Group and a FILE SECTION Français Tel: +49 (0) 180-532 93 58 which consists of several file areas where valuable applica- tion software and utilities could be found. Italiano Tel: +49 (0) 180-534 16 80 JAPAN: Tel: +81-043-299-2309 DIAL-A-HELPER BBS via a Standard Modem S.E. ASIA: Beijing Tel: (+86) 10-6856-8601 Modem: CANADA/U.S.: (800) NSC-MICRO Shanghai Tel: (+86) 21-6415-4092 Hong Kong Tel: (+852) 2737-1600 (800) 672-6427 Korea Tel: (+82) 2-3771-6909 EUROPE: (+49) 0-8141-351332 Malaysia Tel: (+60-4) 644-9061 Baud: 14.4k Singapore Tel: (+65) 255-2226 Set-Up: Length: 8-Bit Taiwan Tel: +886-2-521-3288 Parity: None AUSTRALIA: Tel: (+61) 3-9558-9999 Stop Bit: 1 INDIA: Tel: (+91) 80-559-9467 Operation: 24 Hours, 7 Days

27 www.national.com Physical Dimensions inches (millimeters) unless otherwise noted COP880C

Small Outline Molded Dual-In-Line Package (M) Order Number COP882C-XXX/WM, COP982C-XXX/WM, COP682C-XXX/WM or COP982CH-XXX/WM NS Package Number M20B

Small Outline Molded Dual-In-Line Package (M) Order Number COP881C-XXX/WM, COP981C-XXX/WM, COP681C-XXX/WM or COP981CH-XXX/WM NS Package Number M28B

www.national.com 28 COP880C

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Molded Dual-In-Line Package (N) Order Number COP882C-XXX/N, COP682C-XXX/N, COP982C-XXX/N or COP982CH-XXX/N NS Package Number N20B

Molded Dual-In-Line Package (N) Order Number COP881C-XXX/N, COP681C-XXX/N, COP981C-XXX/N or COP981CH-XXX/N NS Package Number N28B

29 www.national.com Physical Dimensions inches (millimeters) unless otherwise noted (Continued) COP880C

Molded Dual-In-Line Package (N) Order Number COP880C-XXX/N, COP680C-XXX/N, COP980C-XXX/N or COP980CH-XXX/N NS Package Number N40A

Plastic Leaded Chip Carrier (V) Order Number COP880C-XXX/V, COP680C-XXX/V, COP980C-XXX/V or COP980CH-XXX/V NS Package Number V44A

www.national.com 30 O80 Microcontrollers COP880C Notes

LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform into the body, or (b) support or sustain life, and can be reasonably expected to cause the failure of whose failure to perform when properly used in the life support device or system, or to affect its accordance with instructions for use provided in the safety or effectiveness. labeling, can be reasonably expected to result in a significant injury to the user.

National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Asia Pacific Customer Japan Ltd. Americas Fax: +49 (0) 180-530 85 86 Response Group Tel: 81-3-5639-7560 Email: [email protected] Email: [email protected] Tel: 65-2544466 Fax: 81-3-5639-7507 Deutsch Tel: +49 (0) 69 9508 6208 Fax: 65-2504466 English Tel: +44 (0) 870 24 0 2171 Email: [email protected] www.national.com Français Tel: +33 (0) 1 41 91 8790

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