Architektura komputerów, Informatyka, sem.III Communication Serial Serial Buses Architektura komputerów, Informatyka, sem.III Serial digital technology: digital modern the dominating is and speeds at higher transfer for allows technology communication serial Improved communication parallel vs Serial sequentially time, one at bit one Sending cable cost PCB(or space), synchronization, distance ! Express, etc. , MIDI, Serial Attached SCSI, Serial ATA, PCI RS232, RS-485, I2C, SPI, 1-Wire, USB, FireWire, , speed ? Architektura komputerów, Informatyka, sem.III RS232, EIA232 RS232, standard RS-232-C (1969) RS-232-C standard Industries Electronic The (EIA) Alliance voltage levels, signaling rate, timing, short-circuit behavior, cable definition of (electrical signal characteristics: many protocols use RS232 (e.g. ) numerous handshake lines (seldom used) truly bi-directional transfer (full-duplex) asynchronous operation (no clock signal) serial transmission (bit-by-bit) 25 or (more often) 9-pin connector length, etc.) Architektura komputerów, Informatyka, sem.III Voltage Levels and support long cable lengths cable long support and immunity noise improve to levels voltage bipolar into signals convert standard TTL/CMOS-level RS-232 +5V (+3.3V) = logic one one logic +5V (+3.3V) = zero 0V =logic TTL/CMOS(UART) many receivers are sensitive to differentials to sensitive are 1V of manyreceivers +3V)vary, may(−3V... area" The"dead "MARK" the as state level voltage zero a accepts and level negative the Someignores equipment → → →

+3V RS232: − 3V …− … +12V(SPACE) 12V (MARK)12V Architektura komputerów, Informatyka, sem.III Dataframe Complete one-byte frame consists of: frame consists one-byte Complete start-bit (SPACE), start-bit (MARK) stop-bits 8), (7, bits data e.g. 9600-8N1e.g. 19200-7E1 or Typical RS-232 hex) 'b'=0x61 byte transfer (ASCII hex) TTL (5V)RS-232 'b'=0x61 bytetransfer (ASCII converter Voltage Architektura komputerów, Informatyka, sem.III DataRates (but not both) not (but meters 400 to up lengths cable and bps 19200 EIAPure to up rates data permits standard RS-232C bps 9600 above speeds at communications for mandatory is UART and FIFO 16550 Common a16-byte incorporates RS-232 via communication fast for Receiver/Transmitter (UART)responsible component – Universal Asynchronous possible m)are 2 than less (over 256kbps as high as rates Data Architektura komputerów, Informatyka, sem.III DTE and DCE and DTE The RS-232 defines two classes of devices: devices: of classes two defines RS-232 The distinction between DTE&DCE allows to avoid confusion e.g. is TD output line on DTE, but input line on DCE equipment (DCE) – modem (female) data terminal equipment (DTE) – computer (male) male chauvinism? male Architektura komputerów, Informatyka, sem.III TxD Transmitted Data [DTE --> DTE] STxD Secondary Transmitted Data [DTE --> DTE] SRxD Secondary Received Data [DCE --> DTE] SRTS Secondary Ready To Send [DTE --> DCE] SDCD Secondary Data Carrier Detected (Tone)[DCE -> DTE] SCTS Secondary Clear To Send [DCE --> DTE] SG Signal Ground RxD Received Data [DCE --> DTE] RTS Request To Send [DTE --> DCE] RI Ring Indicator (ringing tone detected) RCk Receiver (external) Clock input NC No Connection FG Frame Ground (screen or chassis) DTR Data Terminal Ready [DTE --> DCE] DTE Data Terminal Equipment eg. computer, printer DSRS Data Signal Rate Selector [DCE --> DTE] (Not common) DSR Data Set Ready [DCE --> DTE] DCE Data Communications Equipment eg. modem DCD Data Carrier Detected (Tone from a modem) [DCE --> DTE] CTS Clear To Send [DCE --> DTE] but only very few are used in practice Many communications options exist, fairly complex Complete RS232 standard define a lot of signals and is Signals Architektura komputerów, Informatyka, sem.III Handshaking Software handshaking Software handshaking Hardware XON/XOFF DTR/DTE RTS/CTS ● ● ● to resumeto transfer haltto data transfer and anothercharacter(Control-Q, ASCII 17) requires thatthe receiver senda character (Control-S, ASCII 19) asserts the "datasetready" signal(DSR) DTE assertsthe"data terminal ready" (DTR)signal, and DCE asserts "clearsend" to whenit (CTS) is readyreceive to data receive data and deasserts itwhen cannot it accepta data; DCE DTE assertsthe"requestsend" to (RTS) signal when itis ready to Architektura komputerów, Informatyka, sem.III and others and RJ45 9, Sub-D 25, Sub-D Various adapters to DB9 DB25 wiring – Loopback DTE DTE DTE ↔D ↔ DTE – Null-modem (cross-over cable) (cross-over – Null-modem DTE CE – – CE Straight connection Straight Architektura komputerów, Informatyka, sem.III Null-modem Wirings Null-modem Architektura komputerów, Informatyka, sem.III Weaknesses Low transfer rate transfer Low supplies negative and positive for Requirement ground Common Large recommended connector recommended Large device toa power sending for method No options communication unnecessary Many DCE and of DTE definitions Asymmetrical communication only Point-to-point Architektura komputerów, Informatyka, sem.III Strengths communications but ... but communications local for USB by superseded being is RS-232 has no direct analog to the terminal programs for 'raw' USB is more complex (physical layer +protocol + driver) and Lot od cheap RS232<->USB converters It is available in most of microcontrollers is not critical but distance is long Simplicity makes it good for industrial applications where speed over RS232 (by software or hardware) Lots of communication protocols can be easily implemented communication Architektura komputerów, Informatyka, sem.III RS232 Forever ... RS232Forever PCI-Express Cardwith 1 RS232CPort Architektura komputerów, Informatyka, sem.III RelatedStandards RS-485 half-duplex a two-wire differential signaling (U+, U-) speeds up to 35 Mbit/s (10 m) and 100 kbit/s (1200 m) multipoint serial connection (inexpensive local networks) Architektura komputerów, Informatyka, sem.III Differential Signaling Differential Resistance to electromagnetic interference electromagnetic to Resistance electronics low-voltage with use for Suitability Tolerance offsetsof ground RS-485, PCI Express, USB, ... USB, Express, PCI RS-485, Architektura komputerów, Informatyka, sem.III USB all legacy varieties of serial and parallel ports (1995) ports parallel and serial of varieties legacy all retire help to intended was (USB) Serial Universal Complex software+hardware Complex layer physical to access direct No single standardized interface socket error correction,error protocols, device classes, etc. requiring manufacturer specific allowing many standard devices to be used without providing power to devices (2.5 – 4.5 – 15W) plug-and-play + Architektura komputerów, Informatyka, sem.III USB Bus Topology Bus USB devices with host host with devices connects always USB host+interconnect+devices system: USB is a tiered star tiered a is topology Interconnect (master-slave) Architektura komputerów, Informatyka, sem.III Speed ⅔ about is devices real with attained throughput actual The rates: data Several USB 1.x full-speed 12 Mb/s USB 1.x low-speed 1.5 Mb/s USB 3.0 Super-Speed USB 2.0 high-speed 480 Mb/s of the maximum theoretical bulk data transfer rate transfer data bulk theoretical maximum the of ● ● ● 4.8Gbit/s (600MB/s) USB 3.1SuperSpeed+10 Gbit/s Full-duplex withadditional twisted pair (10 pinsin total) Architektura komputerów, Informatyka, sem.III Electrical Interface (1.x, 2.0)Interface Electrical (1.x, Clock tolerance: Clock ± Speed) (Low/Full High 2.8–3.6V and Low 0.0–0.3V Twisted impedance ±15% 90Ω with cable data pair half-duplex, differential cable, signaling, Four-wire 400mV in High Speed (+ protocol to negotiate HS) negotiate to protocol (+ Speed High in 400mV 1.50 Mbit/s ±1.5% 12.000 Mbit/s ±0.25% 480.00 Mbit/s ±0.05% Architektura komputerów, Informatyka, sem.III Data Signaling (Low/Full) DataSignaling NRZI (non-return-to-zero inverted) encoding inverted) (non-return-to-zero NRZI packets in organized is transmission Data Architektura komputerów, Informatyka, sem.III NRZI Encoding NRZI "0" has no transition no has "0" transition a by represented is "1" slip bit avoid to be used must technique synchronization code, aself-synchronizing Not condition rest or neutral other no with represented are "0s" and "1s" which in code Binary Architektura komputerów, Informatyka, sem.III I²C - Inter- - I²C Inter-Integrated

I²C ( I²C only two wirescommon (+ ground) communication between integrated circuits simple – hardware or(easy) software implementation 7bit or 10bit unique device addressing no strict baud rate requirements (master sends the clock) multi-master/multi-slave, bidirectional, 8-bit I-squared-C ) – Philips (NXP), early 80's (XX) 80's early (NXP), –Philips ) → small PCB'ssmall Architektura komputerów, Informatyka, sem.III Highly-integrated TV set TV Highly-integrated (historical) Example of TV set architecture with I2C Architektura komputerów, Informatyka, sem.III Characteristics Voltage levels Two-wired ground) (+ bus Speed: 400 kbps (fast mode) 100 kbps (standard mode) LOW HIGH not fixed, depends on supply level of voltage serial clock line (SCL) serial data line (SDA) 3.4 Mbps (high-speed mode) → →

1 0 Architektura komputerów, Informatyka, sem.III Bit Transfer Bit Bit transfer is level triggered level is transfer Bit one clock pulse per data bit SCL = 0 data change during low clocks stable data during high clocks ↑ 1 → SDA = valid data Architektura komputerów, Informatyka, sem.III Start and Stop and Start Start condition (S) condition Start SCL &SDA idle when high are Stop condition (P) condition Stop open-drain pull-up+ resistor SDA 0 SDA 1 ↑ ↓ 0 transition when SCL = 1 1 transition when SCL = 1 Architektura komputerów, Informatyka, sem.III Slave must respond with acknowledge with respond must Slave master by initiated are transfers All Acknowledge Architektura komputerów, Informatyka, sem.III Data Frame Data Stop (master Data slave from Acknowledge Command + Direction address Slave + Start → slave slave or slave → master ) + ) + Ack. Architektura komputerów, Informatyka, sem.III Frame Formats Frame Combined receiver Master transmitter Master Architektura komputerów, Informatyka, sem.III Addressing 7-bit addressing 7-bit 10-bit addressing 10-bit 7 addresses reserved max. 112 slaves 1024 new addresses 11110 prefix +10 address bit (R/W in the middle) ● e.g.broadcast, 10-bitextension start-byte, Architektura komputerów, Informatyka, sem.III Closing Remarks Closing Elegance of I²C: simplicity & effectiveness & simplicity I²C: of Elegance Limited Limited Space: Address addresses slave I²C obtain to required but implementation, I²C for fees licensing No circuits integrated & microcontrollers for standard communication common most of One flexible timing: no strict baud rate, clock stretching shared bus, reasonable speed, two wires (pins), hotplug devices with configurable address arbitration & collision detection in multi-master mode ● higher bits indicate model,lower bits type - Architektura komputerów, Informatyka, sem.III Derivatives (SMBus) Bus Management System ... Two (TWI) Interface Wire VESA(DDC) Channel Data Display low-bandwidth devices on a PC motherboard I connection between monitor graphics card 2 C implementedC in chips from Atmel ● ● withDVI,HDMIconnectors VGA, configurationdata DDR2, of ... laptop'sbattery, or voltage temperature,fan, sensors, Architektura komputerów, Informatyka, sem.III 1-Wire® instruments weather and thermometers digital as such devices Typically inexpensive small with communicate to used Maxim-Dallas) (now Corp. Semiconductor Dallas of trademark Registered Signaling and power using 1 wire ground) (+ Easy implementation Low cost Long range (up tp 500m) Low-speed ( < 1 kbps) Architektura komputerów, Informatyka, sem.III AvailableDevices ... Monitors and Selectors, Protectors, Battery TimekeepingReal-Time and Clocks Converters A-to-D Interfaces 1-Wire ROM,NV EEPROM, SRAM, EPROM, Memory: TemperatureSwitches and Sensors Architektura komputerów, Informatyka, sem.III Powering 1-Wire Powering Devices Parasite-powered supply external With DS18B20 - Programmable Resolution 1-Wire Digital Digital 1-Wire Resolution Programmable - DS18B20 and user-definable nonvolatile alarm settings alarm nonvolatile user-definable and accuracy Thermometer,±0.5°C +125°C, to –55°C Architektura komputerów, Informatyka, sem.III Device Addressing every device on the bus the on device every of address the recover to algorithm an has also bus The devices toparticular addressed commands and commands broadcast are There bus same the share can devices slave Many master bus one only always is There Each device has a unique 64-bit serial number serial 64-bit unique a has device Each Architektura komputerów, Informatyka, sem.III TransactionSequence Step 1. Initialization Step (followed by any required data exchange) data required any by (followed Command 3. Function Step exchange) data required any by (followed Command 2. ROM Step reset pulse Read, Write, ReadPowerSupply, ... Search, Read, Match, Skip, Alarm, ... Architektura komputerów, Informatyka, sem.III Initialization devices are on the bus the on are devices slave that know master bus the lets pulse presence The slave(s) the by transmitted pulse(s) presence by followed master bus the by transmitted pulse Reset Architektura komputerów, Informatyka, sem.III MasterWrite Bit pulling the 1-Wire bus low bus 1-Wire the pulling master the by initiated are Write slots time continues to hold the bus low for the time slot Write 0 time slot: after pulling the bus low, the bus master releases the bus (pullup will pull the bus high) Write 1 time slot: after pulling the bus low, the bus master Architektura komputerów, Informatyka, sem.III Master Read Bit MasterRead the master issues read-related commands read-related issues master the after master the to data transmit only can Slaves the slave begins transmitting a 1 or 0 on bus After the master initiates the read time slot, and 0 by pulling the bus low 1 is transmitted by leaving the bus high Architektura komputerów, Informatyka, sem.III SS — SlaveSS — Select(active low; outputfrom master) Slave— MasterInput, Output (output from slave) MISO/SOMI Slave— MasterOutput, Input (output from master) MOSI/SIMO SCLK— Serial Clock (output from master) SPI Serial Peripheral Interface Bus (SPI) - Motorola - (SPI) Bus Interface Peripheral Serial synchronous serial data link (clock signal) four wire" serial bus (chip select) multiple slaves are allowed with individual slave select full duplex mode Architektura komputerów, Informatyka, sem.III Data TransmissionData transmission occurs: transmission data duplex full a cycle, clock SPI each During that same line (rising SCLK) the master sends a bit on the MOSI line; the slave reads it from that same line (falling SCLK) the slave sends a bit on the MISO line; the master reads it from Architektura komputerów, Informatyka, sem.III Closing Remarks Closing Disadvantages Advantages ● ● ● ● ● ● ● ● ● ● No synchronization problems No arbitration orassociated failure modes Extremely simplehardwareinterfacing Arbitrary choice of messagesize and content Very higher fast- throughput than I²C Fullduplex communication short distances limitedto single a slave No hardware flow control, noslave acknowledgment lines/pinsmore thanI²C