TABLE 4-1 Baudot Code
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. TABLE 4-2 ASCII-77: Odd Parity
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. TABLE 4-2 (Continued)
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. TABLE 4-3 EBCDIC Code
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. TABLE 4-3 (Continued)
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. TABLE 4-3 (Continued)
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-1 Typical bar code
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. TABLE 4-4 Code 39 Character Set
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-2 Code 39 bar code
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-3A (a) UPC version A character set; (b) UPC label format; (c) left- and right-hand bit sequence for the digit 4
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-3B (a) UPC version A character set; (b) UPC label format; (c) left- and right-hand bit sequence for the digit 4
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-3C (a) UPC version A character set; (b) UPC label format; (c) left- and right-hand bit sequence for the digit 4
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. TABLE 4-5 UPC Number System Characters
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-4 UPC character 0
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-5 CRC-16 generating circuit
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-6 Data unit comprised of m character bits and n Hamming bits
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-7 Asynchronous data format
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-8A Telephone communications network: (a) human communications; (b) digital data communications
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-8B Telephone communications network: (a) human communications; (b) digital data communications
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-9A Two point data communications circuit: (a) DTE/DCE representation; (b) device representation
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-9B Two point data communications circuit: (a) DTE/DCE representation; (b) device representation
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-10 Multipoint data communications circuit using POTS links
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-11 Line control unit UART interface
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-12 UART transmitter block diagram
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. TABLE 4-6 UART Control Register Inputs
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-13A Asynchronous characters: (a) ASCII character; (b) ARQ character; (c) Baudot character
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-13B Asynchronous characters: (a) ASCII character; (b) ARQ character; (c) Baudot character
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-13C Asynchronous characters: (a) ASCII character; (b) ARQ character; (c) Baudot character
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-14 UART transmitter signal sequence
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-15 UART receiver block diagram
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-16 UART receive signal sequence
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-17A Start bit verification: (a) 1X RCP; (b) 16X RCP; (c) valid start bit
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-17B Start bit verification: (a) 1X RCP; (b) 16X RCP; (c) valid start bit
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-17C Start bit verification: (a) 1X RCP; (b) 16X RCP; (c) valid start bit
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-18 16X receive clock rate
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-19A Sampling error: (a) 8X RCP; (b) 16X RCP
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-19B Sampling error: (a) 8X RCP; (b) 16X RCP
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-20 RS-232 serial interface connector: (a) DB25P; (b) DB25S; (c) DB9P; (d) DB9S
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-21 EIA-561 modular connector
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. TABLE 4-7 RS-232 Voltage Specifications
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-22A RS-232 logic levels and noise margin: (a) driver and terminator voltage ranges; (b) noise margin with a +10V high and -10V low; (c) noise violation
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-22B RS-232 logic levels and noise margin: (a) driver and terminator voltage ranges; (b) noise margin with a +10V high and -10V low; (c) noise violation
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-22C RS-232 logic levels and noise margin: (a) driver and terminator voltage ranges; (b) noise margin with a +10V high and -10V low; (c) noise violation
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-23 RS-232 Electrical specifications
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. TABLE 4-8 EIA RS-232 Pin Designations and Direction of Propagation
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. TABLE 4-9 EIA RS-232 Pin Designations and Designations
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-24 RS-232 data timing diagram - ASCII upper case letter A, 1 start bit, even parity, and one stop bit
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-25A Functional block diagram for the drivers and terminators necessary for transmission of asynchronous data over the RS-232 interface between a DTE and a DCE (modem): (a) transmit circuits; (b) receive circuits
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-25B Functional block diagram for the drivers and terminators necessary for transmission of asynchronous data over the RS-232 interface between a DTE and a DCE (modem): (a) transmit circuits; (b) receive circuits
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-26A Typical timing diagram for control and data signals for asynchronous data transmission over the RS-232 interface between a DTE and a DCE (modem): (a) transmit timing diagram; (b) receive timing diagram
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-26B Typical timing diagram for control and data signals for asynchronous data transmission over the RS-232 interface between a DTE and a DCE (modem): (a) transmit timing diagram; (b) receive timing diagram
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. TABLE 4-10a RS-449 Pin Designations (37-Pin Connector)
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. TABLE 4-10b RS-449 Pin Designations (Nine-Pin Connector)
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. TABLE 4-11 RS-449 Category I and Category II Circuits
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. TABLE 4-12 RS-530 Pin Designations
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-27 Data communications modems - POTS analog channel
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-28 Simplified block diagram for an asynchronous FSK modem
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. TABLE 4-13 Bell System Modem Specifications
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. TABLE 4-14 ITU-T V-Series Modem Standards
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. TABLE 4-14 (Continued)
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-29 V.32 constellation diagram using Trellis encoding
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved. FIGURE 4-30 V.33 signal constellation diagram using Trellis encoding
Tomasi Copyright ©2004 by Pearson Education, Inc. Advanced Electronic Communications Upper Saddle River, New Jersey 07458 Systems, 6e All rights reserved.