AREA EFFICIENT CMOS CHARGE PUMP CIRCUITS
Ryan Perigny Un-Ku Moon and Gabor Temes
Conexant Systems, Inc. Department of Electrical and Computer Engineering 3536 JFK Parkway Oregon State University Fort Collins, CO 80525, USA Corvallis, OR 97331, USA
ABSTRACT connections of the n-channel switches are grounded. The p-channel V
switches are in an n-well, which is connected to the well node. This paper describes the operation of three types of charge pump circuits. Power efficiency theory of charge pumps is dis- V cussed. A method of estimating the output ripple of a charge pump well Vout from the size of the capacitors used is described. A new charge Vdd pump circuit that uses two cascoded buffer transistors to improve M M M M Io Cx M 3 124 the area efficiency is proposed. 5 M6 V a V b
Ca C 1. INTRODUCTION b φφ The charge pump [1] is a dc-dc converting circuit used to obtain a 1 2 dc voltage higher or lower than the supply voltage, and/or opposite Figure 1: Conventional 2-capacitor charge pump. in polarity to the supply voltage. Charge pumps are widely used in low-voltage circuits [2], dynamic random access memory circuits
[2], switched-capacitor circuits [3] and EEPROM’s [4]. This circuit uses two clock phases and operates as follows:
M M C
a
Three important issues of on-chip charge pump circuits are during , switches and are turned on and capacitor is
V M M
output voltage ripple, power efficiency and area efficiency. For charged to dd . During , switches and are turned on and
C V C
a dd
most applications, a low output ripple is desired. Large output capacitor b is charged to . Capacitor , which was charged V
ripple degrades the performance of the circuit that the charge pump to dd during the previous clock phase, is now connected between
V V dd
is powering. Charge pumps with very low power efficiency cancel dd and the load, lifting the voltage at the load to . During V the benefit of scaling the supply voltage down and are not desirable every clock cycle, one capacitor is being charged to dd and the
for portable applications. Area efficiency is desirable for many other capacitor is providing the load current.
M M V V
dd applications as smaller chip areas are less expensive to fabricate. Switches and are used to bias w ell to , prevent- For low-noise applications, a very low output ripple is desir- ing latchup from occurring during startup. This method is dis- able to achieve good performance. This paper introduces a new cussed in [5]. charge pump circuit that provides very low output ripple with a smaller amount of capacitance than existing charge pumps, at the 2.1. Non-Filtering Case
cost of a reduced output voltage and reduced power efficiency.
V In this paper, the operation of three types of charge pumps If there is no load current, the output voltage will remain at dd .
will be described. Comparisons between the three charge pumps If there is a significant load current and no added output capacitor
C
with regard to area efficiency, power efficiency and output voltage ( x ), the voltage at the output will ramp down with a slope
I
o
V
of for half of a clock period before it is boosted to dd again. C
ripple will be discussed. a
V In Section 2, the conventional 2-capacitor charge pump will The peak-to-peak voltage ripple at the output, out , can be be described and analyzed. In Section 3, a charge pump that uses calculated as
a buffer transistor to improve the area efficiency will be discussed.
I
o
V
In Section 4, a newly proposed charge pump that uses two cas- out (1)
f C a
coded buffer transistors to further improve the area efficiency will clk f be described. where clk is the clock frequency. If there is an output capacitor, which is the usual case when
a significant current must be provided, the slope of the output is I
2. CONVENTIONAL CHARGE PUMP reduced to o due to the added capacitance at the output node.
C C x This reducesa the ripple. The ripple is now A conventional 2-capacitor charge pump that uses cross-coupled
NMOS transistors [2] is shown in Figure 1. For simplicity, the I
o
V
body/bulk connections are not shown in the figure. The body/bulk out (2)
f C C
a x clk
Special thanks to Mustafa Keskin and Jos«e Silva for their generous A drawback of this circuit is that in order to achieve a very help with this research. small output ripple, a large amount of capacitance is required. For Vdd example, in order to drive a load current of 50 A with a clock Charge Pump 2 frequency of 10 MHz and a desired output ripple of 5 mV, more Vx than 500 pF of capacitance is required. For low-current pumps, ron(M3 ) most of the chip area of a charge pump is due to the capacitor V Cx Ca Vdd bias area, so the area efficiency of a charge pump can be significantly Charge Pump 1 Mbuf
improved by reducing the total capacitance needed to achieve a C Vout desired output ripple. g Power efficiency is an important consideration in charge pump Io Co design. An important cause of power loss in a charge pump is
the charging and discharging of the bottom-plate parasitics of the
C C a
pump capacitors ( and b in the previous example). These par- Figure 2: Single cascode charge pump. V asitics are charged to dd every clock cycle. For the conventional
2-capacitor charge pump shown in Figure 1, neglecting the resis-
V V out
tance of the switches, and assuming that out , and
V M buf
provide around dd at the gate of . Charge pump 1 also
V V out low , the efficiency can be derived as provides the n-well bias voltage for all of the p-channel switches.
Charge pump 2 provides the load current.
I V
o
low
(3)
I V f pC V
o a
dd clk dd 3.1. Non-Filtering Case
Here, p is the ratio of stray capacitance to desired capacitance
C C
C pC
x o a ( p ). This value is determined by the type of capacitors If and are small enough that both of the corner frequencies
used and is usually between 5 and 20%. A good derivation of an are greater than twice the clock frequency, then filtering is negli-
I
o M
equivalent expression for the power efficiency can be found in [5]. gible, and the ripple at the drain of buf will be
f C C
a x
clk
V
as given by (2). The ripple at the output, out , is reduced by the
g r o 2.2. Filtering Case intrinsic gain of the buffer transistor ( m ) and can be shown to be
One way to reduce the capacitance needed to achieve a given out- M
put voltage ripple is to use the on-resistance of transistor and
I
o C
capacitor x as a lowpass filter. This can be achieved by making
V
out (5)
f g r C C
a x
clk
mM oM
M M
buf buf transistors and narrow enough to provide enough resis-
tance to bring the corner frequency of the RC branch below twice M
the clock frequency. Unfortunately, this also lowers the average It is important that the voltage at the drain of buf not drop
V M T
output voltage due to the voltage drop across the switch, but for more than below the voltage at the gate in order to keep buf
I
o
I r V
o T
M
in saturation. This means that on . Thus,
f C
low current and high clock frequency applications the drop in out-
a clk
put voltage may be small.
I
o
C C
The corner frequency of the filter is equal to .If
a a
r C
(6)
min
x
on M
f V I r
T o
clk
onM
this corner frequency is less than twice the clock frequency, then
M
buf V If this condition is violated, becomes biased in the triode
an approximation for the ripple at the output, out can be found
M
buf V
V region and the output resistance of falls off sharply, causing a
by assuming, for simplicity, that the ripple at nodes and b in
I
o f the circuit to be much less effective.
Figure 1 is a sinusoid of frequency clk and amplitude .
f C a If this were the case, the output ripple would be calculatedclk as
3.2. Filtering Case
I
o
V
out (4)
M
f r C C
buf
x a If enough capacitance is added at the drain of or at the out-
onM clk put, the ripple is further reduced due to additional lowpass filtering.
Because the waveform is a ramp (not a sinusoid), the resulting M
Assuming the on-resistance of is large, the ripple at node
ripple amplitude is smaller than the approximation given by (4).
V V x
x in Figure 2, , can be found using (1) to be I
3. SINGLE CASCODE CHARGE PUMP o
V
x (7)
f C
a clk A charge pump circuit that greatly reduces the total capacitance If the corner frequencies of the RC branches of this filter are needed to achieve a given output voltage ripple is reported by Duis- all less than twice the clock frequency, additional filtering occurs, ters and Dijkmans in [6]. A similar circuit is shown in Figure 2 as futher reducing the ripple amplitude.
a simplified schematic. The capacitors shown with boxes around M
The charge pump used to bias the gate of buf introduces them symbolize conventional 2-capacitor charge pumps of the type more bottom-plate losses, which lowers the efficiency. The effi- described in the previous section. This circuit uses a buffer tran- ciency for a single cascode charge pump can be expressed as
sistor and the on resistance of the switch connecting Charge Pump
M
buf V
2 to the drain of to provide additional filtering of the ripple. I
o out
(8)
Charge pump 1 provides the gate voltage for the buffer transis-
I V pf C C V
o a g
dd clk
dd
M M buf
tor buf . Because there is no dc current through the gate of ,
V V V V V
out T T
dd
M where is now equal to ef f ,
the charge pump capacitors need only be large enough to overcome buf
p p
V V V V V
T out GS T
f ef f the leakage from the parasitic gate capacitance of the switches and f , and . V 3.3. Gate Biasing Circuit Charge Pump 3 dd
Vx
M
Because buf acts as a source follower to the output of the single r cascode charge pump, it is important that the gate bias voltage be on(M 3 ) V Cx Ca as stable as possible in order to achieve very low ripple. Although Vdd bias1 Charge Pump 1 M charge pump 1 does not provide any current, there may be a sig- buf1
M Cg1 nificant ripple at the gate of buf caused by clocking glitches. From a power standpoint, the best clocking scheme is to have V
Vdd bias2 Co1
the two clock signals and cross somewhere in the middle Charge Pump 2 Mbuf2 of the voltage range. This minimizes the wasted power due to
leakage currents during the transition period, but also results in Cg2 Vout M
large glitches at the gate of buf . The ripple at this node occurs Io Co2
M C M
a
because when connects to the gate of buf , the voltage
V V a at has not yet reached dd . The ripple at this node can be as much as a few millivolts, which can still increase the ripple at the Figure 4: Double cascode charge pump. output node if very low ripple is desired. We propose a new circuit which provides a much smaller bias voltage ripple with clock signals that overlap in the middle of 4.1. Second Gate Biasing Circuit
the voltage range is shown in Figure 3. The circuit is similar to
M
the conventional charge pump circuit, with the addition of two The circuit used for biasing the gate of buf is shown in Figure
M M
5. This circuit is similar to the modified conventional 2-capacitor
switches and two capacitors. During , switches , and
C V
M charge pump shown in Figure 3, with the addition of two capaci-
g
are turned on and capacitor is charged to dd . During
C C V V
y z g
h
M M M C
tors, and from nodes and to ground. This circuit
, switches , and are turned on and capacitor h is
C V C
g y
dd
C V
V works as follows: when capacitor is charged to , is also
g dd
charged to dd . Capacitor , which was charged to during
V V
dd dd V
V charged to . When the clock rises to , some of the charge gx
the previous clock phase, is now connected between dd and ,
C C
g y
V
V in is shared with , causing the output voltage to be less than gx
lifting the voltage at to dd . During the next clock phase
V C
y
dd
V M
. When drops to zero, the additional charge stored in
gx
( ), is connected to the gate of buf , providing a bias volt-
C
g V goes back into . This is important because it allows a volt-
age of dd .
V
age lower than dd to be provided without any additional power
V loss due to the extra capacitors. The bias voltage bias should be
Vwell
V V M
dd buf
M
no higher than ef f in order to bias in the Vbias buf M buf saturation region. M Vgx V V M 7 dd hx 8 C f
Cgx Chx M3 M12M M4 M5 M6
Vg V h V bias2 Mbuf2 Cg Ch M Vgx2 V Vhx2 M 7 dd 8 C f2 φφ 1 2 C C gx2 M32M1 M M4 hx2 Vg2 Vh2 Figure 3: Modified conventional charge pump to provide the gate
Cy Cg2 Ch2 Cz M voltage for buf . φφ
1 2
V V gx The ripple at nodes and hx is not easily determined, but depends on the rise and fall times of the clocks, the on-resistance Figure 5: Conventional charge pump with added capacitors to ob-
tain the second bias voltage.
M M C C C
gx gx
of switches and , and the size of and hx .If and
C V V
gx hx hx are very small (less than 0.5 pF), the ripple at and
is on the order of tens of millivolts. This is fairly large, but when The output voltage of this biasing charge pump is controlled
C C
y z M
M by the size of (and ) and is given by
these nodes are switched/relayed to the gate of buf through
M
and , the ripple at the output is very small (less than 0.1 mV).
C
g C
A small capacitor, f , also helps to reduce the bias voltage ripple.
V V
dd
bias (9)
C C
g y
4. DOUBLE CASCODE CHARGE PUMP 4.2. Non-Filtering Case
A proposed new charge pump circuit that further improves the area The operation of this circuit is similar to the single cascode equiv-
efficiency of a charge pump is shown in Figure 4. This circuit alent circuit, but the ripple is attenuated by the intrinsic gain of
M includes two cascoded buffer transistors, a third charge pump and buf and another filter branch.
an additional output capacitor. Charge pump 1 provides a bias In order for the third branch to filter effectively, the corner fre-
g
m M
buf
V M
buf
voltage of dd to . Charge pump 2 provides a lower gate quency, , must be less than twice the clock frequency.
C
o
M
voltage for transistor buf in order to bias it in the saturation If the on-resistance of the p-channel switches in charge pump
I
o
M
region. Charge pump 3 provides the load current. 3 is small, the ripple at the drain of buf will be
f C C
a x clk
I
o
V
out (10)
f g r g r C C
a x
clk
mM oM mM oM
buf buf buf buf
0 as given by (2). If a small amount of capacitance is used, so that 10 no filtering occurs, the ripple at the output is reduced by the prod- Conventional
−1
10
M M
buf
uct of the intrinsic gains of buf and . The ripple at the
V output, out , for a double cascode charge pump with no filtering Single Cascode −2 is easily determined and is shown in (10) at the top of the page. 10
−3 4.3. Filtering Case 10 Ripple (V) Double Cascode If the on-resistance of the p-channel switches in charge pump 3 is −4
10
V V x
relatively large (to provide filtering), the ripple at node x , , I
will be o as given by (1).
f C a clk −5 10 Treating the three filter branches as separate single-pole filters 35 40 45 50 55 60 65 70 75 80 Efficiency (%)
and assuming that the corner frequencies of all of the branches are
f well below clk , an approximation for the ripple at the output for
the filtering case can be found. The net result is a dramatically Figure 6: Efficiency vs. ripple for different charge pump circuits
I C p f
o clk
attenuated ripple amplitude. without filtering ( =100 A, total =30 pF, =5%, =10 MHz,
V jV j V V
T
dd ef f
M =1.65 V, =0.55 V, T 0.7 V, =0.2 V). The charge pump used to bias the gate of the second buffer buf transistor introduces additional bottom-plate losses, but because 0
10 C
the capacitors used in this charge pump are small compared to a C and b , this power loss may be tolerable. The power efficiency of
−1 the double cascode charge pump is given by 10 Conventional
−2
10
I V
o out
(11) Single Cascode
I V pf C C C V
o a g g
dd clk
dd −3 10
Ripple (V)
V V V V V
out T
dd
M ef f M
where ef f ,
buf buf
−4
p p
10
V V V V V V
T T out GS T
f ef f f , and . Double Cascode
−5 10 35 40 45 50 55 60 65 70 75 80 5. CONCLUSIONS Efficiency (%)
Figure 6 shows a plot of output ripple vs. efficiency for all three Figure 7: Efficiency vs. ripple for different charge pump circuits
charge pumps where no filter is used. This plot was generated from
I C p f
o clk with filtering ( =100 A, total =30 pF, =5%, =10 MHz,
multiple transistor level simulations. This shows that as buffer
V jV j V V
T
dd ef f
M =1.65 V, =0.55 V, T 0.7 V, =0.2 V). transistors are added to the circuit, the maximum efficiency de- buf creases, but the ripple gets much smaller due to the intrinsic tran- sistor gain for each stage that is added, regardless of the total ca- 6. REFERENCES pacitance or clock frequency that is used. The relationship between output ripple and efficiency for the [1] J. Dickson, ”On-chip high-voltage generation in MNOS integrated cir- case where filtering is used is shown in Figure 7. For the filtering cuits using an improved voltage multiplier technique,” IEEE Journal case, the difference in minimum ripple between the three charge of Solid-State Circuits, vol. SC-11, pp. 374-378, June 1976. pumps is much larger, and is dependent on how much total capac- [2] Y. Nakagome et al., ”An experimental 1.5-V 64 Mb DRAM,” IEEE itance is used. If more capacitance were used, the curves would be Journal of Solid-State Circuits, vol. 26, pp. 465-472, April 1991. farther apart, and if less capacitance were used, the curves would [3] T. Byunghak and P. Gray, ”A 10 b, 20 Msample/s, 35 mW pipeline be closer together. A/D converter,” IEEE Journal of Solid-State Circuits, vol. 30, pp. 166- This new charge pump circuit is more area-efficient than the 172, March 1995. single cascode charge pump, at a price of reduced headroom (thus [4] J. Witters, G. Groeseneken and H. Maes, ”Analysis and modeling of lower power efficiency). The size of ripple that can be tolerated on-chip high-voltage generator circuits for use in EEPROM circuits,” IEEE Journal of Solid-State Circuits, vol. 24, pp. 1372-1381, October seems to be the most important factor in determining which charge 1989. pump to use for a given application. For example, if power effi- ciency is the biggest concern and a larger output ripple can be toler- [5] P. Favrat, P. Deval and M. J. Declercq, ”A high-efficiency CMOS volt- age doubler,” IEEE Journal of Solid-State Circuits, vol. 33, pp. 410- ated, either a single cascode or a conventional charge pump would 416, March 1998. be a good choice. The double cascode circuit would be especially [6] T. Duisters and E. C. Dijkmans, ”A -90 dB THD rail-to-rail input useful for applications where power efficiency is less critical and a opamp using a new local charge pump in CMOS,” IEEE Journal of very low output ripple is desired. Solid-State Circuits, vol. 33, pp. 947-955, July 1998.