On Ambient Intelligence, Needful Things and Process Technologies
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On ambient intelligence, needful things and process tech nologies C.J. van der Pael*, F. Pessolano, R.Roovers, F.Widdershoven, G. van de Walk, E. Aarts and P Christie Philips Research The ongoing miniaturization of electronic circuits and responsive to the presence of people. Such an the corresponding exponential increase in embedded environment should be computational power is reaching the point where it - Ubiquitous: surrounding the user by a multitude of becomes viable to integrate electronics into people interconnected systems environments. Ambient Intelligence pasten] refers to - Transparent: integrated and “hidden” into the an electronic environment that is sensitive and background . Intelligent: adapting to the people that Live in it The potential to distribute functionality over a network of devices is determined by the power resources of the device and upon considering these demands it appears helpful to further classify in-home Ambient Intelligence “devices” into three distinct classes illustrated in figures 1 and2. - The “watt-node”, taking care of the major information processing computational intensive tasks, e.g. 3D TV at high data rates, networked games etc: a mains connected ‘static’ device; the power is limited by package cost (a few Watts for traditional consumer products to 100 Watts for PC Figure 1: In Home AI nodes like devices with ._6 COrnmunEaton ratebps ,G canputingops ____ 1mW 1w Power Figure 2: AI Power nodes *) carel.van.der.poelCphilips.com 3 0-7803-8480-6104/$20.00BZW IEEE - The “milli-watt-node”, representing low power some educated guessing on markets and production processing, Computational Efficient [de Man I, costs. mobile, personal and connected (audio /video) The result of such an analysis is depicted in figure 4, devices in the home. These are portable devices where the number of future applications is given per with a rechargeable battery; the power is linuted by process node (from 0.12um till 0.045um). Let’s battery technology. consider the standard industrial case, where we choose - The “micro-watt-node”, representing a multitude of the process node in order to minimize costs only for a “electronic dust” devices that perform given an application requiring a given performance. environmental tasks like sensing, identification, This is illustrated in figure 4a. Obviously, future positioning, etc. These are autonomous devices applications have been identified that require advanced powered by energy scavenging or lifetime battery technologies like 0.045um. However, their number is decreasing. In a different scenario, where more It is envisaged that each of the three classes represents advanced technologies also provide a reduction in about equivalent “in-home” Si-area. In this paper we power by means of combined technology scaling and try to map the system needs associated with these circuit design, power-limited applications (e.g. for nodes, differing by orders of magnitude with respect to mobile devices) would find their optimal node in a the amount of information to be processed as well as more advanced CMOS technology (see fig 4b). the available power, onto requirements for Si process technology choices. Watt Node: digital technology As electronics the industry gets more mature, and technology development and deployment increasingly expensive and complex, the necessity of following Moore’s law is starting to be doubted. Furthermore, the expected next deep sub-micron technologies (0.065um 0.12 0.09 0.065 c=0.045 Process Node Figure 4 Application distribution per process node minimidng (a) mainly costs, (b) cods and power, This is, of course, valid in case technology indeed is capable of providing a power reduction. Such assumption is so far true till 0.090um. At the same time, we are showing that the next process nodes should be developed with more focus on power: power and not 0” 01 02 01 04 05 a6 07 0.8 09 IO I., Nod: (urn) speed should drive technology development. We can take this analysis a step further so as to assess Moore’s Figure 3: Si Area Price trend vs ITRS node law timing. and 0.045um) seem unable to provide further leaps in The case for 0.065um technology is described in figure performance, while costs are steadily growing (figure 3) 5. The ITRS roadmap expects this technology available A simple question thus arises: do we need advanced in 2007. If we look at the introduction time for technology and, if so, in what form? applications that would use this process node if We try to answer such an apparently trivial question by developed in the traditional way (referred to as ITRS- not restating Moore’s law, but looking at it from based - Fig sa), we can observe a gap of 2 years before another angle: the future applications themselves. Even the technology is used. When repeating the analysis for if with some approximation, we can already peek into 0.045um a 4-year gap results. If the 0.065um node were the future by analyzing industry and academic developed with power as main optimization factor, the roadmaps for the next 15 years. Based on these technology would he required from industry already in roadmaps, we have made a first assessment of the 2004 (figure 5b). required performance, system architecture and, with 4 and multi-gate device architectures appear to be needed for viable solutions to many of the leakage current and drive strength limitations of classically scaled poly- Si/SiOz devices. A similar argument holds for the rapid development of additional embedded functionality options like Flash, RF/Analog and Power. These are not just incremental improvements over existing approaches and our challenge is to explore in an early phase the impact of these new technology choices on system-level performance at the level of standard cell arrays (-100k cells) and embedded memory blocks (-1Mb). 2004 2005 2006 2007 2008 2009 2010 2011 2012 Due to the uncertainties associated with the validity of different performance metrics in different system-level Figure 5: Application introduction yean for 0.06Sum (a) with scenarios, technology assessment is performed using a standard lTRS.based and (b) power-bared technology development. virtual design flow called PSYCHIC (Parameuic System-level Characterization of Integrated Circuits), From these observations, we can conclude that modeled on the Philips SoC Design Environment, see technology pace is too high if development overlooks Figure 6. power, while it would be too slow when optimized for We begin by defming target lor specifications and use power. front-end TCAD process simulators to design candidate When this is true, power would he also the main reason devices architectures within each of the technology that keeps Moore’s law still valid, as the technology options which meet the specifications, where possible development pace would be just enough to satisfy the (see Figure 7). Generally, we use the “classical” low- demand. Most applications of the future will require power poly-siliconlnitr-ided oxide device with a supply some mix of technologies, ranging from pure digital voltage of 1.2 V as the reference device and use this CMOS to sensors, which will render digital CMOS the device to determine the I,, current specifications. less blocking part of the technologies involved in the Different device technologies are then mapped on to system of the future. these reference le and I,, specifications of the classical reference device by allowing the supply voltage to vary. Virtual Technology Chain In the case of double gate devices, for example, the The trend in front-end technology development is greater channel control allows the specifications to be unmistakably in the direction of increasing number of met by a dramatically reduced supply voltage if just process options, with multiple threshold voltages and 0.76V. low-power, general purpose, and high-performance To allow the device technologies to be assessed within application domains being offered at the 65nm node. complex system-level environments, the TCAD process The situation at the 45nm node is likely to he even more diverse since metal gate, high-k gate dielectric, v,l.2vselr I, Figure 7: Front End Technology Mapping with Lgate (Physiral)=45 nm, CET (nitrided oxidel=Z.S nm simulator is used to extract timing and power matrices Figure 6 Closing the Loop on System Level suitable for use in the standard design flows of ASIC technology exploration. 5 cell libraries and memory cells. This requires that we based on so-called Rentian wire length distribution. embed the devices within an appropriate cell layout. Using a range of wiring signature parameters extracted Both logic and memory cells are designed using from a wide range of Pbilips circuit layouts, we have lithographically driven design methods in order to developed a scalable model of the wire length ensure manufacturability under a variety of optical tool distribution produced by commercial placement tools. scenarios. By regularizing the layout style to reduce the This wire length distribution is allocated to individual spatial bandwidth, it is possible to achieve a much more wiring layers using a pseudo-routing method, where the manufacturable cell library and reduce the necessity of shortest wires of the distribution are allocated to the expensive optical assist features, such as phase-shifting lowest wiring layers, and successively longer wires are masks. Our analysis has shown that these techniques allocated to higher layers, taking into account have minimal impact on overall cell array area, timing, inefficiencies in the routing algorithm, and the routing or power. resources required by clock and power distribution. Once an appropriate cell layout style has heen Benchmark critical paths can he connected by sampling determined, the TCAD process simulators can be used the required connecting wires from the pseudo-placed to extract timing and power matrices to be used within and pseudo-routed wire length distribution in each system-level benchmark performance simulations.