SMOMAPL138B-HIREL Low-Power Applications Processor Datasheet

SMOMAPL138B-HiRel www.ti.com SLVSAQ9B –JANUARY 2011–REVISED JULY 2013 SMOMAPL138B Low-Power Applications Processor Check for Samples: SMOMAPL138B-HiRel

1 SMOMAPL138B Low-Power Applications Processor 1.1 Features

123 • Highlights – Compact 16-Bit Instructions – Dual Core SoC • C674x Two Level Cache Memory Architecture • 375-MHz ARM926EJ-S™ RISC MPU – 32K-Byte L1P Program RAM/Cache • 375-MHz C674x Fixed/Floating-Point VLIW – 32K-Byte L1D Data RAM/Cache DSP – 256K-Byte L2 Unified Mapped RAM/Cache – Enhanced Direct-Memory-Access Controller – Flexible RAM/Cache Partition (L1 and L2) (EDMA3) • Enhanced Direct-Memory-Access Controller 3 – Serial ATA (SATA) Controller (EDMA3): – DDR2/Mobile DDR Memory Controller – 2 Channel Controllers – Two Multimedia Card (MMC)/Secure Digital – 3 Transfer Controllers (SD) Card Interface – 64 Independent DMA Channels – LCD Controller – 16 Quick DMA Channels – Video Port Interface (VPIF) – Programmable Transfer Burst Size – 10/100 Mb/s Ethernet MAC (EMAC): • TMS320C674x Floating-Point VLIW DSP Core – Programmable Real-Time Unit Subsystem – Load-Store Architecture With Non-Aligned – Three Configurable UART Modules Support – USB 1.1 OHCI (Host) With Integrated PHY – 64 General-Purpose Registers (32 Bit) – USB 2.0 OTG Port With Integrated PHY – Six ALU (32-/40-Bit) Functional Units – One Multichannel Audio Serial Port • Supports 32-Bit Integer, SP (IEEE Single – Two Multichannel Buffered Serial Ports Precision/32-Bit) and DP (IEEE Double • Dual Core SoC Precision/64-Bit) Floating Point – 375-MHz ARM926EJ-S™ RISC MPU • Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks – 375-MHz C674x VLIW DSP • Supports up to Two Floating Point (SP or • ARM926EJ-S Core DP) Reciprocal Approximation (RCPxP) – 32-Bit and 16-Bit (Thumb®) Instructions and Square-Root Reciprocal – DSP Instruction Extensions Approximation (RSQRxP) Operations Per – Single Cycle MAC Cycle – ARM® Jazelle® Technology – Two Multiply Functional Units – EmbeddedICE-RT™ for Real-Time Debug • Mixed-Precision IEEE Floating Point • ARM9 Memory Architecture Multiply Supported up to: – 16K-Byte Instruction Cache – 2 SP x SP -> SP Per Clock – 16K-Byte Data Cache – 2 SP x SP -> DP Every Two Clocks – 8K-Byte RAM (Vector Table) – 2 SP x DP -> DP Every Three Clocks – 64K-Byte ROM – 2 DP x DP -> DP Every Four Clocks • C674x Instruction Set Features • Fixed Point Multiply Supports Two 32 x – Superset of the C67x+™ and C64x+™ ISAs 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per – Up to C674x MIPS/MFLOPS Clock Cycle, and Complex Multiples – Byte-Addressable (8-/16-/32-/64-Bit Data) – Instruction Packing Reduces Code Size – 8-Bit Overflow Protection – All Instructions Conditional – Bit-Field Extract, Set, Clear – Hardware Support for Modulo Loop – Normalization, Saturation, Bit-Counting Operation 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2TMS320C6000, C6000 are trademarks of Texas Instruments.

3ARM926EJ-S is a trademark of ARM Limited.

PRODUCTION DATA information is current as of publication date. Products conform to Copyright © 2011–2013, Texas Instruments Incorporated specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. SMOMAPL138B-HiRel

SLVSAQ9B –JANUARY 2011–REVISED JULY 2013 www.ti.com

– Protected Mode Operation • USB 2.0 OTG Port With Integrated PHY (USB0) – Exceptions Support for Error Detection and – USB 2.0 High-/Full-Speed Client Program Redirection – USB 2.0 High-/Full-/Low-Speed Host • Software Support – End Point 0 (Control) – TI DSP/BIOS™ – End Points 1,2,3,4 (Control, Bulk, Interrupt or – Chip Support Library and DSP Library ISOC) Rx and Tx • 128K-Byte RAM Shared Memory • One Multichannel Audio Serial Port: • 1.8V or 3.3V LVCMOS IOs (except for USB and – Two Clock Zones and 16 Serial Data Pins DDR2 interfaces) – Supports TDM, I2S, and Similar Formats • Two External Memory Interfaces: – DIT-Capable – EMIFA – FIFO buffers for Transmit and Receive • NOR (8-/16-Bit-Wide Data) • Two Multichannel Buffered Serial Ports: • NAND (8-/16-Bit-Wide Data) – Supports TDM, I2S, and Similar Formats • 16-Bit SDRAM With 128 MB Address – AC97 Audio Codec Interface Space – Telecom Interfaces (ST-Bus, H100) – DDR2/Mobile DDR Memory Controller – 128-channel TDM • 16-Bit DDR2 SDRAM With 512 MB – FIFO buffers for Transmit and Receive Address Space or • 10/100 Mb/s Ethernet MAC (EMAC): • 16-Bit mDDR SDRAM With 256 MB – IEEE 802.3 Compliant Address Space – MII Media Independent Interface • Three Configurable 16550 type UART Modules: – RMII Reduced Media Independent Interface – With Modem Control Signals – Management Data I/O (MDIO) Module – 16-byte FIFO • Video Port Interface (VPIF): – 16x or 13x Oversampling Option – Two 8-bit SD (BT.656), Single 16-bit or Single • LCD Controller Raw (8-/10-/12-bit) Video Capture Channels • Two Serial Peripheral Interfaces (SPI) Each – Two 8-bit SD (BT.656), Single 16-bit Video With Multiple Chip-Selects Display Channels • Two Multimedia Card (MMC)/Secure Digital (SD) • Universal Parallel Port (uPP): Card Interface with Secure Data I/O (SDIO) Interfaces – High-Speed Parallel Interface to FPGAs and Data Converters • Two Master/Slave Inter-Integrated Circuit (I2C Bus™) – Data Width on Each of Two Channels is 8- to 16-bit Inclusive • One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address/Data Bus For High Bandwidth – Single Data Rate or Dual Data Rate Transfers • Programmable Real-Time Unit Subsystem – Supports Multiple Interfaces with START, (PRUSS) ENABLE and WAIT Controls – Two Independent Programmable Realtime • Serial ATA (SATA) Controller: Unit (PRU) Cores – Supports SATA I (1.5 Gbps) and SATA II (3.0 • 32-Bit Load/Store RISC architecture Gbps) • 4K Byte instruction RAM per core – Supports all SATA Power Management Features • 512 Bytes data RAM per core – Hardware-Assisted Native Command • PRU Subsystem (PRUSS) can be disabled Queueing (NCQ) for up to 32 Entries via software to save power – Supports Port Multiplier and Command- • Register 30 of each PRU is exported from Based Switching the subsystem in addition to the normal R31 output of the PRU cores. • Real-Time Clock With 32 KHz Oscillator and Separate Power Rail – Standard power management mechanism • Three 64-Bit General-Purpose Timers (Each • Clock gating configurable as Two 32-Bit Timers) • Entire subsystem under a single PSC • One 64-bit General-Purpose/Watchdog Timer clock gating domain (Configurable as Two 32-bit General-Purpose – Dedicated interrupt controller Timers) – Dedicated switched central resource • Two Enhanced Pulse Width Modulators • USB 1.1 OHCI (Host) With Integrated PHY (eHRPWM): (USB1)

2 SMOMAPL138B Low-Power Applications Processor Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: SMOMAPL138B-HiRel SMOMAPL138B-HiRel www.ti.com SLVSAQ9B –JANUARY 2011–REVISED JULY 2013

– Dedicated 16-Bit Time-Base Counter With outputs Period And Frequency Control – Single Shot Capture of up to Four Event – 6 Single Edge, 6 Dual Edge Symmetric or 3 Time-Stamps Dual Edge Asymmetric Outputs • 361-Ball Plastic Ball Grid Array (PBGA) – Dead-Band Generation [GWT Suffix], 0.80-mm Ball Pitch – PWM Chopping by High-Frequency Carrier • Commercial, Extended or Industrial – Trip Zone Input Temperature • Three 32-Bit Enhanced Capture Modules • Community Resources (eCAP): – TI E2E Community – Configurable as 3 Capture Inputs or 3 – TI Embedded Processors Wiki Auxiliary Pulse Width Modulator (APWM)