1984 Annual Report

1984 ANNUAL REPORT COOPERATIVE RESEARCH SEMICONDUCTOR RESEARCH CORPORATION Member Companies AT&T Technologies, Incorporated Advanced Micro Devices, Incorporated Burroughs Corporation Control Data Corporation Digital Equipment Corporation E.I. du Pont de Nemours & Company E-Systems, Incorporated Eaton Corporation GCA Corporation GTE Laboratories, Incorporated General Electric Company COOPERATIVE General Instrument Corporation RESEARCH General Motors Corporation Goodyear Aerospace Corporation Harris Corporation Hewlett-Packard Company Honeywell, Incorporated IBM Corporation Intel Corporation Eastman Kodak Company LSI Logic Corporation Monolithic Memories, Incorporated Monsanto Company Motorola, Incorporated National Semiconductor Corporation The Perkin-Elmer Corporation RCA Corporation Rockwell International Corporation SEMI, Chapter* Silicon Systems, Incorporated Sperry Corporation Texas Instruments Incorporated *The following companies are included in the Semiconductor Union Carbide Corporation Equipment and Materials Institute, Inc., CHAPTER: Micrion Varian Associates, Incorporated Corporation; Micronix Corporation; Pacific Western Westinghouse Electric Corporation Systems, Inc.; Probe-Rite, Inc.; Pure Aire Corporation. Xerox Corporation The Semiconductor Research Corporation is a consortium of US. companies having a common interest in accelerating the progress of research in semiconductor technology, broadening the university base, and increasing the supply of qualified personnel for the industry. In February, 1982, articles were filed incor- porating the SRC as a nonprofit organization to “conduct research which will include scientific study and experimentation directed toward increasing knowledge and understanding in the fields of engineering and physical sciences related to semiconductors.” The SRC asses- ses its members’ needs for research, develops strategies to meet these needs, and funds research that is consistent with these strategies. The goals of the research are aimed at providing an advanced science and technology base leading to development efforts and subsequent industrial use. Beyond these research goals, the SRC has a major responsibility for transferring research results to its member companies and in helping the United States maintain a lead in information technology. Although the technical program is primarily conducted at academic institutions, the SRC’s charter provides for undertaking exploratory and advanced development programs where and when appropriate to its goals and its members’ needs. The SRC is currently supported by 40 U.S. companies who are either suppliers or users of integrated circuits, or vendors of material or equipment to the industry. The SRC’s Board of Directors is elected by the Semiconductor Industry Association and consists of execu- tives from member companies. Two special advisory groups complement the board. The Technical Advisory Board, having representation from each member company, provides the Board and President with a continuing industrial perspective on the research program. The University Advisory Committee, drawn from senior faculty of representative U.S. universities, provides counsel on university relations, policies and practices.

— SRC Research, Microelectronics Center of N.C. GEORGE M. SCALISE Chairman, Board of Directors

The SRC has completed its second full year of research funding. Having been involved since its inception, I have gained great personal satisfaction in the growth from the original eleven firms to the current 40. But even more significant, I have seen and felt the effects of the SRC on the university research community and on our industry. Two years is a very short time for a still relatively small operation to make this kind of impact. Through cooperative R&D, we are achieving together what we could not do separately! The SRC was conceived as the U.S. semiconductor industry’s response to the challenge of concerted national research efforts in other countries. Never has that challenge been greater. Since the SRC’s formation in 1982, the share of the worldwide semiconductor market held by Japanese companies has increased from 33 percent to 37 percent. Worldwide market share for U.S. companies has dropped from 57 percent to 54 percent. In selected segments, such as memory, the picture is much worse. It is an ominous trend. One of the strengths of U.S. manufacturers in worldwide semiconductor trade competition has been our ability to innovate. And it is imperative that we maintain that innovator’s edge. However, the industrial community must take full responsibility for taking that innovation into our factories and to market rapidly. While we must be aggressive in putting new technology to use, we must be patient in terms of our expectations from long-term research. The research we support looks far into the future. Its purpose is preservation of our species. We cannot, and should not, expect short-term miracles. It is also important to remember that we are getting a combination of research results and highly trained manpower. If we wanted either one alone, we would have done it another way. Although not discussed in this report, a large amount of effort was expended by the SRC technical staff in preparation of an industrial research initiative: Project Leapfrog. For a variety of reasons this ambitious program was not initiated in 1984. We are continuing to evaluate options that would allow us to address this type of effort without dilution of our university research program. I would like to share with you my vision of 1995 and the effects the SRC will have had on our industry by that time.

The US. semiconductor industry will cross the $100 billion/year level. This industry will be using many of the devices, processes, concepts, and software that are currently being researched through SRC contracts. Over 3,000 professionals who were supported by SRC-sponsored research will be employed in our industry, actively producing products and developing new ones. At least 50 universities will be producing highly qualified undergraduate and graduate microelectronic engineers and scientists, at least 20 of which would not be involved except for SRC support. Over 1,000 graduate students and 300 faculty will be engaged in SRC research. The SRC scheme of cooperative research will have been emulated by other industries, and a majority of their academic support will flow through such cooperatives. The government will recognize the role of the research cooperative and will funnel increasing percentages of its research funds through these industry-directed efforts.

I would solicit your help in continuing to provide the SRC with the necessary resources to make this happen, We are a cyclical industry, but we must not let short-term influences determine our long-term future. I know that we are capable of meeting the challenge. LARRY W. SUMNEY President

The forty companies that comprise the current SRC membership represent the bulk of U.S. capability in integrated circuits and their application. These companies belong to the SRC for a variety of reasons. All of our members recognize the decline in U.S. competitiveness and the need for changes in the way we do business — like cooperative R&D. Even the U.S. Government’s Office of Technology Assessment is questioning who will fill the role of a surrogate national laboratory for microelectronics and information technology. Many members with small research organizations, concentrating on near-term products, recognize the need to invest in a longer range program. Others with significant internal R&D efforts regard the growth of university faculty and a continuing stream of qualified graduate students as a major interest. Still others emphasize directing the attention of the academic community to areas such as manufacturing which have been traditionally neglected. Trading off these various interests at current budget levels involves quite a balancing act. In 1983, the Board of Directors encouraged us to begin to broaden this country’s university base in microelectronics by funding research at schools that do not yet have an established reputation in this field. This was supported by our University Advisory Committee, and today we have contracts at 16 schools in this category. This is necessary if we are to have students needed for industry and the faculty necessary to train them. These seed efforts have resulted in significant leveraging of our funds through grants by federal and state agencies — as much as 3:1 in some cases. At the same time, we see the need to concentrate programs requiring state-of-the-art capital equipment at major centers where costs can be shared and the faculty exceeds a critical threshold size. You will note in this year’s report, a continuing change in emphasis and direction in some of our programs as problems are solved, priorities shift, and new opportunities arise. Next year will see increased emphasis on manufacturing and process research — fields in which the universities must become more involved. The growth in understanding between industry and university that is occurring as the result of interaction among our members, faculty and graduate students is most rewarding. Except in a few instances such as national defense and space, the United States has been relatively ineffective in mobilizing the academic community. I feel that through the SRC we are beginning to demonstrate that industry and academia can work together on solutions that are crucial for the economic survival of the commercial U.S. integrated circuit industry. Various government agencies have expressed an interest in an appropriate relationship with the SRC. Although nothing is solidified, I would expect this situation to be resolved in the coming year. It is also heartening to note that several of the recommendations of the President’s Commission on Industrial Competitiveness describe the type of cooperation embodied in the SRC. In 1982, an estimated $70 million was provided to universities for integrated circuit research but only $7 million was associated with silicon — the backbone of our industry. In 1984, we estimate that $23 million will be spent on silicon research at universities, more than half of which is supplied directly by the SRC. The SRC is beginning to make a difference!

Photo Courtesy of General Electric Company 1984 Research Funding Microstructure Sciences $5,801,574 Manufacturing Sciences $3,544,888 Design Sciences $3,974,845

— SRC Research, University o f California a t Santa Barbara RESEARCH

“Setting Long-Term Goals On a more quantitative level these For The Semiconductor goals read; “by 1994 we shall be Industry” able to:” T h e U.S. semiconductor/ computer industry has established increase complexity 250 fold the SRC as the organization through increase performance 10,000 fold which it sets research goals and decrease cost/gate 500 fold future directions of the technology. maintain chip reliability of no This is accomplished jointly by the more than one failure in 10 million SRC Technical Advisory Board, its hours. working committees, and the SRC technical staff. These directions are These goals must be reached then translated into relevant uni- with full consideration given to the versity research programs by the additional factors of capital costs SRC which subsequently monitors per unit area of silicon, wafer and guides the research progress, throughput and automation, dispos- interprets and disseminates the ability of reaction products, defect resultant scientific information and, introduction, stability of processes, where applicable, transfers tech- safety, and increasing wafer size. nology to the member companies through appropriate vehicles. Starting in 1982 with a budget of $6 million, the research program has expanded in scope and direction. In 1984, over fifty research contracts totaling $12 million were in place at 37 universities. Currently, more than 180 faculty and 400 graduate students are involved in SRC contracts. The program addresses needs for improved performance and higher density integrated circuits with increased reliability, designed in short cycles to be free or tolerant of faults, easily tested, and produced by control- lable manufacturing processes at acceptable costs. Pseudo Three-Dimensional Display of EBIC Image of IC Sructure —SRC Research, University of North Carolina

— SRC Research, University o f California a t Santa Barbara MICROSTRUCTURE SCIENCES

Goals micrometer minimum feature size MOS dielectric. The devices have a leakage Microstructure Sciences research transistors have been fabricated. current dependent on gate voltage due to encompasses materials, phenomena, Device models have been formulated field-enhanced emission. which include the effects of ballistic devices, circuits, and techniques re- High-Speed Bipolar Devices quired to achieve the industry’s 1994 transport in short-channel devices. complexity and performance goals: Selective deposition of tungsten by Although CMOS technology is LPCVD has been demonstrated to pro- favored for ULSI circuits, bipolar tech- 2 x 107 transistors/cm2 duce high-quality Schottky diodes suit- nology remains important for high- 50 pico seconds logic gate delay able to fabricate latchup-free CMOS. performance analog and high-speed digital applications. For CPU applica- 5 femtojoules power-delay product MoSi2 and WSi2 deposited from hot- tions, package design can accommo- 16-bit analog-digital converter at wall CVD reactors, and SiO2 and SiO 100 MHz. films produced from ion cluster beams, date the power dissipation require- have been shown to have acceptable ments of emitter-coupled logic circuits. These goals are being addressed film quality. A new protonic interface Logic circuits that combine CMOS through a major effort on the identi- trap has been discovered and identi- FET’s with bipolar transistors can fication and solution of key problems fied, and an ion implantation process operate at subnanosecond speeds but limiting the development of a 0.25 has been developed and characterized only dissipate the fractional milliwatt micrometer CMOS technology, and which inhibits the lateral encroachment power level of CMOS. Bipolar totem through four complementary efforts on of silicide in small silicide contact areas. pole drivers, fully oxide-isolated with optical interconnect, multilayer inte- Integration of these important elements sidewall base contact and polysilicon grated circuits, high-speed submicron into a total CMOS process will begin in emitters, can drive the off-chip capaci- bipolar technology, and III-V high elec- the coming year. tive loads. Polysilicon emitter research is underway, and additional projects in tron mobility transistor/heterojunction Optical Interconnects bipolar integrated circuits. Feature size bipolar/CMOS and high-speed bipolar A potential solution to both interchip will continue to decrease, four levels of technology are planned. and intrachip communications delay is interconnect will be required, and new optical interconnect. Ill-V light emitters I I I-V Digital Devices concepts will be needed to overcome and silicon photodetectors integrated Ill-V technology, in addition to its the circuit speed limitation imposed by on the silicon wafer are one possibility well-known, band structure dependent today’s interconnect technology. with interlevel dielectric acting as an properties of direct band gap optical photon emission and high mobility, 0.25 Micrometer CMOS optical wave guide. MBE and MOCVD techniques are being pursued to fabri- provides a flexibility to build devices CMOS circuits have the inherent using artificially structured material that cate GaxAI1-xAs quantum-well, light- advantages of low-power dissipation, emitting devices on silicon substrates is not available in silicon. Recent improved transfer characteristic, as an optical interconnect source. research in quantum-well lasers and greater resistance to soft errors, and GaAs light-emitting diodes integral with high electron mobility transistors has enhanced noise immunity. Coupled with silicon have been made. taken advantage of these properties. A a manufacturing cost near parity with joint effort between the University of NMOS for advanced complexity ULSI Multilayer Integrated Circuits California at Santa Barbara and Stan- components, CMOS has become the The potential for multilayer integrated ford University is conducting HEMT/ MOS technology of choice for the circuits is being explored in the SRC HJBT device research. The basic differ- VLSI/ULSI era. Device modeling has research program at MIT. The thrust of ence between HEMT and MESFET shown that MOS gate lengths of about the effort is to produce single-crystal devices has been explored in terms of 0.25 micrometer are the practical silicon films on non-crystalline sub- electrostatic potential that causes a scaling limit as contact resistance, strates at low temperature, and to fabri- saturation of the diffusion velocity interconnect delays, and, eventually, cate integrated circuits in these films rather than the drift velocity. A HEMT reliability, will limit further size reduc- using low temperature processes. SPICE model has been developed, and tion The SRC 0.25 micrometer CMOS Although a new method (surface- the use of superlattice structures under research thrust is centered at Cornell energy-driven secondary grain growth) the gate has been investigated to elimi- University, with contributing projects at for producing large crystals has been nate deep levels in the n-AIGaAs barrier Wisconsin, Illinois, Stanford, Colorado developed, it does not appear that layer. MBE growth stop-and-restart State, Arizona, Yale, and Notre Dame usable single-crystal films of sufficient capability has been demonstrated using where particular expertise exists. area in 750-angstrom-thick layers can InAs as a passivating layer. During this past year several key be produced below a temperature of The guidance of the Microstructure processes, models, and fundamental 800°C. P-channel MOSFETS, fabri- Sciences Subcommittee has been physical effects have been elucidated. cated as the second-level transistor of invaluable in the formulation and the A 0.5 micrometer minimum feature size a joint CMOS gate inverter were made review of SRC research programs process employing E-beam patterning using a composite Si3N4 on SiO2 gate during the past year. The research has has been demonstrated, and 0.25 been high quality and productive. Goals The research goals in Design Sciences specify that a chip at 1994 levels of complexity (2 x 108 transistors) should require no more than six man-months of design effort to map from high-level description to error- free layout. In addition, the resulting design must be economically testable to assure less than 1 in 106 rejects. This design productivity goal exceeds current capability by several orders of magnitude, and the design fortestability goal is much more aggressive than the ‘fault coverage’ metrics often used for testability today. A more subjective goal is the development of new architectures that provide enhanced processing and memory capabilities, IC technology is becoming increasingly I/O, and interconnect limited and novel architectures may offer alternative solutions. Workstations having two orders of magnitude more computational power are needed to support design using next generation levels of IC complexity. Moreover, the design process must be moved to higher levels of abstraction in order to increase designer productivity. SRC research in design methods includes work in device and process modeling. physical design, synthesis methods, design verification, design for fault tolerance and testability, and new design concepts for VLSI architectures In 1984, a Request For Pro- posal was issued to expand effort in design concepts.

Photo Courtesy General Electric Company DESIGN SCIENCES

Physical Design Design Synthesis and expensive test procedures. In the The physical design problem is one It has been clear for some time that new SRC Program in Reliable Chip of the most important IC design tasks the designer should enter the design Architectures at the University of since it deals with the placement of process at a higher level in order to Illinois/Urbana-Champaign, several macrocells on the chip and the subse- increase productivity. However, most facets of the design-for-test problem quent interconnection of the macro- past attempts fall short with respect to are being addressed. Tasks include: (1) cells according to a given net list. An both levels of abstraction and density software to automatically generate test effective solution minimizes both the of design. The design automation effort patterns for a wide class of micro- chip area and the length of intercon- at Carnegie-Mellon has several pro- processors, (2) built-in self test for nects between the macrocells and jects that address elements of this microprocessors, (3) fault simulators thereby enhances yield and perform- problem, including: DEMETER, a high- that efficiently evaluate the effective- ance simultaneously. Approximately 15 level design aid for a computer system ness of test procedures, and (4) fault tasks were underway in 1984 in the on a chip; a chip interface synthesis tolerant design procedures for highly SRC Design Sciences research pro- project; MOBY, a module binder that concurrent matrix and signal processor gram across a wide spectrum of algo- associates hardware with data paths; computing arrays. Other research tasks rithms and design styles, Examples ULYSSES, a CAD knowledge-based include: VICTOR II, an automatic test include: TALIB, an NMOS cell layout advisor for tool utilization; and CLEO- pattern generator for digital circuits; system based on knowledge engi- PATRA, a natural language interface PLATEST, a generator of automatic neering principles; algorithms based for circuit simulation. In addition, sev- test patterns and/or self-test circuitry on eigenvalue methods for graph bisec- eral other tasks are underway that for PLA’s; concurrent on-line testing tion; probabilistic search methods for focus on other specialized synthesis schemesfor microprocessors; testable layout using the simulated annealing applications: analog-digital signal pro- CMOS speed-independent circuits; and paradigm; fast and efficient PLA folding cessors; silicon compilation from a new technique called Inductive Fault software; and fundamental channel Boolean equations based on level Analysis that relates physically occur- routing studies. SRC graduate students graph heuristics; UNIGRAFIX, aflexible ring process defects to circuit faults. also contributed to larger projects such graphics interface software system; as MAGIC and BBL.2. The latter two and hardware compilers based on the VLSI Architectures programs are now available to U.S. gate matrix design style. Another major area of research is companies from the SRC Center of novel architectures and applications Excellence in IC/CAD at the University Design Verification for IC technology. Two processor of California at Berkeley. After an IC layout has been com- design projects — CONDEL (CON- pleted, there remains the very impor- current Directly Executed Language Device and Process Modeling tant issue of verifying that the circuit is machine), and MISP, (Multiple Instruc- The need for accurate models for error-free and that it achieves the in- tion stream, Shared Pipeline processor) short channel MOS devices as well as tended functional and performance — are currently being supported. A 20 extraction methodologies to determine goals. SRC research tasks in design nanosecond pipelined floating point parameter values from process meas- verification include circuit simulators processor is being designed using the urements has served to motivate the (BIASlisp, a Lisp-based circuit simu- very dense NORA CMOS Technology. development of the BSIM project at lator; RUBICC, an expert circuit critic), This effort will be expanded in 1985. Berkeley. If one accepts the view that timing simulators, logic simulators (E- This country has a lead in design the actual manufacturing process for Logic), design rule checkers, circuit ex- sciences. The SRC is fortunate to have IC’s is characterized by statistical dis- tractors, and a layout profile predictor involved in its programs a number of turbances that create variations in IC for use in estimating device charac- world-recognized universities and re- device parameters, then analysis tools teristics from process parameters and searchers Universities are an ideal are needed to predict the impact of flow (SIMPL2). Software systems are place to conduct research in design process variability on the circuits’ per- sometimes complemented by the use sciences, and the results of this formance. The FABRICS-II software of hardware accelerators for verifica- research can often be rapidly trans- tool set has been developed at the SRC tion. At Berkeley, a multiprocessor ferred to industry. The dedication of the Center of Excellence in IC/CAD at system has been shown to reduce Design Sciences Subcommittee has Carnegie-Mellon University to allow circuit simulation time relative to a com- contributed in a major way to the effec- evaluation of the impact of process parable single processor system. tiveness of this program. statistics on design. Process models such as those used in FABRICS are Design for Testability also providing impetus to the study of The testing of integrated circuits to optimization methods for both circuit assure that they are fault free to the and manufacturing control system degree required by the 1994 goal set is design. very difficult and may require lengthy MANUFACTURING SCIENCES

Goals Fabrication Technology procedure: a low temperature pre- The purpose of the Manufacturing The core Manufacturing Sciences anneal followed by rapid thermal Sciences research program is to de- research program consists of three annealing. The incorporation of ger- velop a generic technology base that related efforts at the Microelectronics manium during epitaxial growth to addresses the effective use of techni- Center of North Carolina (MCNC), obtain misfit dislocations has been cal, economic, and human resources Stanford University, and the University successfully demonstrated for impurity in optimizing production capabilities for of Michigan. gettering. In the particulate area, meas- integrated circuits at the cost and with The program at Stanford is focused urements have been made in clean the quality required. Because the man- on modeling and simulation of equip- rooms down to 10 nanometer particle ufactuing sciences have not been part ment and unit manufacturing opera- diameters, and current research is of academic research agendas, much tions directed toward the evolution of focusing on the study of particles on effort is required to define and initiate a more efficient CAM/CAF tools and the wafers. research program where none previ- management of yield. The initial year of ously existed. inherent in the program this research has concentrated on Reliability is the development of means to attract automation, micropattern generation A research program directed to the high-quality graduate students and and inspection, etching, device and reliability of submicron integrated cir- faculty to semiconductor manufacturing process modeling, and testing and yield cuits is underway at Clemson Univer- sciences. Packaging and reliability, both modeling. The automation research sity. The three tasks are electromigra- of which suffer from a similar lack of centers on the development of a repre- tion, charge trapping, and electrostatic university attention, are included as sentation language, FABLE, for fabri- discharge. During the initial period of part of the manufacturing sciences cation operations. A sensitive electrical this research, emphasis has been effort. end-point detection method for plasma placed on expanding the university’s The ten-year goals of the SRC Manu- etching has been demonstrated, and a instrumentation and analytical facturing Sciences research program defect reduction scheme for lithogra- capability. are to create manufacturing capabili- phy using successive exposures ties for the 1994 complex chip tech- through different but identical reticules Packaging nologies defined in the microstructure has been developed. A major effort in packaging was sciences program. This requires re- At Michigan, SRC research is di- initiated at the University of Arizona in ducing defect levels to 0.25/cm2, rected to automation of selected semi- 1984. The goal of this work is a com- developing process capabilities and conductor unit operations. Reactive ion puter modeling and simulation scheme automation that enable five-fold im- etching is the initial research for first-level packages based on inter- provements in productivity, and keeping vehicle. In-process sensors, testing, active thermal and electrical consider- capital costs at acceptable levels, The machine vision, expert systems, and ations. Several existing modeling performance of high-speed digital cir- modeling are the subjects of research schemes have been evaluated for their cuits is already limited by packaging during the first year. A thermal imager, applicability to packaging. Particular from both a thermal and electrical an integrated gas flow controller, and emphasis is being placed on the induc- viewpoint, and the goals of 100 watt an automated process cell controller tive switching noise and transmission packages with 400 I/O’s and port•hertz are being developed. line problems in high-speed circuits, products of 1012 are probably conserva- MCNC is integrating a low-tempera- The program at Stanford on enhanced tive. Current levels of reliability with a ture, 1.0 micrometer CMOS fabrication cooling techniques for VLSI produced 250-fold increase in the number of capability. The scaling of vertical doping the first technology transfer for SRC devices/chip must be maintained. profiles and lateral lithographic dimen- research with at least two member sions is being approached through companies proceeding with advanced tasks on shallow junction formation, development activities. Thermal dissi- extrinsic gettering, plasma contamina- pation of 1400 watts/ cm2 was demon- tion and damage, and plasma-assisted strated in silicon through the use of oxidation. The fabrication related re- liquid-cooled microchannels. This work search is addressing the effects of has led to other applications on capil- particulates, CMOS latchup, and pro- lary hold-down of wafers in vacuum cess integration. It has been found that and improved die attach. The Cornell B+ implants are preferred over boron activities on defects in multilayer fluoride ions and that implant chan- ceramics is leading to models for con- neling necessitates precise wafer ori- trolling shrinkage for composites used entation control. Leakage current in in complex packages. A new project on shallow p+/n junctions can be reduced hybrid wafer-scale integration, which significantly by a two-stage annealing involves a silicon wafer as an active package substrate, was initiated at Auburn University. A Packaging Strat- egy Committee composed of experts from twelve member companies has been instrumental in developing a plan for increased university attention to packaging sciences. Five universities will participate in study contracts leading to a major new program in 1985.

Metrology At the University of North Carolina, work with digital scanning electron microscopy has resulted in a new technique (PREBIC) which has been applied to the analysis of current- related phenomena in CMOS devices. The acoustical microscopy project at Minnesota continues to evaluate the utility of this instrument for nondestruc- tive analysis of subsurface VLSI structures. Manufacturing sciences represents the SRC’s biggest challenge. It com- bines the largest need expressed by industry with a major void in academic research to date. It is further compli- cated by the fact that the technical literature does not represent state-of- the-art industry practice, thus dictating a diligent educational and motivational effort by experts from member companies directed to university scientists.

Photo by Tom Tracy; Courtesy o f Advanced Micro Devices, Inc. CAD Simulation of CMOS Inverter Cross Section Using SIMPL-2 — SRC Research, University of California at Berkeley

Photo Courtesy of Eaton Corporation FUTURE DIRECTIONS

Goals processes are brought to the wafer) puting arrays for large chips, high By continuing refocus of established will become increasingly important. The speed/accuracy analog-to-digital con- research thrusts, the SRC is addressing SRC is establishing a thrust to develop version, and new built-in test design the near-term needs of its member an in-situ technology that addresses methods. The SRC is continuing to companies. New thrusts are directed this future need. Research programs expand its initiative in the design con- to longer range research in the ten- employing energy beam processing cepts with research in signal pro- year time frame. Three areas are pre- are underway at Rensselaer Poly- cessing architectures, adaptive associ- sently identified, with funding planned technic Institute, the University of ative memories, and artificial intelli- and initiated: “post-shrink“ silicon Illinois, the University of California at gence engines. devices, in-situ manufacturing, and Los Angeles, The Johns Hopkins Uni- system design concepts. versity, and Columbia University. A time-dependent general model de- “Post-Shrink” Silicon scribing the incorporation of dopants The feasibility of building computing into single-crystal films grown by MBE structures of higher performance and has been developed. Prior to attempting complexity than can be accomplished to fabricate superlattice structures, at the limit of 0.25 micrometer silicon IC growth of laterally uniform CoSi2 on technology has recently been defined silicon by MBE has been achieved. by the SRC in a “Post-Shrink” Silicon Workshop. Through the use of artifici- Design Concepts ally structured materials, systems of Algorithm design, system architec- reduced dimensionality may be fab- ture, concurrency of operation, and ricated which exhibit quantum domain device technology are the major ave- phenomena. Distributed computer arch- nues along which computer science itecture systems, consisting of quantum- and engineering have traditionally pur- coupled oscillator arrays, may then be sued their central goal of increasing envisioned. Principal contributions to computational throughput. In the past, the “post-shrink” thrust are being made algorithm design has sought to develop at Cornell and the University of Cali- better procedures and data structures fornia at Los Angeles. A theory for the that will reduce the time to solve specific band structure of two-dimensional (pat- problems on a given computing system; terned), ultra-small, periodic superlat- concurrency of operation has sought tice structures has been developed; to achieve a better utilization of avail- and, three-terminal device structures able resources by overlapping activities based on a superlattice construct have that use disjoint parts of the computing been conceived. Additional projects system; device technology has ad- are planned. vanced along the traditional lines of reducing the minimum geometries; and, In-Situ Processing system architecture has constructed As the sophistication of computer- the hardware resources to optimize the aided design tools for the rapid design system for classes of algorithms. of integrated circuits and integrated Increasing complexity and design capa- circuit complexity increases, a greater bility mean that architectures specific portion of the circuits manufactured to a given algorithm are affordable will be custom designs. Artificial intelli- through custom design. Recognizing gence applications that require several this, the SRC has initiated a thrust to orders of magnitude more logic and investigate and develop advanced arch- memory than provided by the current itectures that will address identified generation of custom designs and future applications. accelerators can be identified. This In late 1984, the SRC began a search use of custom circuits impacts the for innovative design concepts for the approach for future manufacturing ULSl/VLSI generation of technology systems; i.e., high-yield, short-cycle- by issuing a Request for Proposal to time fabrication (based on in-situ pro- the university community. As a conse- cessing in which the wafer is main- quence of this solicitation, new re- tained in a stable environment and search will be started in 1985 in com- OUTREACH

Goals special interests. Opportunities for Technology Transfer Courses The activities of the SRC are pro- additional mentors will continue to grow The product of research is under- viding an opportunity for technical pro- as the research program expands. standing and sometimes invention, fessionals and managers to become while technology is usually the result of involved with university researchers, Topical Research Conferences development. Since the SRC is not yet often for the first time. Participation in engaged in development, the task is to Topical Research Conferences deal technical committees, conferences, assist the universities in interpreting with a specific topic that is part of the and workshops are vehicles for inter- the significance of their research and SRC’s ongoing research. They create change not found in the large profes- in defining what needs to be done by an environment for active dialogue sional societies, Following are some of industry to develop technology. In the among researchers in the field. Many the highlights that characterize this case of software and analytical tech- purposes are served: early access to increasing involvement and commit- niques, a direct translation can often research results, inputs from unpub- ment of the members. be made from university research to lished industrial research efforts, and industry use. An effective way to constructive critique. During 1984, con- Technical Advisory Board and accomplish this for the member com- ferences on the following subjects were Subcommittees panies is through short courses given held: The Technical Advisory Board (TAB) by the researchers themselves, The Built-In Testability continues to be the major focus of first Transfer Course, FABRICS-II, was VLSI Interface Engineering interaction and information exchange held at Carnegie-Mellon University. Design Synthesis among industry, the SRC staff, and the Due to limitations imposed by labor- Devices and Structures universities. Participation in the Tech- atory facilities, attendance was re- Manufacturing Sciences nical Advisory Board and its three stricted. Repeat sessions will be sched- Interconnections and Contacts subcommittees doubled in 1984 with uled to meet all members’ needs. Three Rapid Thermal Annealing the opportunity for each member com- additional courses are scheduled for Attendance, limited in order to encour- pany to be represented on each sub- 1985: age interaction, averaged 45 persons committee. The addition of nine new Microstructure Characterization per meeting. Over 285 different repre- member companies during 1984 Techniques — Cornell sentatives from member companies brought new expertise and perspective. Ill-V HEMT Modeling — and faculty participated. The confer- The first SRC-TAB planning session Stanford ence on Rapid Thermal Annealing was held in August resulted in changes in Analog Design CAD — judged by leading researchers as the scope and direction of the research Georgia Tech best forum ever held on the subject. program and further quantified the A continuing stream of these events technical goals for the 1990’s. This is anticipated as the SRC research annual “summer study” provides con- Workshops programs progress. tinuity in TAB leadership. Workshops help the SRC decide whether a new research thrust is appro- Publications Industrial Mentor Program priate and where the most fruitful Publishing activities increased dra- The Industrial Mentor Program in approaches lie. Leading researchers matically in 1984. The library now con- which technical experts from member are invited from industry, government, tains 800 documents including contract companies affiliate with individual uni- and academia to present historical reports and papers, the Technical versity research tasks as resource perspectives, current research, and Report Series, proceedings of SRC people is unique to the SRC. This views of technology limits and oppor- conferences and workshops, and news- program is the result of recognition by tunities. For the Wafer-Scale Integra- letters Twenty-one company libraries the Technical Advisory Board that the tion Workshop, survey papers written have established procedures to archive university benefits from continuing by commission of the SRC reviewed and distribute SRC information. In addi- industrial perspective and resources. the history of worldwide research on tion to regular mailings, individual Layouts, mask sets and custom fabri- this subject while active industrial and requests are being received at the rate cation of wafers are examples of ser- university researchers provided a cut- of over 400 per month — most of which vices offered to universities by mem- ting edge view. The conclusions were are filled within 48 hours. bers At the request of the TAB, the used to formulate beginning projects in number of mentors was increased from the new in-situ processing thrust. Information Central 55 to 145 during the year. This was Workshops on “Post-Shrink” Silicon, Over 125 people now have direct applauded by the university community. Health and Safety, In-Situ Processing access to our VAX 11/780 Information The mentors gain from real-time inter- and Technology Assessment are sched- Central system. The primary activities action with faculty and students per- uled for 1985. are electronic mail and requests for forming research relevant to their publications. New features are being added as this computer capability is upgraded. The user base will increase as software support for a variety of terminals becomes available from the SRC. Por- tions of the SRC data base are now on tape and available to members for incorporation into internal information systems.

Researchers in Residence Opportunities are provided for researchers who are employees of member companies to hold visiting research faculty positions at universities that are participants in the SRC program. Appli- cants must be approved by the university, and the residencies are typically six months to two years.

Speakers Bureau Effective in March, 1985, the SRC Speakers Bureau will begin operation. Over forty university researchers under contract to the SRC will be available as visiting lecturers to member company locations. Eighty topics are included. This program provides company audi- ences the opportunity to review research and to discuss issues of particular relevance to their business.

Industrial Residency at the SRC The SRC provides the opportunity for member companies to place Pro- gram Managers on the SRC Technical Staff for periods of one to two years. This residency program seeks employees with management and technical expertise in specific fields of interest to the SRC to lend industry perspective to the research effort and to help with the task of monitoring research contracts To date, seven specialists from five companies have participated.

Photo by Tom Tracy; Courtesy o f Advanced Micro Devices, Inc. 1984 RESEARCH PORTFOLIO

Arizona, University of Antialiasing and Realistic Rendering Clemson University Chemical Vapor Deposition of Refractory Metals Applying Color Science to Raster Computer Electromigration in the Pulsed Mode and Their Silicides From Solid Sources Graphics Charge Injection in Gate Oxides Efficient Method for Simulating MOS Integrated Berkeley UNIGRAFIX Latent Electrostatic Discharge Effects Circuits and Its Implementation in Currently Testing for Regular Structures and Self-Testing Colorado State University Used GAD Tools Techniques Low Resistance Ohmic Contacts for VLSI Electrical Modeling and Simulation of VLSI Testability Analysis of Digital Circuits Packages Technology Testability Analysis for Analog Circuits Thermal Modeling and Simulation of VLSI Columbia University Software Reliability Packages MOS Model lmplementation in Next Generation VLSI Circuit Layout Experimental Characterization of VLSI Packages Circuit Simulation Cornell University Arizona State University Transistor Models for BIAS-B/P One-Quarter Micron CMOS Device/Circuit A Three-Dimensional VLSI Device Simulator Bagel: Berkeley Automatic Gate Array Layout Technology Auburn University Automated Parameter Extraction System for the High Density Memory Cell Considerations CSIM MOS Device Model Active Silicon Wafer-Scale Packaging Multilevel Integrated Circuits Technology Optimization-Based Design of Robust Control Monolithic Optical Interconnect Systems Low Resistance Contacts Brown University Robot Programming and Inverse Kinematics Reactive Ion Etching Hierarchical Silicon Compilation Hand-Eye Coordination Problems for Robots Transmission Lines as Interconnects for VLSI California at Berkeley, University of Computer-Based Precision A/D Converter Ballistic Transport Devices Testing Goal-Oriented Hierarchical Building-Block Laser Photochemistry for In-Situ Processing Layout System Floating Point Support for Special-Purpose “Post-Shrink” Periodic Submicron Device Simulation Hardware Routing Region Definition and Ordering Structures Gridless Channel Routing California at Los Angeles, University of Heat Removal in ICs Routing in MAGIC MBE of Silicides for VLSI Applications Physics of Submicron Scale Electron YACR-Yet Another Channel Router Confinement California at Santa Barbara, University of Topological Design of Array Logic Noise Mechanisms in Small Devices Device Physics of III-V Heterojunction Field- Theoretical Analysis of Probabilistic Hill Climbing Effect Transistors Electron Microscopy of Submicron Devices and Methods for Layout of Integrated Circuits ICs Optimization of III-V Heterostructure Graph Bisection Using Multiple Eigenvectors Configurations Defects and Morphology of Interfaces Global Wire Routing in Two-Dimensional Laterally-Structured, Multiple-Level MBE Polyimide Films for Interlevel Dielectrics Gate-Arrays Capability for Ill-V Devices Damage Induced During Plasma Etching Electrical Logic Simulation Carnegie-Mellon University Duke University (See Microelectronics Center Object Oriented Programming in BIASlisp An interactive Graphical Process Editor for of NC) BLOSIM FABRICS-II SIMPL-2 (SIMulated Profiles from Layout — Florida, University of A Methodology for Optimal Test Structure Design version 2) The Optimization of Polysilicon Emitters for Analytical Modeling of Small Geometry BSIM, an IC Process-Oriented MOSFET Model Bipolar Transistors MOSFET’s and Associated Characterization and Georgia Institute of Technology Simulation Facility Parameter Estimation for Statistical Process Characterization lnvestigations of Mechanical-Environmental Nonlinear Device Validation: Hardware and Interactions in VLSI Bond Interfaces Software Aspects PROMISE — A Fabrication Process Optimization System A Computer-Aided Design Methodology for Characterization and Modeling of Intrinsic and Analog LSI/VLSI Extrinsic Gate Capacitances of Small- Interface Specification and Synthesis Geometry MOSFETs DEMETER Project — DA Design Aid for Illinois at Urbana/Champaign, University of Scalable, Process-Independent Analog Integrated Circuit Computer Systems Investigation of Thermal and Accelerated Macrocells for Analog-Digital VLSI MOBY — A Module Binder for the CMU-DA Dopant/Surface Interactions During Vapor Expert Systems for Circuit Verification System Phase Film Growth in VLSI Device Fabrication by MBE Software Aids for Programmable Digital Signal Knowledge-based Layout Tools: TALIB Processors Towards a Natural Language Interface for CAD Design Verification and Testing of VLSI Circuits Flexible Manufacturing Cells for CAM ULYSSES — An Environment for VLSI Design Design of Testable VLSI Circuits DELIGHT.MIMO: An Interactive, Optimization- Automation Reliability Physics of Silicon VLSI Transistors Based Control System Design Package Exploitation of Low-Level Concurrency: An IMP VLSI Arrays, Applications and Layout Techniques Information System for a Microfabrication Facility Compilation of MultipIe Processor Automatic Test Generation for Microprocessors Low-Pressure Hot-Wall Silicon Epitaxy Interconnections A Fault Simulator Using Multilevel Subscripted Control of Dopant Diffusion in Silicon Dioxide Polysilicon In Advanced Integrated Circuit Ds Processes Stress-Strain Analysis of Oxidation Process for Built-In Self-Test for Microprocessors Advance Isolation Technologies On-Line Testable Processors and Testing of Design of a Pipelined Floating-Point Multiplier MOS VLSI Circuits with Recursive Fraction Unit Reducing the Technological Cost of MOS Self- Microelectronics Center of North Carolina Rensselaer Polytechnic Institute Checking Checkers [MCNC] (including work performed by Duke Proximity Correction for E-Beam Patterning Fault-Tolerant Matrix Arithmetic and Signal University [DU], North Carolina State University Electron Beam Annealing [NCSU], The University of North Carolina at Processing on Highly Concurrent Computing Ion-Cluster Beam Deposition Structures Chapel Hill [UNC/CH], and Research Triangle Institute [RTI]) Mass Spectroscopy Analysis of Ion Cluster Design Rule Checker and Circuit Extractor Beams Ultra-Compaction Techniques for VLSI Layouts An MOS Fault Simulator with Waveform [DU, MCNC] Resist Development for Ion, X-Ray, E-Beam and Information UV Lithography Shallow Junction Formation, Defects, and A Multiple Instruction Stream Shared Pipeline Structural Stresses [DU, MCNC, NCSU, Focused Ion Beam Processing Processor UNC/CH] Liquid Metal Ion Sources for FIB Hierarchical Fault Simulation Extrinsic Gettering of Impurities in Silicon Via the Switch-Level Fault Simulation Research Triangle Institute (See Introduction of Misfit Dislocations [NCSU] Microelectronics Center of NC) Timing Verification Effects of Plasma-Enhanced Etching Processes Channel Routing Algorithms and Cleaning on Surface Layer Damage and Rochester, University of General Routing of Multiterminal Nets Contamination [NCSU, UNC/CH] CAD Techniques for VLSI Layouts Network Partitioning Plasma-Assisted Low Temperature Oxidation. South Carolina, University of Film Formation and Epitaxy [MCNC, NCSU] VLSI Computing Arrays VLSI Digital Signal Processors Global Layout Techniques The Role of Particles in Yield Considerations [RTl] Southern California, University of Iowa, University of CMOS Latchup Modeling As Related to Process Laser Repair of Transparent VLSI Mask Development of a Design Automation System for Limits [DU, NCSU] Microfaults Speed-Independent Circuits Integration of Low Temperature Processing Into Stanford University One Micrometer CMOS Technology [MCNC, The Johns Hopkins University Performance Enhancement of VLSI Through the NCSU] Sources for Cluster Ion Beam Deposition Use of Advanced Cooling Techniques Minnesota, University of Massachusetts Institute of Technology Technology of Multilevel Interconnections and Three-Dimensional Integrated Circuits Contacts for Submicron VLSI Surface-Energy-Driven Secondary Grain Growth for Si Epitaxy Very Low Temperature Silicon Epitaxy by Complementary MESFET Devices for VLSI Sputtering Technology Low Temperature Silicon Epitaxy by Low Pressure Plasma Enhanced CVD Application of Acoustic Microscopy to the Studies of the Origin of Silicon-Silicon Dioxide Examination of ICs Interface States Laser Induced Chemical Vapor Deposition of High-Level Language for Representation of VLSI Active and Passive Materials Mississippi State University Fabrication Processes (FABLE) Plasma Assisted CVD of Refractory Metals and Multilevel Interconnect Materials Process and Equipment Modeling and Simulation Silicides Reactive Ion Beam Sources for VLSI Characterization and Modeling of the Plasma Generic Models for Semiconductor Fabrication Etching of Polycide Structures North Carolina at Chapel Hill, University of Equipment (See also Microelectronics Center of NC) Controlled Heat Transfer for High Quality Specialized Test Patterns Liquid-Phase Recrystallization Transfer of Software Methodology to VLSI Design A Hierearchical Parameter Distribution Control Study of Stacked Device IC Technology Performance and Failure Analysis of System: From Equipment to Process Circuit Microelectronics Devices by Digital Scanning Ultra-Thin Gate Dielectrics for Scaled CMOS Heterojunction Field-Effect Transistor Modeling Electron Microscopy Technology and Development Zero Shrinkage Ceramic Tape for IC Packages North Carolina State University (see The Texas A&M University Microelectronics Center of NC) Michigan, University of A Computer-Aided Design Methodology for Analog LSI/VLSI Sensors and Advanced Instrumentation For Notre Dame, University of Equipment Diagnostics, Process Control, Optimization of Incoherent Light and CW Laser Vermont, University of Wafer Diagnostics, and Process Evaluation Annealing in Si MOS VLSI at Low Temperatures Modeling and Control of Semiconductor Facilities The Pennsylvania State University Wisconsin, University of End-Process Testing for Detection of Thermal Nitridation of Silicon Manufacturing Defects Studies of Silicide Metallizations for VLSI Plasma and Reactive-Ion Etching With Fluorine Modeling of RIE Process for Characterization Based Compounds Yale University and Control Process-Induced Radiation Effects In Application of Machine Vision and Logical Purdue University Small-Dimension MOS Devices Inspection Units to Manufacturing Process Advanced Models for Heterostructure Devices, Thin Insulators and Their Interfaces in Control including High-Speed Bipolar Transistors Metal/Insulator/Semiconductor Systems Expert Systems for VLSI Manufacturing TECHNICAL ADVISORY BOARD TAB Co-Chairmen General Motors Corporation National Semiconductor Corporation 5 5 James M. Daughton (Honeywell) Gary L. Snyder James Harris 2,4 1,2,3 Robert M. Burger (SRC) Frank S. Stein Court Skinner 3 J. Charles Tracy The Perkin-Elmer Corporation AT&T Technologies, Incorporated Goodyear Aerospace Corporation Donald R. Herriott2 Richard M. Goldstein2,4 Melvin H. Davis1,2 Harry Sewell3 5 David J. Lando Carter M. Glass RCA Corporation 3 4 Hy J. Levinstein Robert Parker Norman Goldsmith3 Advanced Micro Devices, Incorporated Harris Corporation Robert D. Lohman2 J. Philip Downing1,2 Kurt E. Gsteiger5 William M. Webster 3 Colin W. T. Knight Thomas J. Sanders2,3 Rockwell International Corporation George Rigg James P. Spoto4 Moiz E. Beguwala5 Burroughs Corporation Hewlett-Packard Company Frank Micheletti2,5 2 Robert F. Elfant Dirk Bartelink SEMI, Chapter 2,3 Greg Gaertner Dragan Ilic John Doherty3 3 Rakesh Kumar Richard Lucic5 Larry A. Kolito2 Control Data Corporation Honeywell, Incorporated William Snow5 1,2 W. B. Edwards” James M. Daughton Semiconductor Research Corporation 1,2,5 3 W. W. Lindemann Jack S. T. Huang Robert M. Burger1,2 3 C. T. Naber Robert Payne Silicon Systems, Incorporated Digital Equipment Corporation IBM Corporation Steven Coopers 1,2,4* Kenneth H. Slater William E. Bernier Gary Kelson1,2,4 Don Sumner Billy Lee Crowder1,2,5* Greg Winner 3,4 E. I. du Pont de Nemours & Company James F. Freedman Sperry Corporation 2,5 Grant A. Beske Intel Corporation Stephen Campbell2,3 3 Denis G. Kelemen Alan Baldwin1,2,3,5 Ash Patel4 4 E-Systems, Incorporated Richmond B. Clover Texas Instruments Incorporated 1,2,4 4 Charles T. Brodnax Stephen Nachtsheim Dennis D. Buss4 Samuel A. Musa Eastman Kodak Company David A. Peterman, Sr.5 Rajinder P. Khosla2,5 G. R. Mohan Rao1,2,3* Eaton Corporation 4 Lyle Hoppie Teh-Hsuang Lee Union Carbide Corporation 2,5 3 S. V. Jaskolski David L. Losee William F. Beach GCA Corporation LSI Logic Corporation Raymond P. Roberge2,5 5 2 Robert W. Allison Conrad J. Dell’Oca Varian Associates, Incorporated 2,3 Michael W. Powell Monolithic Memories, Incorporated Larry L. Hansen1,2 5 GTE Laboratories, Incorporated George Kern Jon Thompkins 4 John H. Blank4 William E. Moss Ira Weissmans 5 2,3 Arthur H. Mones Michael Rynne Westinghouse Electric Corporation 2,3 Leslie A. Riseberg Monsanto Company William S. Corak General Electric Company Robert A. Cravan Michael Michael2,5 4 1,2,3 Gary W. Leive Harold W. Korb Xerox Corporation 2,3 Kenneth A. Pickar Motorola, Incorporated David Franco4 1,2,3 General Instrument Corporation L. David Sikes James C. Vesely2 2 Don Butler National Science Foundation 1 1,2,4 TAB Executive Committee Bernie Chern 2TAB Representative 3 3Microstructure Sciences Subcommittee Donald J. Silversmith 4Design Sciences Subcommittee 5Manufacturing Sciences Subcommittee 6Subcommittee Chairman UNIVERSITY ADVISORY COMMITTEE Professor David A. Hodges, Chairman Professor John G. Linvill Professor Joseph Stach University of California at Berkeley Stanford University Massachusetts Technology Park Corp. Professor Charles E. Backus Professor Noel MacDonald Professor Andrew J. Steckl Arizona State University Cornell University Rensselaer Polytechnic Institute Professor Stephen W. Director Professor Nino A. Masnari Professor Ben G. Streetman Carnegie-Mellon University North Carolina State University University of Texas at Austin Professor David Dumin Professor James L. Merz Professor Timothy Trick Clemson University University of California at Santa Barbara University of Illinois Professor Robert M. Hexter Professor Paul Penfield, Jr. Professor Ken D. Wise University of Minnesota Massachusetts Institute of Technology University of Michigan BOARD OF DIRECTORS George M. Scalise, Chairman Bob J. Jenkins Fred Schwettmann Advanced Micro Devices, Motorola, Incorporated Hewlett-Packard Company Incorporated Jeffrey C. Kalb Tim B. Smith Michael J. Callahan Digital Equipment Corporation Texas Instruments Incorporated Monolithic Memories, Brian A. Hegarty Larry W. Sumney Incorporated Honeywell, Incorporated Semiconductor Research Jon E. Cornell John W. Lacey Corporation Harris Corporation Control Data Corporation Richard D. Alberts Eugene J. Flath* Paul R. Low SRC (Secretary to the Board, Intel Corporation IBM Corporation January-August, 1984) Gregory Harrison Carmelo J. Santoro Ralph E. Darby, Jr. National Semiconductor Silicon Systems, Incorporated SRC (Secretary to the Board Corporation beginning September, 1984)

*Chairman June-November, 1984.

SRC STAFF Larry W. Sumney John J. Cox Richard D. LaScala President (Resident from E. I. du Pont de Nemours Contract Administrator Richard D. Alberts & Company) Wayne M. Wagoner Staff Vice President for Policy and Program Manager, Packaging Financial Administrator Planning James R. Key Cheryl Taylor (Resident from Control Data Corporation) Robert M. Burger Financial Assistant Program Manager, Technology Transfer Staff Vice President for Research Marian U. Regan Richard Lucic* Publications Coordinator Ralph K. Cavin III (Resident from Hewlett-Packard Director, Design Sciences Suzanne C. Gwynne Company) Publications Coordinator William C. Holton Program Manager, Manufacturing Kimberly A. Olive Director, Microstructure Sciences Sciences Publications Coordinator D. Howard Phillips Patrick W. Wallace Karen A. Spruill Director, Manufacturing Sciences (Resident from E. I. du Pont de Nemours Travel and Conference Coordinator Benjamin J. Agusta* & Company) Sandra D. Thomas (Resident from IBM Corporation) Program Assistant, Packaging Administrative Assistant Program Manager, Microstructure Ralph E. Darby, Jr. Shirley R. Fallin Sciences Director, Administration Secretary/Word Processor Jeffrey A. Coriale Michael D. Connelly Tonya R. Johnson (Resident from Harris Corporation) Manager, Information Systems Secretary/Word Processor Program Manager, Microstructure Brian T. N. Stokes Krista A. Saharic Sciences Information Systems Analyst Receptionist/Word Processor

*Returned to company August 1, 1984. Cover Photos: Microelectronics Center of N.C., General Electric Co., UC. at Santa Barbara.

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