Application Report SPRA847 - June 2003

OMAP5910 NTSC or VGA Output

Thanh Tran, Ph.D. DSP/EEE Catalog, OMAP Applications

ABSTRACT

The OMAP5910 is a true system-on-a-chip device, which consists of an ARM925T microprocessor unit (MPU) and TMS320C55x digital signal processor (DSP) cores. The device has many important peripherals necessary for gluelessly interfacing with external devices in multimedia communication systems. One of the ports available is a general-purpose, 16-bit parallel bus called EMIFS that is typically being used for communicating with devices such as flash, ethernet controller, and others. This application report describes an external video system design using a 2-D graphics accelerator that interfaces with the EMIFS bus and provides a super video graphics array (SVGA), video graphics array (VGA), phase alternate line (PAL) or National TV Standards Committee (NTSC) video output.

Contents 1 Introduction ...... 2 1.1 Supported Display Modes...... 2 1.1.1 Example resolution: 320x240 16bpp, 640x240 16bpp, 640x480 16bpp, 800x600 16bpp...... 2 2 Design Description ...... 2 2.1 Parallel Bus Interface (EMIFS)...... 3 2.2 2-D Graphics Accelerator on EMIFS...... 4 2.2.1 Host Interface Block...... 5 2.2.2 2-D Accelerator Block...... 6 2.2.3 TV/CRT Look-Up-Table (LUT)...... 7 2.2.4 TV Encoder...... 10 2.3 Video System Design...... 13 2.4 Software ...... 14 3 Conclusion ...... 15 4 References ...... 15

List of Figures Figure 1. OMAP5910 Video Architecture...... 3 Figure 2. S1D13506 Block Diagram...... 5 Figure 3. 4-Bit-Per-Pixel Monochrome Mode Data Output Path...... 7 Figure 4. 4-Bit-Per-Pixel Color Mode Data Output Path...... 8 Figure 5. 8-Bit-Per-Pixel Color Mode Data Output Path...... 9

Trademarks are the property of their respective owners.

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Figure 6. 15/16 Bit-Per-Pixel Format Memory Organization...... 10 Figure 7. Interlaced Scanning for Television...... 11 Figure 8. Non-Interlaced-to-Interlaced Conversion (Throw-Away Lines)...... 12 Figure 9. Non-Interlaced-to-Interlaced Conversion (Lines Averaging)...... 12 Figure 10. OMAP5910 Video System Design...... 14 Figure 11. OMAP5910 Video Demonstration on Innovator...... 15

List of Tables

Table 1. EMIFS Signal List ...... 4 Table 2. Host Interface Connection to EMIFS ...... 5 Table 3. Power-On-Reset Options...... 6 Table 4. Summary of BitBLT Operations ...... 6 Table 5. TV Encoder Filters ...... 13

1 Introduction

This application report describes an implementation of the 2-D graphics controller on the 16-bit parallel asynchronous bus of the OMAP5910 [1] [2]. The video system design consists of an external graphics accelerator and associated circuits to provide direct support for CRT up to 800x600 60Hz 64K colors, using embedded RAMDAC and direct support for NTSC/PAL TV output using embedded RAMDAC. The accelerators include a 2-D engine with bit block transfers or BitBLTs (write BLT, move BLT, solid fill, pattern fill, transparent write BLT transparent move BLT, read BLT, color expansion, and move BLT with color expansion) [3], and hardware cursor.

1.1 Supported Display Modes • 4/8/15/16 bit per pixel (bpp) color depths • Up to 64 shades of gray on monochrome passive LCD panels using frame rate modulation (FRM) and dithering • Up to 32K/64K colors in 15/16 bpp modes on color passive LCD panels using dithering • Up to 64K colors on TFT/D-TFD, CRT and TV

1.1.1 Example resolution: 320× 240 16bpp, 640× 240 16bpp, 640× 480 16bpp, 800× 600 16bpp

2 Design Description

Figure 1 shows the video architecture of the design and how the interface between an external graphics accelerator and the EMIFS port of the OMAP5910 is done. The system consists of three main parts: parallel bus interface, graphics accelerator, and TV video/VGA output.

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Power Mngmnt Osc. Osc.

OMAP5910 Suspend CLK1 CLK2 NTSC /PAL TV Display GPIOn M/R GPIOm Reset Epson Composite S1D13506F00A Video CSn CS LCD S–Video FADD[20:1] AB[20:1] Controller PDATA[15:0] DB[15:0]

nFWB WE0 VGA or SVGA WE1 CRT Display nFOB RD Red/S–Video R EMIFS RD/WR (luma) 16–bit Green/Video Parallel Osc. BCLK G Bus (comp) nFRDY WAIT Blue/S–Video B (chroma) HSYNC HSYNC VSYNC VSYNC A[11:0] MA[11:0] D[15:0] MD[15:0] 1M x 16 WE WE FPM/EDO DRAM RAS RAS LCAS LCAS UCAS UCAS

Figure 1. OMAP5910 Video Architecture

2.1 Parallel Bus Interface (EMIFS)

The EMIFS is a general-purpose, 16-bit data 24-bit address bus that is designed to interface and handle all transactions to flash memory, read-only memory (ROM), asynchronous memories, and synchronous burst flash. In addition to interfacing with different memory devices, this bus can be configured to work with other hardware accelerators such as 2D graphics controllers, full-frame-rate MPEG-2 decoders, and other 16-bit devices. The interface can drive up to four devices by assignment to one of the four chip-selects. Each chip-select has a corresponding register, to specify the protocol used for the associated external device. Table 1 outlines the signals associated with the EMIFS port. For more detailed technical information and discussion of this port, refer to the OMAP5910 Data Manual [1], which can be downloaded from the OMAP web site, www.omap.com

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Table 1. EMIFS Signal List

Signal Name I/O Description FLASH.RDY I Ready/busy signal from device

FLASH.WP O Active-low write protection

FLASH.CLK I/O Clock signal for flash device

FLASH.RP O Active-low flash power-down/reset

FLASH.CS0 O First active-low chip-select O FLASH.CS1 Second active-low chip-select

FLASH.CS2 O Third active low chip-select

FLASH.CS3 O Fourth active low chip-select

FLASH.OE O Active-low output enable

FLASH.WE O Active-low write enable

FLASH.ADV O Active-low address valid

FLASH.D[15:0] I/O 16-bit flash data bus

FLASH.A[24:1] O 24-bit flash address bus

FLASH.BE O Active-low byte enable

2.2 2-D Graphics Accelerator on EMIFS

The external 2-D accelerator being utilized is the Epson S1D13506 color liquid crystal display/cathode ray tube/television (LCD/CRT/TV) controller [3]. This device can be configured to operate in different bus interface modes for supporting reduced instruction set computing (RISC), million instructions per second (MIPS) and other processors. In this design, the bus is configured in a generic mode, to allow direct connection to the EMIFS port of the OMAP. Figure 2 shows the video accelerator device architecture. In this design, only the CRT/TV path is being used, since the design is intended to drive a stand-alone flat panel with analog RGB inputs, computer monitor with analog RGB inputs, or TV with composite or S-Video input.

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DRAM

MEM Controller

LCD LCD LCD LCD Pipeline LUT I/F Panel * * * Host I/F EMIFS (Generic Mode) CRT/TV CRT/TV 2D Pipeline LUT CRT MUX DAC /TV TV Registers Encoder

* Not utilized in this design Figure 2. S1D13506 Block Diagram

2.2.1 Host Interface Block The host interface port consists of a 16-bit data bus, 21-bit address bus, and control signals. Table 2 shows how the S1D13506 host interface is connected to the EMIFS port of the OMAP.

Table 2. Host Interface Connection to EMIFS

Host Interface (2D) EMIFS (OMAP) Description DB[15:0] FLASH.D[15:0] 16-bit bus connected to the OMAP Flash data bus

AB[0] — Connected to VDD for Generic mode AB[20:1] FLASH.D[20:1] The upper 20 bits of the host interface addr bus, connected directly to the OMAP addr bus

— FLASH.D[24:21] Not used by the host interface

CS FLASH.CS2 Chip-select connected to Flash chip-select 2

M/R GPIO1 Memory or register access connected to the GPIO1 of the OMAP

BS — Connected to VDD for generic mode RD FLASH.OE Input read command for lower data byte connected to the Flash output enable

RD/WR FLASH.OE In generic mode, this input reads the command for upper data byte and is connected to the Flash output enable

WE0 FLASH.WE Input write enable command for lower data byte

WE1 FLASH.WE Input write enable command for upper data byte

RESET GPIO2 Device reset connected to GPIO2, allowing OMAP to control the accelerator

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Table 2. Host Interface Connection to EMIFS (Continued)

Host Interface (2D)EMIFS (OMAP) Description BUSCLK — Driven by external 80-MHz oscillator, with BUSCLK divide by 2 option (40 MHz operation)

WAIT FLASH.RDY OMAP flash ready is not supported.

In this design, the S1D13506 graphics accelerator bus interface is configured in the generic mode, which requires some signals on the graphics memory interface to be pulled up appropriately. Table 3 shows a summary of the power-on-reset options selected for this design. Table 3. Power-On-Reset Options

Mode 10K Resistor Pullup Generic Pins 37 and 39 (MD1 and MD2)

Little Endian Pin 43 (MD4)

2MB DRAM Frame Buffer Pin 47 (MD6)

Bus Clock Divided by 2 Pin 40 (MD12)

2.2.2 2-D Accelerator Block The 2-D block within the graphics accelerator includes a hardware cursor for fast cursor update, a double buffering scheme for smooth animation and instantaneous screen update, and hardware BitBLTs for moving and copying rectangles of bits between the main and display memories. The integrated BitBLTs are Write BLT, Move BLT, Solid Fill, Pattern Fill, Transparent Fill, Transparent Write BLT, Transparent Move BLT, Read BLT, Color Expansion, and Move BLT with Color Expansion. The BitBLT engine design is based on a 16-bit architecture that supports rectangular and linear addressing modes for source and destination. This 2-D block also has a dedicated BitBLT IO access space, which allows for running multi-tasking applications, such as simultaneous BitBLT and CPU read/write operations. 2.2.2.1 BitBLT Operations Table 4 shows a summary of the BitBLT operations. For the definition of the BitBLT registers, see the component specifications [3] .

Table 4. Summary of BitBLT Operations

BitBLT Name Function Write BitBLT Provides two 16-bit operand ROP (raster operation) functions

Move BitBLT Provides two 16-bit operand ROP functions and supports both positive and negative directions

Read BitBLT Supports bit block transfers from the display buffer to the host, no ROP function applied

Solid Fill Fills the specified BitBLT area with a solid color, as defined in the foreground color register. In the 8-bpp mode, only the lower byte of the foreground color is used.

Pattern Fill Fills the specified BitBLT area with an 8-pixel by 8-line pattern in the full color defined in the off-screen display buffer. The pattern data has to be stored in a contiguous address.

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Table 4. Summary of BitBLT Operations (Continued)

BitBLT Name Function Transparent Pattern Fill Fills the specified BitBLT area with an 8 x 8 pattern in the full color defined in the off-screen display buffer

Transparent Write BitBLT Supports bit block transfers from the host to display buffer

Transparent Move BitBLT Supports bit block transfers from display buffer to display buffer in a positive direction only

Color Expansion BitBLT Expands the host’s monochrome data to 8- or 16-bpp color format

Move BitBLT with Color Move BitBLT with color expansion Expansion

2.2.3 TV/CRT Look-Up-Table (LUT)

The LUT architecture consists of four modes, monochrome, 4 bit-per pixel, 8 bit-per-pixel, and 15/16 bit-per-pixel. Except for the 15/16 bit-per-pixel, all other modes use the LUT to create proper colors, or a gray scale for the monochrome case that are controlled by the pixel data stored in the image buffer. For the 15/16 bit-per-pixel case, the LUT is bypassed and the color data is directly mapped to the color depths showing in Figure 6. Figure 3 through Figure 6 show the LUT architectures for all modes, and how the image buffer is being arranged for the direct mode or 15/16 bit-per-pixel mode.

In the monochrome mode, shown in Figure 3, only the green outputs are being used to send out different gray scale data to the integrated digital–to–analog converter (DAC). The 4 bit-per-pixel from the image buffer selects which gray level to display from the LUT.

Green LUT, 256x4

00 0000 01 0001 02 0010 4 Gray Scale Data

0F 1111

4 Bit per Pixel Data from Image Buffer

Figure 3. 4-Bit-Per-Pixel Monochrome Mode Data Output Path

In the 4 bit-per-pixel color mode, shown in Figure 4, the 4-bit-per-pixel data from the image buffer selects which colors to display from the three LUTs (red, green, and blue). The LUT only consists of 16 levels for each color, and the outputs to the integrated DAC are always 4 bits per displayed color.

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Red LUT, 256x4 00 0000 01 0001 02 0010 4 Red 03 0011 Data

0F 1111

Green LUT, 256x4 00 0000 01 0001 02 0010 4 Bits per Pixel 4 Green Data from 03 0011 Data Image Buffer

0F 1111

Blue LUT, 256x4 00 0000 01 0001 02 0010 4 Blue 03 0011 Data

0F 1111

Figure 4. 4-Bit-Per-Pixel Color Mode Data Output Path

In the 8-bit-per-pixel color mode, shown in Figure 5, the 8-bit-per-pixel data from the image buffer selects which colors to display from the three LUTs. Each of the LUT consists of 256 colors, and the outputs to the integrated DAC are always 4 bits per displayed color.

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Red LUT, 256x4 00 0000 0000 01 0000 0001 02 0000 0010 Red 03 0000 0011 Data

FF 1111 1111

Green LUT, 256x4 00 0000 0000 01 0000 0001 02 0000 0010 8 Bits per Pixel Green Data from 03 0000 0011 Data Image Buffer

FF 1111 1111

Blue LUT, 256x4 00 0000 0000 01 0000 0001 02 0000 0010 Blue 03 0000 0011 Data

FF 1111 1111

Figure 5. 8-Bit-Per-Pixel Color Mode Data Output Path

In the 15/16 bit-per-pixel color modes, shown in Figure 6, the LUT is bypassed, and the colors are directly mapped to the selected color depths. In this case, the display memory are arranged, as shown in Figure 6, for the little-endian system, where the host addresses the display buffer directly to display the 15- or 16-bit color depth on the selected pixel. For example, in the 15-bit color mode, the pixel P0 is displaying the RGB data addressed by byte 0 and byte 1 from the host.

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MSB555 RGB LSB

Byte 0 G02 G01 G00 B04 B03 B02 B01 B00 P0 P1

Byte 1 R04 R03 R02 R01 R00 G04 G03

Byte 2 G12 G11 G10 B14 B13 B12 B11 B10 Pn=(Rn4–0, Gn4–0, Bn4–0) Display Byte 3 R14 R13 R12 R11 R10 G14 G13 Panel

Host Display Buffer Address

MSB 565 RGB LSB

Byte 0 G02 G01 G00 B04 B03 B02 B01 B00 P0 P1

Byte 1 R04 R03 R02 R01 R00 G05 G04 G03

Byte 2 G12 G11 G10 B14 B13 B12 B11 B10 Pn=(Rn4–0, Gn5–0, Bn4–0) Display Byte 3 R14 R13 R12 R11 R10 G15 G14 G13 Panel

Host Display Buffer Address Figure 6. 15/16 Bit-Per-Pixel Format Memory Organization

2.2.4 TV Encoder

As shown in the Figure 2 block diagram, the video output can be configured as CRT or TV mode. For CRT, the DAC data input comes from the LUT or the image buffer directly, as described in section 2.2.3. For the TV mode, the DAC data input comes from the TV encoder, which can be configured to output either NTSC (14.31818 MHz input to CLKI2 or pin 71) or PAL (17.734475 MHz to CLKI2 or pin 71) video format. In this design, only NTSC mode is included. The video data output from the 2-D graphics block is compatible with a noninterlaced display, such as computer monitor. To display the data on an interlaced TV display, it is necessary to do the non-interlaced-to-interlaced conversion.

2.2.4.1 Noninterlaced to Interlaced Conversion Overview Figure 7 shows an example of how interlaced scanning works for the television monitor. Each TV frame consists of two fields, and each field comprises half the scanning lines. The second field is delayed half the frame time from the first field. For NTSC, there are 780 pixels in one horizontal line, 525 horizontal lines total, and 59.94-Hz vertical refresh rate.

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336 23 337 24 338 25 339 26 27 Two fields of 312.5 Second field retrace lines each (25 lines) (2x287.5 visible)

Second field retrace (25 lines) 620 621 308 622 309 623 310 Schematic representation of interlaced scanning (625 lines)

Write

Black Level

Synchronization Horizontal Level Synchronization Visible Part Horizontal Suppression Total Line Duration Figure 7. Interlaced Scanning for Television

There are two common techniques [4] to convert the non-interlaced to interfaced format, throwing away every other line in each non-interlaced frame, and using three scan lines of non-interlaced frame to generate one interlaced scan line. The first technique is simple but the video artifacts, such as flicker, are not acceptable; therefore, the second method is preferred. The disadvantage of the second method, where the conversion requires three non-interlaced scan lines to generate one interlaced scan line, is that this technique requires line stores to store the video data for processing as well as digital filters. This method greatly reduces the flicker and makes this the preferred implementation. Figure 8 demonstrates the first method, where each interlaced field is generated by throwing away every other line of the noninterlaced frame. Figure 9 demonstrates the second conversion method, where each interlaced field is generated by taking an average of three lines.

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525 Noninterlaced 525 Interlaced 525 Noninterlaced 525 Interlaced Frame #1 Odd Field Frame #2 Even Field 1 1 1

2 2 263

3 2 3

4 4 264

5 3 5

6 6 265

7 4 7

8 8 266

525 Noninterlaced 525 Interlaced 525 Noninterlaced 525 Interlaced Scan Line Number Scan Line Number Scan Line Number Scan Line Number Figure 8. Non-Interlaced-to-Interlaced Conversion (Throw-Away Lines)

525 Noninterlaced 525 Interlaced 525 Noninterlaced 525 Interlaced Frame #1 Odd Field Frame #2 Even Field 1 1 1

2 2 263

3 2 3

4 4 264

5 3 5

6 6 265

7 4 7

8 8 266

525 Noninterlaced 525 Interlaced 525 Noninterlaced 525 Interlaced Scan Line Number Scan Line Number Scan Line Number Scan Line Number Figure 9. Non-Interlaced-to-Interlaced Conversion (Lines Averaging)

2.2.4.2 NTSC TV Encoder Filters The S1D13506 TV encoder design is based on averaging three non-interlaced lines to create one interlaced line. Using this technique requires proper digital filters to reduce image distortions such as cross-luminance, cross-chrominance, and flicker. The distortions are typically generated by sharp chrominance and luminance transitions, which are necessary for high-resolution computer graphics. To optimize the quality on the TV output, it is preferable to turn on the filters listed in Table 5.

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Table 5. TV Encoder Filters

Filter Register Definition Chrominance Filter REG[05Bh], bit 5 = “1” enable Reduces cross-luminance distortion by limiting the bandwidth of the chrominance signal. This filter has the most effect on the composite video output.

Luminance Filter REG[05Bh], bit 4 = “1” enable Reduces cross-chrominance distortion by limiting the bandwidth of the luminance signal. This filter has the most effect on the composite video output.

Anti-Flicker Filter REG[1FCh], bits [2:0] = ”110” flicker Reduces flicker on TV display caused by filter enable displaying only half the refresh rate of the original non-interlaced images.

2.3 Video System Design Figure 10 shows a complete video system design that includes external components to interface with the OMAP5910. External filter circuitries and low-noise board layout techniques are required and are very important for designers to achieve an acceptable video performance. Here are some of the recommended techniques for low noise video system design: • Separate the power supply voltage for the video DAC from the system power supply voltage. The best way is to use a high power supply rejection ratio (PSRR) linear voltage regulator such as TI TPS76701QPWPR. • Place the 100-nF capacitors as close to the power pins of the video device as possible, and distribute the number of the capacitors evenly around the part. Place one 10- mF bulk capacitor at each side of the device as close to the 100 nF as possible. • As shown in Figure 10, all data bus, address bus, and clock signals should have 22-W series termination resistors. These termination resistors should be placed as close to the pins as possible. • Use 100-W ferrite beads at 100 MHz for the video output Pi filters. The Pi structure provides two-pole roll-off where the first corner frequency is 1 , where R is the device output 2pRC resistance, and C is the external filter capacitance at the output pin (C100, 102, 104, 106, or 1 108). The second corner frequency is also 2pRC, where R is the ferrite bead impedance, and C is the capacitance connected from the VGA connector to ground (C101, 103, 105, 107 or 109). • Keep all the high-speed signal traces as short as possible. The video outputs (red, green, blue, hsync, and vsync) should have the same widths and lengths.

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3V3

U100 R116 TP3

5V0I 1 GND/HSINK GND/HSINK 20 VDAC 2 19 1 GND/HSINK GND/HSINK TP2 R117 0R0 100K RST_VIDEO# 3 18 4 GND NC 17 NC NC 1 3 L107 5 16 6 EN# RESET# 15 R118 50 R120 1.5K 2 Q1 IN FB/ Ferite 7 IN OUT 14 1% 1% 2N2222A 8 13 J101 NC OUT TP1 1 9 12 R121 10 GND/HSINK GND/HSINK 11 1K 4 3 GND/HSINK GND/HSINK 1 C128 C130 + C131 1% R122 S_VIDEO 100nF C129 + 10UF 100nF 69.8 2 1 R119 10UF 16V 1% TPS76701QPWPR 30K 16V 1% L105

Ferite J100 L109 Ferite 1 COMPOSITE VIDEO 2

L100

Ferite

1 L106 5V0I R100 C100 C101 D100 3V3I FADD_1FADD_2FADD_3 C132 C133 C134 150, 1% 20pF 20pF BAV99/SOT Ferite FADD_4FADD_5FADD_6FADD_7FADD_8FADD_9FADD_10FADD_11FADD_12FADD_13FADD_14FADD_15FADD_16FADD_17FADD_18FADD_19FADD_20 100nF 100nF 100nF 5 6 7 8 RN14 RN15 RN16 3 2 J102 RN12 R104 3V3 + 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 C127 22 22 15 15 +C125 C126 10UF RN13 1 C124 10UF 100nF 16V 22 L101 1 14 4 3 2 1 100nF 16V 2 14 2 Ferite 13 13 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 3 1 3 C102 C103 12 12 22 22 22 R101 20pF 20pF D101 4 150, 1% BAV99/SOT 4 11 5 11 5 3 2 10 1281271261251241231221211201191181171161151141131121111101091081071061051041031021011009998 97 10 6 6 3V3 1 96 9 J103 AB2 VSS 9 2 FWE# VSS1 1 2 AB1 AB3AB4AB5AB6AB7AB8AB9 FPDAT16 95 L102 7 7 FADD_1 4 3 FD_0 3 VSSVDD RED VDD 94 8 A1 D0 AB0 AB10AB11AB12AB13AB14AB15AB16AB17AB18AB19AB20 VRTCHRTCBLUE IREF FPDAT15 8 FADD_2 6 5 FD_1 R115 22 4 GREEN 93 FADD_3 8 A2 D1 7 FD_2 22 5 CS# DACVSSDACVDDDACVDDDACVDDDACVSSFPDAT14 92 Ferite FADD_4 10 A3 D2 9 FD_3 R114 6 M/R# FPDAT12 91 RGB_15–P A4 D3 BS# FPDAT11 1 FADD_5 12 A5 +3.3V 11 R113 0 7 RD# FPDAT10 90 C104 C105 FADD_6 14 13 FD_4 R112 22 8 89 R102 20pF 20pF D102 FADD_7 A6 D4 FD_5 WE0# FPDAT9 16 A7 D5 15 R111 0 9 WE1# FPDAT8 88 150, 1% BAV99/SOT FADD_8 18 17 FD_6 R110 22 10 U101 87 FADD_9 20 A8 D6 19 FD_7 11 RD/WR# VSS 86 FADD_10 22 A9 D7 21 12 RESET# FPDAT7 85 3 2 24 A10 VSS2 23 FD_8 13 VDD FPDAT6 84 +3.3V D8 BUSCLK FPDAT5 FADD_11 26 A11 D9 25 FD_9 14 VSS FPDAT4 83 FADD_12 28 27 FD_10 15 82 FADD_13 A12 D10 FD_11 FD_15 WAIT# FPDAT3 30 A13 D11 29 4 5 16 DB15 FPDAT2 81 L103 FADD_14 32 31 FD_14 3 6 17 80 FADD_15 34 A14 +5V 33 FD_12 FD_13 2 7 18 DB14 FPDAT1 79 FADD_16 36 A15 D12 35 FD_13 FD_12 1 8 19 DB13 S1D13506 FPDAT0 78 Ferite FADD_17 38 A16 D13 37 FD_14 FD_11 22 4 5 RN11 20 DB12 VSS 77 A17 D14 DB11 FPSHIFT 1 FADD_18 40 A18 D15 39 FD_15 FD_10 3 6 21 DB10 DRDY 76 C106 C107 FADD_19 42 41 FD_9 2 7 22 75 20pF 20pF D103 FADD_20 A19 VSS3 FD_8 DB9 LCPWR 44 A20 FCLK 43 1 8 23 DB8 FPLINE 74 3V3 BAV99/SOT 46 45 R108 22 FD_7 22 4 5 RN10 24 73 FADD_21 48 FOE# FRDY# 47 FD_6 3 6 25 DB7 FPFRAME 72 FADD_22 50 A21 NC 49 FD_5 2 7 26 DB6 VDD 71 3 2 A22 NC DB5 CLKI2 52 VSS4 VSS5 51 FD_4 1 8 27 DB4 TESTEN 70 FADD_23 54 53 FD_3 22 4 5 RN9 28 69 FADD_24 56 A23 NC 55 5V0 FD_2 3 6 29 DB3 CLKI1 68 58 A24 NC 57 FD_1 2 7 30 DB2 VSS 67 60 NFCS +5V 59 FD_0 1 8 31 DB1 MA3 66 L104 GPIO1 GPIO2 DB0 MA4 22 RN8 32 VSS MA2 65 OMAP5910 EMIFS VDDMD15MD0MD14MD1MD13MD2MD12MD3MD11MD4MD10MD5MD9MD6MD8MD7VSSLCAS#UCAS#WE#RAS#VDDMA9/GPIO3MA11/GPIO2MA8MA10/GPIO1MA7MA0MA6MA1MA5 Ferite 1 3334 35363738 394041 424344 45464748 49505152 535455 565758 59606162 6364 C108 C109 20pF 20pF D104 R107 BAV99/SOT 10K R123 22 3V3 3 2 R125 R124 10K R105 10K 22 3V3

3V3 1 2 3 4 1 2 3 4 U103 C110 R124 RN2 RN1 4 VCC OE 1 100nF C110 10K 22 22 R106 100nF 22 3 2 8 7 6 5 8 7 6 5 OUT GND 1 2 3 4 14.31818MHz for NTSC U104 RN3 17.734475MHz for PAL 1 2 3 4 4 VCC OE 1 22 RN40 1 2 3 4 1 2 3 4 R141 47K RN5 RN4 8 7 6 5 R109 NI 3 2 10K 22 22 OUT GND 33.333MHz 3V3 8 7 6 5 8 7 6 5 8 7 6 5 PRELIMINARY OMAP5910 NTSC/PAL VIDEO OUTPUT R140 22 R123 OR VGA OUTPUT – Revised on 1/13/03 1 2 3 4 10K RN6 22

3V3 8 7 6 5 50 49484746 454443 424140 36 35343332 313029 282726 3V3 C210 NC NC A9A8 A7A6A5A4 100nF 1 2 3 4 VSS VSS DQ9DQ8 OE# VSS DQ15DQ14DQ13DQ12DQ11DQ10 CASL# CASH# RN7 22 U105 C111 + C112 + C113 + C114 + C115 + 4 1 8 7 6 5 U102 10UF 10UF 10UF 10UF 10UF VCC OE MT4LC1M16E5 VCCDQ0DQ1DQ2DQ3VCCDQ4DQ5DQ6DQ7NC NCNCWE#RAS#NCNCA0A1A2A3 VCC 16V 16V 16V 16V 16V 1 2 3 4 5 6 7 8 9 R200 22 3 2 1011 15 16171819 202122 232425 OUT GND 80MHz 3V3I L108

Ferite C116 C117 C118 C119 C120 C121 C122 C123 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF

C135 C136 C137 Title 100nF 100nF 100nF OMAP5910 NTSC/PAL Video Design Size Document Number Rev A2 Preliminary OMAP Video Design TTT Date:Thursday, May 01, 2003 Sheet 11of Figure 10. OMAP5910 Video System Design

2.4 Software

Refer [6] for programming notes and examples for initializing the S1D13506 Color LCD/CRT/TV Controller. The reference source codes are available on the Epson web site, www.eea.epson.com. Currently, there are device drivers available for many popular embedded operating systems and detailed information can be found on the same web site. Figure 11 demonstrates the OMAP5910 on the Innovator Development platform [5] interfacing with the S1D13506 graphics controller, to drive an external VGA monitor.

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Figure 11. OMAP5910 Video Demonstration on Innovator

3 Conclusion This application report provides an example for OMAP5910 system designers to add a VGA or NTSC video output feature to their product definition. It is intended to provide important information to successfully design the video hardware and to interface with the EMIFS bus of the OMAP5910. While the document only discusses the NTSC video, it is possible to make simple a modification (changing the video clock frequency) to provide a PAL video output as well.See [3] for more detailed information. One limitation to this design is that only one output can be enabled at a time. For example, designers can only configure the video controller to operate in one of the two modes, VGA up to 800 × 600 resolution or NTSC video, not both simultaneously.

4 References 1. OMAP5910 Dual-Core Processor Data Manual (SPRS197). 2. OMAP5910 Dual-Core Processor Technical Reference Manual (SPRU602). 3. Epson Research and Development. S1D13506 Color LCD/CRT/TV Controller Technical Manual. www.eea.epson.com 4. Jack, Keith. Video Demystified. San Diego: Hightext, 1996. 5. Productivity Systems, Inc. Innovator Development Kit for the Texas Instruments OMAP Platform, www.prodsys.com 6. Epson Research and Development. S1D13506 Programming Notes and Examples. www.eea.epson.com 7. Poynton, Charles A. A Technical Introduction to Digital Video. Toronto: Wiley, 1996.

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