5 4 3 2 1

D EFM32 Development Kit D

Board Function Page Revision History Analog Interfaces 2 Rev. Description

Sensors, SPI bus and I2C bus 3 PA18 Removed STM32 testADC connection Added OE signal to BC_SPI buffer User Interface 4 Clamped DIR signal on BC_SPI buffer Display Interface 5 A00 Changed ST1 and ST2 to NM Flash and SRAM 6 Initial Release

Board Control - Control MCU 7 C A01 Fixed EFM32_A80 connection C Board Control - Buses 8 Set D11 to Not Mounted A02 Board Control - Misc 9 Changed capacitors on trace lines to 8.2 pF Board Control - JTAG 10

Control MCU 11

Control MCU - BC Interface 12

Debug Interface 13

Trace Interface 14 B B Board Control Level shift #1 15

Board Control Level shift #2 16

EXP32 Assignments #1 17

EXP32 Assignments #2 18

EFM32 Board Connectors 19

EXP32 Board Connectors 20 TOP Main Power Regulators 21 Schematic Title A A EFM Power Regulators and AEM 22 EFM32 Development Kit - Mainboard PCB1 Page Title

Designed: Approved: Title Page JNO PCB3201 JNO Document number Revision Size BOM Doc No: A3 BRD3201A A02 Design Created Date: Sheet Created Date Sheet Modified Date Sheet Wednesday, December 03, 2008 Saturday, March 21, 2009 Thursday, September 08, 2011 1of 22 5 4 3 2 1 Line In Amplifier5 & Filter 4 3 Line Out Driver & Filter2 1

R15 15K R17 15K TP104 C9 150P C10 220P TPJ161 TP105 R262 C16 R19 TP106 J2 1K 10U 15K R20 27K U2A U3B 3 LINE_IN_RIGHT 2 5 - C14 R22 10R R23 7K5 R24 7K5 4 R30 C12 1 8 10 TP107 1 AUDIO_IN_RIGHT OUT_AUDIO_OUT_RIGHT D 2 1K 680P INR OUTR R25 10R J1 D 1 C13 C15 3 1U VLINE_IN 3 + 10N 1N 5 SJ1-3515 R16 47K AGND AGND TLV2473IDGQ MAX9724A R26 10R 4 AGND 2 AGND GND 1 R21 C11 R27 15K 47K 100N R28 15K TP108 SJ1-3515 TPJ162 TP110 C18 220P C19 C20 C21 150P TP111 TP109 10N 10N R263 C17 AGND U3A 1K 10U R36 27K U2B LINE_IN_LEFT 8 C22 AO_SGND AO_SGND AO_SGND - R32 7K5 R33 7K5 R35 R38 10R 6 11 OUT_AUDIO_OUT_LEFT R29 15K C25 9 INL OUTL 2 AUDIO_IN_LEFT 1K 680P C23 1U C26 1N 7 + 10N AGND MAX9724A AGND TLV2473IDGQ GND AGND

I2S DAC C C AUDIO_OUT_LEFT AUDIO_OUT_RIGHT U85A 16 3 NC1 3V3 U86A 9 NC2 6 12 NC3 2 OUT_AUDIO_OUT_LEFT SYSCLK/PLL1 14 NC4 COM1 5 OUT_AUDIO_OUT_RIGHT 1 VOUTL COM2 7 I2S_SCLK 2 BCK 1 COM3 10 I2S_WS R421 R420 3 WS 4 NO1 COM4 I2S_DATA DATAI NO2 0R 0R 8 NM 16 11 NO3 15 NM AUDIO_OUT_SELECT 7 VOUTR NO4 IN 11 SFOR1 TS3A5018 SFOR0 GND R422 R423 8 MUTE 0R 0R 9 10 DEEM/CLKOUT 12 PLL0 VREF R425 UDA1334 C326 C327 R424 R426 GND 0R 0R 0R R419 100N 10U 0R

GND B GND GND B

3V3

L33 R427 TP153 1R 3V6 1 2 BLM21B102S U86B U85B 1 2 4 13 14 VDD_D VDD_A V+ GND AO_SGND GND AGND AO_SGND L34 C332 BLM21B102S R428 C328 C329 C330 C331 1R 10N 13 6 10U 100N 100N 10U EN GND Power Supply and Decoupling 5 15 TS3A5018 VSS_D VSS_A UDA1334 C27 1U AUDIO_OUT_CONNECT GND GND GND 3V3 R39 U3C TOP 47K 1 3 TP23 VLINE_IN TP24 C1P C1N R41 L2 Schematic Title U2C 10R 5 10 1 2 5V 5 9 A AUDIO_IN_CONNECT GND A 1SHDN VDD BLM21B102S TP98 SHDN SVSS 7 EFM32 Development Kit - Mainboard 6 SGND 2SHDN C35 C36 C37 1 2 12 4 Page Title R43 4 VDD PVSS 2 C28 GND PGND 47K 11 100P 10N 10U L1 R40 C29 C30 C31 1U Designed: Approved: Interface - Analog GND_HEAT BLM21B102S 0R JNO TLV2473IDGQ 10U 10N 100P MAX9724A JNO Document number Revision Size BOM Doc No: A3 BRD3201A A02 Design Created Date: Sheet Created Date Sheet Modified Date Sheet AGND AGND GND GND AO_SGND Wednesday, December 03, 2008 Saturday, March 21, 2009 Tuesday, September 06, 2011 2of 22 5 4 3 2 1 5 4 3 2 1 3V3 3V3 I2C Bus 3V3 microSD Card Slot 3V3 P9 Temp U36A ADM3315E 3V3 7 18 A_TX 5 R159 R160 IF_RS232_TX Sensor 8 T_IN1 T_OUT1 17 9 4K7 4K7 TP88 R163 TPJ187 TPJ190 TPJ188 TPJ189 CTRLMCU_RS232_TX 9 T_IN2 T_OUT2 16 4 R161 100K T_IN3 T_OUT3 EEPROM GND 8 10 0R U42A STDS75 R272 3 1 3 22R R273 R274 R275 I2C_BUS_SDA SDA O.S. 7 11 I2C_BUS_SCL 2 SPI_BUS_#CS 47K 47K 47K 2 SCL IF_RS232_RX 10 15 A_RX 6 R162 U41A 7 P16 11 R_OUT1 R_IN1 14 1 0R 5 A0 6 R255 1 CTRLMCU_RS232_RX R_OUT2 R_IN2 SDA A1 DAT2 12 13 GND 6 5 22R 2 D R_OUT3 R_IN3 SCL A2 CD / DAT3 D SPI_BUS_MOSI 3 19 TYCO_5747844_6 1 4 CMD IF_RS232_SHUTDOWN SD 2 A0 5 VDD A1 SPI_BUS_SCLK CLK 5 3 7 GND 6 EN A2 WP R257 7 VSS 22R 8 DAT0 24AA024 DAT1 GND R168 C249 4K7 SPI_BUS_MISO 100N microSD R254 22R GND TPJ191 TPJ192 TPJ193 TPJ194

RS232 Physical Layer GND

Ethernet SPI MAC+PHY and Connector TPJ195 TPJ196 TPJ197 TPJ198 3V3 TP186 3V3_ETH H1102NL

R462 1 16 P20 4K7 1 U82A 2 15 2 TX+ 28 11 3 TX- ETH_SCLK SCLK RX+ RX+ ETH_MISO 27 12 3 14 4 31 MISO RX- 14 5 CAP ETH_MOSI C 26 MOSI TX+ 15 6 NC C ETH_#CS CS TX- R404 6 11 7 RX- 1K 8 TX CT 2 1 7 10 RX CT

PME LED0 SH SH ETH_#INT 3 32 19 INTRN LED1 3V3 R406 R407 R408 R409 8 9 RJHSE-5380 RST 9 R405 49R9 49R9 49R9 49R9 10 2K U102 3V3 R415 17 2 2 R410 R411 R412 R413 0R NM ISET LED125 LED126 C307 C308 C309 75R 75R 75R 75R R414 GREEN YELLOW 1 C311 3.01K 100N 100N 10U D10 R416 1N4148 10K C310 10 1 1 1N GND GND GND GND 1N 20 EECS 7 2kV 2 X1/CLK EESK 21 6 GND 2kV SGND ETH_#RST X2 EED_IO X1 KSZ8851SNL C312 2 1 SGND 3V3 3V3 10U C313 25MHz C314

12P 12P U84 NM GND R418 1 8 4K7 2 CS VCC 7 C315 SCK NC GND GND 3 6 4 DI ORG 5 100N DO GND B AT93C46 B GND

C153 C152 C151

U36B ADM3315E 100N 100N 100N 6 20 Power & Decoupling 2 C1+ C1- 4 24 C2+ C2- 22 C3+ C3- 3V3

1V8_ETH 3V3 21 3 V- VCC L30 C156 C157 C158 3V3 100N C159 1 2 3V3_ETH 100N 100N 10U BLM21B102S U82B L31 23 1 16 25 GND V+ VDD_A3V3 VDD_IO 30 1 2 GND GND C316 C317 C318 VDD_IO BLM21B102S 2 GND 1U 100N 10N TPJ199 TOP L32 1V8_ETH C323 C324 C325 Schematic Title BLM21B102S 5 100N 100N 10U 1 VDD_CO1V8 A GND 9 23 A VDD_A1V8 VDD_D1V8 3V3 3V3 EFM32 Development Kit - Mainboard U41B U42B 8 4 C319 C322 8 8 C320 C321 13 AGND DGND 22 100N 1U VCC VDD Page Title 100N 10N 18 AGND DGND 24 AGND DGND 29 4 C168 4 C169 Designed: Approved: Interface - Digital 33 DGND VSS 10N GND 10N GND JNO 24AA024 STDS75 JNO Document number Revision Size BOM Doc No: KSZ8851SNL A3 BRD3201A A02 GND GND Design Created Date: Sheet Created Date Sheet Modified Date Sheet GND GND Wednesday, December 03, 2008 Saturday, March 21, 2009 Tuesday, September 06, 2011 3of 22 5 4 3 2 1 5 4 3 2 1 SE -> Diff Input C1 100P Single-Ended Input/Output User switches

TP99 P1 R1 390R TP101 TP102 2 R3 P2 AMP_112538_BNC TP100 3V3

3 390R U1A R4 2 1 8 + 49R9 3 R2 4 5 1 ANALOG_DIFF_N ANALOG_SE_A 5 4 VDIFFAMP 2 C3 5 0R 390P 2 C2 R175 R176 R177 R178

GND 2 4 22P 10K 10K 10K 10K - ANALOG_DIFF_P 1 D R6 ST2 NM UIF_DIP[3..0] D AMP_112538_BNC ST1 10K R8 NM SW2 NM R10 AD8132ARM 49R9 AGND UIF_DIP0 1 ON 8 1 390R R13 C6 C7 1 UIF_DIP1 2 7 1 390R 22P 22P R5 AGND UIF_DIP2 3 6 C408 49R9 UIF_DIP3 4 5 R7 R12 100N 49R9 10K R11 SW_DIP4_SMD 24R9 GND C8 AGND 100P AGND AGND

AGND AGND AGND

User pushbuttons 3V3 VDIFFAMP TP25 3V3 SW3 R187 U1B R42 10R 100R 3 1 2 1 3 V+ R183 R184 R185 R186 C32 C33 C34 L3 BLM21B102S UIF_PB[3..0] 100K 100K 100K 100K 2 4 6 7 100P 100N 10U GND V- NC UIF_PB0 AD8132ARM UIF_PB1 UIF_PB2 SW4 UIF_PB3 R188 1 3 100R AGND C170 C171 C172 C173 2 4 C 10N 10N 10N 10N C GND SW5 R189 GND GND GND GND 100R 1 3

2 4 GND

SW6 R190 100R 1 3 3V3 2 4 GND

R219 SW10 R220 100K 100R UIF_AEM 1 3 C246 2 4 GND 10N

GND

B User LEDs Joystick B 3V3 UIF_LEDS[4..0] UIF_LEDS0 R327 2 2 2 2 220R LED103 LED104 LED105 LED106 UIF_JOYSTICK[4..0] YELLOW YELLOW YELLOW YELLOW R191 R192 R193 R194 R195 100K 100K 100K 100K 100K 4 3 2 1 SW7 1 UIF_JOYSTICK3 6 1 1 1 1 UIF_JOYSTICK4 UIF_LEDS1 R328 UIF_JOYSTICK0 2 2 2 2 UIF_JOYSTICK1 2 5 220R LED107 LED108 LED109 LED110 UIF_JOYSTICK2 YELLOW YELLOW YELLOW YELLOW C174 C175 C176 C177 C178 4 8 7 6 5 10N 10N 10N 10N 10N R196 3 1 1 1 1 100R UIF_LEDS2 R329 2 2 2 2 1 220R Inputs LED LED114 LED113 LED112 LED111 2 GND YELLOW YELLOW YELLOW YELLOW zzz01 3 GND zz0z1 4 5 z0zz1 6 TOP 12 11 10 9 0zzz1 zzz10 7 1 1 1 1 zz01z 8 Schematic Title UIF_LEDS3 R330 z0z1z 9 2 2 2 2 0zz1z 10 A 220R zz1z0 11 A LED115 LED116 LED117 LED118 zz10z 12 EFM32 Development Kit - Mainboard YELLOW YELLOW YELLOW YELLOW z01zz 13 0z1zz 14 15 Page Title 16 15 14 13 z1zz0 z1z0z 1 1 1 1 z10zz Designed: Approved: Interface - Analog & UI 01zzz UIF_LEDS4 JNO JNO Document number Revision 16 Size BOM Doc No: A3 BRD3201A A02 Design Created Date: Sheet Created Date Sheet Modified Date Sheet Wednesday, December 03, 2008 Wednesday, March 16, 2011 Thursday, October 13, 2011 4of 22 5 4 3 2 1 5 4 3 2 1 TFT-LCD Flat Panel Connector (FPC) 3V3

3V3 R457 3V3 3V3 47K NM R458 TP60 TP61 TP62 TP63 P18 0R 1 DISPLAY_TOUCH_Y2 R115 R114 Y2 2 47K 47K X2 3 C403 Y1 4 1N X1 DISPLAY_#RESET P15 4pin_1mm_pitch_FPC DISPLAY_DC 1 D DISPLAY_#RD D 2 VCI R459 DISPLAY_#WR GND 3 VCI 0R DISPLAY_#CS 4 VSS DISPLAY_SCL VDDIO DISPLAY_TOUCH_X2 DISPLAY_SDO 5 6 VSS C404 DISPLAY_SDI 7 RESB 1N 8 DC / SDC TP130 9 E / RD 10 R/W / WR CS / SCS 11 R460 GND 12 SCL 0R DISPLAY_WSYNC SDO 13 DISPLAY_TOUCH_Y1 14 SDI DISPLAY_DATA[17..1] DISPLAY_DATA17 15 WSYNC C405 DISPLAY_DATA16 16 D17 1N DISPLAY_DATA15 17 D16 DISPLAY_DATA14 18 D15 DISPLAY_DATA13 19 D14 D13 TP203 TP204 TP205 TP206 DISPLAY_DATA12 20 R461 GND DISPLAY_DATA11 21 D12 0R D11 DISPLAY_DATA10 22 DISPLAY_TOUCH_X1 DISPLAY_DATA9 23 D10 DISPLAY_DATA8 24 D9 C406 DISPLAY_DOTCLK DISPLAY_DATA7 25 D8 1N DISPLAY_HSYNC DISPLAY_DATA6 26 D7 DISPLAY_VSYNC DISPLAY_DATA5 27 D6 DISPLAY_OE DISPLAY_DATA4 28 D5 D4 DISPLAY_DATA3 29 GND R497 R441 DISPLAY_DATA2 30 D3 C 100K 100K DISPLAY_DATA1 31 D2 C 32 D1 33 D0 34 VSS DOTCLK 3V3 GND GND 35 36 HSYNC DISP1 37 VSYNC U103A 38 OE 39 VSS 2 6 40 PS0 41 PS1 42 PS2 R442 43 PS3 1 100K 44 VSS TFT_LEDA 45 NC 46 NC TFT_LEDK 47 NC NC U103B GND 48 ENTRY_MODE PS[3..0] Description 49 VSS 5 3 50 K DISPLAY_ENTRY_MODE A 0 0010 16 bit 8080 mode USMH_8252MD_320X240_RGB R489

7 1 0101 16 bit generic mode + SPI 100K GND URT USMH-8252MD 320x240 TFT-LCD MODULE TOUCH GND

GND B B FPGA debug connector TFT_LEDK R277 DISPLAY_DATA[17..1] 1K DISPLAY_KSENSE TFT_LEDA P17 R276 C251 DISPLAY_DATA1 1 2 DISPLAY_DATA2 100K R279 DISPLAY_DATA3 3 4 DISPLAY_DATA4 100N DISPLAY_DATA5 5 6 DISPLAY_DATA6 DISPLAY_ASENSE 100K DISPLAY_DATA7 7 8 DISPLAY_DATA8 C250 DISPLAY_DATA9 9 10 DISPLAY_DATA10 R278 DISPLAY_DATA11 11 12 DISPLAY_DATA12 TFT-LCD power regulator 10K 100N GND DISPLAY_DATA13 13 14 DISPLAY_DATA14 R363 C292 DISPLAY_DATA15 15 16 DISPLAY_DATA16 100R 100N DISPLAY_DATA17 17 18 DISPLAY_DC DISPLAY_DC 5V NM NM DISPLAY_#RESET 19 20 TP120 DISPLAY_#RESET GND L11 HEADER_2X10_1.27MM_SMD L5 10UH D1 TFT_LEDA NM 1 2 2 1 GND

BLM41P600S C132 1 C133 C134 TFT-LCD decoupling TOP U31 NCP5006 10U D6 1U 100N Schematic Title 5 1 A VBAT VOUT DFLZ24 A GND TP159 GND GND 3V3 3V3 2 EFM32 Development Kit - Mainboard U103C TFT_LEDK 8 4 3 R362 VCC Page Title DISPLAY_PWR_ENABLE EN FB C131 C144 C129 C392

GND 0R 4 Designed: Approved: Display Interface R132 C293 R131 10U 100N 100N 100N GND 2 JNO JNO 10K 100N 15R 74LVC2G125DC Document number Revision NM Size BOM Doc No: A3 BRD3201A A02 GND Place close to P15 Design Created Date: Sheet Created Date Sheet Modified Date Sheet GND GND GND GND GND Wednesday, December 03, 2008 Saturday, March 21, 2009 Monday, September 24, 2012 5of 22 5 4 3 2 1 5 4 3 2 1

BC_AD[15..0] BC_ADDR[22..0]

U52A U25A BC_ADDR0 A3 B6 BC_AD0 BC_ADDR0 E2 E3 BC_AD0 BC_ADDR1 A4 A0 IO0 C5 BC_AD1 BC_ADDR1 D2 A0 DQ0 H3 BC_AD1 BC_ADDR2 A5 A1 IO1 C6 BC_AD2 BC_ADDR2 C2 A1 DQ1 E4 BC_AD2 BC_ADDR3 B3 A2 IO2 D5 BC_AD3 BC_ADDR3 A2 A2 DQ2 H4 BC_AD3 BC_ADDR4 B4 A3 IO3 E5 BC_AD4 BC_ADDR4 B2 A3 DQ3 H5 BC_AD4 D BC_ADDR5 C3 A4 IO4 F5 BC_AD5 BC_ADDR5 D3 A4 DQ4 E5 BC_AD5 D 3V3 BC_ADDR6 C4 A5 IO5 F6 BC_AD6 BC_ADDR6 C3 A5 DQ5 H6 BC_AD6 BC_ADDR7 D4 A6 IO6 G6 BC_AD7 BC_ADDR7 A3 A6 DQ6 E6 BC_AD7 BC_ADDR8 H2 A7 IO7 B1 BC_AD8 BC_ADDR8 B6 A7 DQ7 F3 BC_AD8 BC_ADDR9 H3 A8 IO8 C1 BC_AD9 BC_ADDR9 A6 A8 DQ8 G3 BC_AD9 R211 BC_ADDR10 H4 A9 IO9 C2 BC_AD10 BC_ADDR10 C6 A9 DQ9 F4 BC_AD10 47K BC_ADDR11 H5 A10 IO10 D2 BC_AD11 BC_ADDR11 D6 A10 DQ10 G4 BC_AD11 BC_ADDR12 G3 A11 IO11 E2 BC_AD12 BC_ADDR12 B7 A11 DQ11 F5 BC_AD12 BC_ADDR13 G4 A12 IO12 F2 BC_AD13 BC_ADDR13 A7 A12 DQ12 G6 BC_AD13 BC_ADDR14 F3 A13 IO13 F1 BC_AD14 BC_ADDR14 C7 A13 DQ13 F6 BC_AD14 BC_ADDR15 F4 A14 IO14 G1 BC_AD15 BC_ADDR15 D7 A14 DQ14 G7 BC_AD15 BC_ADDR16 E4 A15 IO15 BC_ADDR16 E7 A15 DQ15__A-1 BC_ADDR17 D3 A16 BC_ADDR17 B3 A16 BC_ADDR18 H1 A17 BC_ADDR18 C4 A17 BC_ADDR19 G2 A18 BC_ADDR19 D5 A18 BC_ADDR20 H6 A19 BC_ADDR20 D4 A19 TP28 TP29 BC_ADDR21 E3 A20 BC_ADDR21 C5 A20 A21 BC_ADDR22 B8 A21 BC_#BL[1..0] C8 A22 BC_#BL0 A1 3V3 F8 A23 BC_#BL1 B2 LB G8 A24 UB A25 B5 R117 BC_#CS2 CS A6 47K GND NC A4 A2 RY/BY BC_#RE G5 OE F2 BC_#WE WE CE BC_#RE G2 MT45W2MW16PGA-70 IT OE C BC_#WE A5 C TP33 TP26 TP27 WE

B4 TP30 WP/ACC F7 BYTE B5 RESET BC_#CS3 TP74 S29GLxxx_FBGA

R118 FPGA_FLASH_#RESET 47K NM Write Protect

GND

B 1.8V PSRAM regulator B

R493 NM

3V3 TP216 RAM_VCORE 0R U110 2 1 IN OUT1 4 R494 OUT2 R495 C413 C414 10K 5 1.79V 43K 7 SET C412 10U 100N SHDN 8 R496 4U7 FAULT 3 100K 9 GND 6 GND_HEAT CC GND GND LP3982ILD-ADJ C415 GND GND GND 33N

GND

3V3 TOP RAM_VCORE 3V3 U25B G5 A1 Schematic Title U52B VCC RFU1 B1 A D6 E1 D8 RFU2 C1 A VCC VCC_Q C118 F1 VIO RFU3 D1 EFM32 Development Kit - Mainboard 100N VIO RFU4 E1 C116 C117 C119 RFU5 G1 100N 100N 100N H2 RFU6 H1 Page Title E8 VSS RFU7 H8 H7 VSS RFU9 A8 Designed: Approved: NOR Flash / SRAM E6 D1 VSS RFU10 VSS VSS_Q JNO S29GLxxx_FBGA JNO Document number Revision MT45W2MW16PGA-70 IT GND Size BOM Doc No: A3 BRD3201A A02 GND GND Design Created Date: Sheet Created Date Sheet Modified Date Sheet Wednesday, December 03, 2008 Saturday, March 21, 2009 Thursday, October 13, 2011 6of 22 5 4 3 2 1 5 4 3 2 1 IF_RS232_UART_CONNECT 3V3 IF_RS232_SHUTDOWN

R199 FPGA_FLASH_#RESET 4K7 FPGA_#INT

FPGA_VCCO2 CTRLMCU_DATA[15..0] U6C FPGA_CFG_M0 T15 CTRLMCU_ADDR[23..16] CTRLMCU_ADDR20 FPGA_CFG_CCLK R15 IO_L1N_M0_CMPMISO_2 P9 V16 IO_L1P_CCLK_2 VCCO_2 R12 D U16 IO_L2N_CMPMOSI_2 VCCO_2 R6 D CTRLMCU_ADDR19 FPGA_CFG_#CS T13 IO_L2P_CMPCLK_2 VCCO_2 U14 CTRLMCU_DATA2 FPGA_CFG_D0 R13 IO_L3N_MOSI_CSI_B_MISO0_2 VCCO_2 U4 IO_L3P_D0_DIN_MISO_MISO1_2 VCCO_2 CTRLMCU_FPGA_#INT V14 U9 CTRLMCU_DATA3 FPGA_CFG_D1 T14 IO_L12N_D2_MISO3_2 VCCO_2 CTRLMCU_DATA15 FPGA_CFG_D10 P12 IO_L12P_D1_MISO2_2 FPGA_CFG_M1 N12 IO_L13N_D10_2 CTRLMCU_ADDR17 FPGA_CFG_D12 V13 IO_L13P_M1_2 CTRLMCU_ADDR16 FPGA_CFG_D11 U13 IO_L14N_D12_2 IO_L14P_D11_2 SPI_BUS_CONNECT T11 R11 IO_L16N_VREF_2 ANALOG_SE_CONNECT IO_L16P_2 ANALOG_DIFF_CONNECT V11 U11 IO_L23N_2 AUDIO_OUT_CONNECT IO_L23P_2 AUDIO_IN_CONNECT T10 R10 IO_L29N_GCLK2_2 FPGA_CLK V10 IO_L29P_GCLK3_2 CTRLMCU_ADDR18 FPGA_CFG_D13 U10 IO_L30N_GCLK0_USERCCLK_2 CTRLMCU_DATA1 FPGA_CFG_D15 T8 IO_L30P_GCLK1_D13_2 CTRLMCU_DATA0 FPGA_CFG_D14 R8 IO_L31N_GCLK30_D15_2 CTRLMCU_DATA4 V9 IO_L31P_GCLK31_D14_2 CTRLMCU_DATA5 T9 IO_L32N_GCLK28_2 CTRLMCU_DATA6 V8 IO_L32P_GCLK29_2 CTRLMCU_DATA7 U8 IO_L41N_VREF_2 CTRLMCU_DATA8 V7 IO_L41P_2 CTRLMCU_DATA9 U7 IO_L43N_2 V15 CTRLMCU_DATA10 V6 IO_L43P_2 NC V12 CTRLMCU_DATA11 T6 IO_L45N_2 NC U15 T7 IO_L45P_2 NC T12 CTRLMCU_ADDR22 R7 IO_L46N_2 NC P11 C CTRLMCU_ADDR21 FPGA_CFG_RD#WR T5 IO_L46P_2 NC P8 C FPGA_CFG_D7 R5 IO_L48N_RDWR_B_VREF_2 NC P7 CTRLMCU_FSMC_#E1 FPGA_CFG_D4 V5 IO_L48P_D7_2 NC N11 CTRLMCU_FSMC_#OE FPGA_CFG_D3 U5 IO_L49N_D4_2 NC N10 CTRLMCU_FSMC_CLK IO_L49P_D3_2 NC CTRLMCU_FSMC_#WAIT FPGA_CFG_D6 T3 N9 FPGA_CFG_D5 R3 IO_L62N_D6_2 NC N8 CTRLMCU_FSMC_#WE V4 IO_L62P_D5_2 NC N7 CTRLMCU_FSMC_#ADV CTRLMCU_DATA12 T4 IO_L63N_2 NC N6 CTRLMCU_DATA14 FPGA_CFG_D9 P6 IO_L63P_2 NC M11 CTRLMCU_DATA13 FPGA_CFG_D8 N5 IO_L64N_D9_2 NC M10 V3 IO_L64P_D8_2 NC M8 CTRLMCU_ADDR23 FPGA_CFG_#INIT U3 IO_L65N_CSO_B_2 NC IO_L65P_INIT_B_2 P13 IF_I2C_BUS_CONNECT CMPCS_B_2 FPGA_CFG_DONE V17 V2 DONE_2 FPGA_CFG_#PROG PROGRAM_B_2 xc6slx9csg324 FPGA_VCCAUX 2 LED80 YELLOW 1

B R68 B 2K

FPGA_CFG_#PROG FPGA_CFG_DONE 2 LED81 GREEN 1

R71 1K

GND FPGA Init LED FPGA Configuration Mode FPGA_VCCO2 TOP Schematic Title 2 A LED79 A YELLOW FPGA_CFG_M0 EFM32 Development Kit - Mainboard FPGA_CFG_M1 Page Title 1 R53 R54 Designed: Approved: Board Control - Control MCU Interface R55 1K 1K JNO JNO 2K NM Document number Revision Size BOM Doc No: FPGA_CFG_#INIT A3 BRD3201A A02 GND GND Design Created Date: Sheet Created Date Sheet Modified Date Sheet Wednesday, December 03, 2008 Saturday, March 21, 2009 Thursday, October 13, 2011 7of 22 5 4 3 2 1 5 4 3 2 1

FPGA_VCCO3

U6D DISPLAY_DATA[17..1] DISPLAY_DATA17 N3 E2 RTCK!!! DISPLAY_DATA16 N4 IO_L1N_VREF_3 VCCO_3 G4 DISPLAY_DATA15 P3 IO_L1P_3 VCCO_3 J2 DISPLAY_DATA14 P4 IO_L2N_3 VCCO_3 J5 FPGA_VCCO0 DISPLAY_DATA13 M5 IO_L2P_3 VCCO_3 M4 IO_L31N_VREF_3 VCCO_3 SDRAM_BA[1..0] DISPLAY_DATA12 L6 R2 U6A DISPLAY_DATA11 U1 IO_L31P_3 VCCO_3 D SDRAM_BA0 C4 DISPLAY_DATA10 U2 IO_L32N_M3DQ15_3 D SDRAM_BA1 D4 IO_L1N_VREF_0 B10 DISPLAY_DATA9 T1 IO_L32P_M3DQ14_3 IO_L1P_HSWAPEN_0 VCCO_0 IO_L33N_M3DQ13_3 SDRAM_DQML A2 B15 DISPLAY_DATA8 T2 B2 IO_L2N_0 VCCO_0 B5 DISPLAY_DATA7 P1 IO_L33P_M3DQ12_3 SDRAM_DQMH IO_L2P_0 VCCO_0 IO_L34N_M3UDQSN_3 SDRAM_WE# C6 D13 DISPLAY_DATA6 P2 D6 IO_L3N_0 VCCO_0 D7 DISPLAY_DATA5 N1 IO_L34P_M3UDQS_3 SDRAM_CAS# IO_L3P_0 VCCO_0 IO_L35N_M3DQ11_3 SDRAM_RAS# A3 E10 DISPLAY_DATA4 N2 B3 IO_L4N_0 VCCO_0 DISPLAY_DATA3 M1 IO_L35P_M3DQ10_3 SDRAM_CS# IO_L4P_0 IO_L36N_M3DQ9_3 SDRAM_CLK A4 DISPLAY_DATA2 M3 B4 IO_L5N_0 DISPLAY_DATA1 L1 IO_L36P_M3DQ8_3 SDRAM_CLKE IO_L5P_0 IO_L37N_M3DQ1_3 CPLD_MOSI A5 DISPLAY_#RD L2 C5 IO_L6N_0 K1 IO_L37P_M3DQ0_3 CPLD_MISO IO_L6P_0 DISPLAY_#WR IO_L38N_M3DQ3_3 CPLD_SCK A6 DISPLAY_DC K2 B6 IO_L8N_VREF_0 L3 IO_L38P_M3DQ2_3 CPLD_CS# IO_L8P_0 DISPLAY_#CS IO_L39N_M3LDQSN_3 UIF_LEDS4 A7 DISPLAY_SCL L4 UIF_LEDS3 C7 IO_L10N_0 J1 IO_L39P_M3LDQS_3 IO_L10P_0 DISPLAY_SDO IO_L40N_M3DQ7_3 UIF_LEDS2 C8 DISPLAY_SDI J3 UIF_LEDS1 D8 IO_L11N_0 H1 IO_L40P_M3DQ6_3 IO_L11P_0 DISPLAY_WSYNC IO_L41N_GCLK26_M3DQ5_3 UIF_LEDS0 A8 DISPLAY_#RESET H2 B8 IO_L33N_0 SDRAM_DQ0 K3 IO_L41P_GCLK27_M3DQ4_3 UIF_LEDS[4..0] BC_SPI_CTRL_BUF_#OE C9 IO_L33P_0 SDRAM_DQ1 K4 IO_L42N_GCLK24_M3LDM_3 TOUCH_CONNECT IO_L34N_GCLK18_0 IO_L42P_GCLK25_TRDY2_M3UDM_3 BC_BUS_EXT_ADDR_MODE D9 SDRAM_DQ2 K5 A9 IO_L34P_GCLK19_0 SDRAM_DQ3 L5 IO_L43N_GCLK22_IRDY2_M3CASN_3 TRACE_CONNECT IO_L35N_GCLK16_0 IO_L43P_GCLK23_M3RASN_3 I2S_ETH_CONNECT B9 SDRAM_DQ4 H3 C11 IO_L35P_GCLK17_0 SDRAM_DQ5 H4 IO_L44N_GCLK20_M3A6_3 UIF_AEM IO_L36N_GCLK14_0 IO_L44P_GCLK21_M3A5_3 DISPLAY_ENTRY_MODE D11 SDRAM_DQ6 K6 A10 IO_L36P_GCLK15_0 SDRAM_DQ7 L7 IO_L45N_M3ODT_3 TRACE_CLK_OUT IO_L37N_GCLK12_0 IO_L45P_M3A3_3 DISPLAY_PWR_ENABLE C10 G11 SDRAM_DQ8 G1 F9 IO_L37P_GCLK13_0 NC G8 SDRAM_DQ9 G3 IO_L46N_M3CLKN_3 DEBUG_#TRST_IN IO_L38N_VREF_0 NC IO_L46P_M3CLK_3 DEBUG_#TRST_OUT G9 F12 SDRAM_DQ10 J6 C A11 IO_L38P_0 NC F11 SDRAM_DQ11 J7 IO_L47N_M3A1_3 C DEBUG_TDI_IN IO_L39N_0 NC IO_L47P_M3A0_3 DEBUG_TDI_OUT B11 F10 SDRAM_DQ12 F1 A12 IO_L39P_0 NC F8 SDRAM_DQ13 F2 IO_L48N_M3BA1_3 DEBUG_TMS_SWDIO_IN B12 IO_L41N_0 NC F7 SDRAM_DQ14 H5 IO_L48P_M3BA0_3 DEBUG_TMS_SWDIO_#OE IO_L41P_0 NC IO_L49N_M3A2_3 DEBUG_TMS_SWDIO_OUT A14 E12 SDRAM_DQ15 H6 B14 IO_L62N_VREF_0 NC E11 SDRAM_A0 E1 IO_L49P_M3A7_3 DEBUG_TCK_SWCLK_IN IO_L62P_0 NC SDRAM_DQ[15..0] IO_L50N_M3BA2_3 DEBUG_TCK_SWCLK_OUT E13 E8 SDRAM_A1 E3 F13 IO_L63N_SCP6_0 NC E6 SDRAM_A2 F3 IO_L50P_M3WE_3 DEBUG_#RESET_IN IO_L63P_SCP7_0 NC IO_L51N_M3A4_3 DEBUG_#RESET A15 D12 SDRAM_A3 F4 C15 IO_L64N_SCP4_0 NC C13 SDRAM_A4 D1 IO_L51P_M3A10_3 DEBUG_TDO_SWO_IN TRACE_DATA0 C14 IO_L64P_SCP5_0 NC C12 SDRAM_A5 D2 IO_L52N_M3A9_3 TRACE_DATA1 D14 IO_L65N_SCP2_0 NC A13 SDRAM_A6 G6 IO_L52P_M3A8_3 TRACE_DATA2 A16 IO_L65P_SCP3_0 NC E7 SDRAM_A7 H7 IO_L53N_M3A12_3 TRACE_DATA3 B16 IO_L66N_SCP0_0 NC SDRAM_A8 D3 IO_L53P_M3CKE_3 IO_L66P_SCP1_0 SDRAM_A9 E4 IO_L54N_M3A11_3 xc6slx9csg324 SDRAM_A10 F5 IO_L54P_M3RESET_3 TRACE_DATA[3..0] SDRAM_A11 F6 IO_L55N_M3A14_3 SDRAM_A12 C1 IO_L55P_M3A13_3 SDRAM_A13 C2 IO_L83N_VREF_3 IO_L83P_3 xc6slx9csg324 SDRAM_A[13..0] TP207 TP208 TP209 TP210 TP211 TP212 TP213 TP214

U104A U104B CPLD_MISO 40 39 41 F1M1 38 F2M1 CPLD_MOSI 43 F1M2 36 F2M2 CPLD_SCK B 42 F1M3_GCK1 3V3 37 F2M3_GTS1 B CPLD_CS# 44 F1M4 34 F2M4 2 F1M5_GCK2 33 F2M5_GTS2 1 F1M6 32 F2M6_GSR CPLD_CLK 3 F1M7_GCK3 31 F2M7 UIF_DIP3 5 F1M8 30 F2M8 UIF_PB[3..0] UIF_DIP2 6 F1M9 R59 R58 UIF_PB0 29 F2M9 UIF_DIP1 7 F1M10 100K 100K UIF_PB1 28 F2M10 UIF_DIP0 8 F1M11 NM NM UIF_PB2 27 F2M11 UIF_JOYSTICK0 12 F1M12 UIF_PB3 23 F2M12 UIF_DIP[3..0] UIF_JOYSTICK1 13 F1M13 BOARD_REVISION1 22 F2M13 UIF_JOYSTICK2 14 F1M14 BOARD_REVISION0 21 F2M14 UIF_JOYSTICK3 16 F1M15 PCB_REVISION1 20 F2M15 UIF_JOYSTICK4 18 F1M16 PCB_REVISION0 19 F2M16 F1M17 F2M17 UIF_JOYSTICK[4..0] R64 R63 XC9536XL 100K 100K XC9536XL

GND GND GND GND

3V3 U104C 11 15 TOP CPLD_TCK 9 TCK VCC_INT 35 CPLD_TDI TDI VCC_INT Schematic Title CPLD_TDO 24 10 TDO 26 A CPLD_TMS TMS VCC_IO A C393 C394 C395 C396 EFM32 Development Kit - Mainboard 100N 100N 100N 10U Page Title 4 GND 17 Designed: Approved: Board Control - FPGA1 GND 25 GND JNO JNO Document number Revision XC9536XL Size BOM Doc No: A3 BRD3201A A02 GND Design Created Date: Sheet Created Date Sheet Modified Date Sheet Wednesday, December 03, 2008 Saturday, March 21, 2009 Thursday, October 13, 2011 8of 22 5 4 3 2 1 5 TP34 TP35 TP36 TP37 TP38 TP39 TP40 TP41 4 3 2 1

U6B FPGA_VCCO1 BC_AD[15..0] BC_AD0 F16 BC_AD1 F15 IO_L1N_A24_VREF_1 E17 BC_AD2 C18 IO_L1P_A25_1 VCCO_1 G15 BC_AD3 C17 IO_L29N_A22_M1A14_1 VCCO_1 J14 BC_AD4 G14 IO_L29P_A23_M1A13_1 VCCO_1 J17 BC_AD5 F14 IO_L30N_A20_M1A11_1 VCCO_1 M15 BC_AD6 D18 IO_L30P_A21_M1RESET_1 VCCO_1 R17 BC_AD7 D17 IO_L31N_A18_M1A12_1 VCCO_1 SDRAM_DQ[15..0] BC_AD8 G13 IO_L31P_A19_M1CKE_1 BC_AD9 H12 IO_L32N_A16_M1A9_1 SDRAM_A[13..0] BC_AD10 E18 IO_L32P_A17_M1A8_1 D BC_AD11 E16 IO_L33N_A14_M1A4_1 D BC_AD12 K13 IO_L33P_A15_M1A10_1 U88A BC_AD13 K12 IO_L34N_A12_M1BA2_1 SDRAM_A0 H7 A8 SDRAM_DQ0 BC_AD14 F18 IO_L34P_A13_M1WE_1 SDRAM_A1 H8 A0 DQ0 B9 SDRAM_DQ1 BC_AD15 F17 IO_L35N_A10_M1A2_1 SDRAM_A2 J8 A1 DQ1 B8 SDRAM_DQ2 BC_#CS[3..0] BC_#CS0 H14 IO_L35P_A11_M1A7_1 SDRAM_A3 J7 A2 DQ2 C9 SDRAM_DQ3 BC_#CS1 H13 IO_L36N_A8_M1BA1_1 SDRAM_A4 J3 A3 DQ3 C8 SDRAM_DQ4 BC_#CS2 H16 IO_L36P_A9_M1BA0_1 SDRAM_A5 J2 A4 DQ4 D9 SDRAM_DQ5 BC_#CS3 H15 IO_L37N_A6_M1A1_1 SDRAM_A6 H3 A5 DQ5 D8 SDRAM_DQ6 G18 IO_L37P_A7_M1A0_1 SDRAM_A7 H2 A6 DQ6 E9 SDRAM_DQ7 BC_ALE G16 IO_L38N_A4_M1CLKN_1 SDRAM_A8 H1 A7 DQ7 E1 SDRAM_DQ8 BC_#WE K14 IO_L38P_A5_M1CLK_1 SDRAM_A9 G3 A8 DQ8 D2 SDRAM_DQ9 BC_#RE IO_L39N_M1ODT_1 A9 DQ9 BC_ARDY J13 SDRAM_A10 H9 D1 SDRAM_DQ10 L13 IO_L39P_M1A3_1 SDRAM_A11 G2 A10 DQ10 C2 SDRAM_DQ11 BC_SPI_SCLK L12 IO_L40N_GCLK10_M1A6_1 SDRAM_A12 G1 A11 DQ11 C1 SDRAM_DQ12 BC_SPI_#CS K16 IO_L40P_GCLK11_M1A5_1 SDRAM_A13 E2 NC1 DQ12 B2 SDRAM_DQ13 BC_SPI_MOSI IO_L41N_GCLK8_M1CASN_1 SDRAM_BA[1..0] NC2 SDRAM DQ13 BC_SPI_MISO K15 B1 SDRAM_DQ14 L16 IO_L41P_GCLK9_IRDY1_M1RASN_1 SDRAM_BA0 G7 DQ14 A2 SDRAM_DQ15 BC_BUS_CONNECT_EBI L15 IO_L42N_GCLK6_TRDY1_M1LDM_1 SDRAM_BA1 G8 BA0 DQ15 BC_ADDR_BUF_#OE[1..0] BC_BUS_CONNECT_SPI BC_ADDR_BUF_#OE0 H18 IO_L42P_GCLK7_M1UDM_1 BA1 BC_ADDR_BUF_#OE1 H17 IO_L43N_GCLK4_M1DQ5_1 E8 SDRAM_DQML J18 IO_L43P_GCLK5_M1DQ4_1 F1 DQML I2S_ETH_SPI_CLK SDRAM_DQMH J16 IO_L44N_A2_M1DQ7_1 DQMH I2S_ETH_SPI_MOSI K18 IO_L44P_A3_M1DQ6_1 F9 I2S_ETH_SPI_MISO SDRAM_WE# K17 IO_L45N_A0_M1LDQSN_1 F7 WE I2S_ETH_SPI_#CS SDRAM_CAS# L18 IO_L45P_A1_M1LDQS_1 F8 CAS BC_AD_BUF_#OE IO_L46N_FOE_B_M1DQ3_1 SDRAM_RAS# RAS BC_AD_BUF_DIR L17 F3 M18 IO_L46P_FCS_B_M1DQ2_1 G9 CLKE F2 BC_BUS_CTRL_BUF_#OE IO_L47N_LDC_M1DQ1_1 SDRAM_CS# CS CLK RP42 BC_SPI_CTRL_BUF_DIR M16 1 8 N18 IO_L47P_FWE_B_M1DQ0_1 C PWR_MON_ADC_#CS IO_L48N_M1DQ9_1 IS42S16800 C PWR_MON_ADC_CLK 2 7 N17 3 6 P18 IO_L48P_HDC_M1DQ8_1 PWR_MON_ADC_MOSI SDRAM_CLK 4 5 P17 IO_L49N_M1DQ11_1 PWR_MON_ADC_MISO SDRAM_CLKE RP23 N16 IO_L49P_M1DQ10_1 1 8 22R N15 IO_L50N_M1UDQSN_1 ETH_SCLK IO_L50P_M1UDQS_1 ETH_MOSI 2 7 T18 3 6 T17 IO_L51N_M1DQ13_1 ETH_MISO IO_L51P_M1DQ12_1 ETH_#CS 4 5 U18 U17 IO_L52N_M1DQ15_1 22R N14 IO_L52P_M1DQ14_1 ETH_#INT IO_L53N_VREF_1 ETH_#RST M14 M13 IO_L53P_1 ETHERNET_CONNECT IO_L61N_1 I2S_SCLK 8 1 L14 7 2 P16 IO_L61P_1 I2S_WS IO_L74N_DOUT_BUSY_1 I2S_DATA 6 3 P15 5 4 IO_L74P_AWAKE_1 xc6slx9csg324 22R RP25 IF_RS232_LEUART_CONNECT AUDIO_OUT_SELECT

B B

3V3 3V3 U88B J9 A7 E7 VDD VDDQ B3 A9 VDD VDDQ C7 VDD VDDQ D3 VDDQ C364 C365 C366 C367 A3 C360 C361 C362 C363 A1 VSSQ B7 100N 100N 100N 100N 10U 100N 100N 100N J1 VSS VSSQ C3 E3 VSS VSSQ D7 VSS VSSQ

IS42S16800 GND GND

TOP Schematic Title A A EFM32 Development Kit - Mainboard Page Title

Designed: Approved: Board Control - FPGA2 JNO JNO Document number Revision Size BOM Doc No: A3 BRD3201A A02 Design Created Date: Sheet Created Date Sheet Modified Date Sheet Wednesday, December 03, 2008 Saturday, March 21, 2009 Thursday, October 13, 2011 9of 22 5 4 3 2 1 5 4 R336 3 2 1 0R RP14 CTRLMCU_JTAG_#TRST 1 8 CTRLMCU_JTAG_TMS 2 7 CTRLMCU_JTAG_TCK 3 6 CTRLMCU_JTAG_TDO 4 5 CTRLMCU_JTAG_TDI U56A U57B 22R 74LVC2G125DC 2 6 R294 22R 74LVC2G125DC 3 5

1 CPLD_TCK U6E D RP13 NM CPLD_TMS D U56B 1 8 FH_TDO_BUF D16 V18 7 CPLD_TDO CPLD_TDI 2 7 FH_TDI_BUF D15 TDO GND V1 5 3 3 6 FH_TMS_BUF B18 TDI GND U12 4 5 FH_TCK_BUF A17 TMS GND U6 74LVC2G125DC TCK GND T16 22R GND R18 7 R16 GND R14 3V3 SUSPEND GND R9 P5 U57A FPGA_VCCAUX GND R4 2 1 P14 GND R1 4 3 FH_TRST 2 6 P10 VCCAUX GND N13 6 5 FH_TDI P5 VCCAUX GND M17 8 7 FH_TMS 74LVC2G125DC M9 VCCAUX GND M6 10 9 FH_TCK R383 K7 VCCAUX GND M2 12 11 1 10K J12 VCCAUX GND L11 14 13 FH_TDO G10 VCCAUX GND L9 VCCAUX GND 16 15 CTRLMCU_DEBUG_#RESET E14 K10 18 17 E9 VCCAUX GND K8 VCCAUX GND 20 19 R295 GND E5 J15 1M B17 VCCAUX GND J11 2X10 2.54MM B1 VCCAUX GND J9 NM VCCAUX GND J4 FPGA_VCCINT GND H10 GND GND M12 H8 VCCINT GND GND GND M7 G17 L10 VCCINT GND G12 L8 VCCINT GND G5 K11 VCCINT GND G2 K9 VCCINT GND E15 C J10 VCCINT GND D10 C J8 VCCINT GND D5 H11 VCCINT GND C16 H9 VCCINT GND C3 G7 VCCINT GND B13 VCCINT GND B7 GND A18 GND A1 GND xc6slx9csg324

Control MCU and FPGA clock GND R490 0R

NM 3V3 TP155 U108A U7A 3 2 4 R56 CTRLMCU_CLK R57 OUTPUT 100K 22R 74LVC1G125 1 1 R200 OE FPGA_CLK 22R ASFLM1 GND

B TP154 R447 B CPLD_CLK 22R

3V3 FPGA_VCCAUX FPGA_VCCO0 FPGA_VCCO1 FPGA_VCCO2 FPGA_VCCO3

R73

0R

C333 C334 C335 C336 C337 C338 C339 C340 C341 C342 C343 C344 C345 C346 C347 C348 C349 C350 C351 C352 C353 C354 470N 470N 470N 4U7 22U 470N 470N 4U7 22U 470N 470N 4U7 22U 470N 470N 4U7 22U 470N 470N 4U7 47U 100U

GND

3V3 TOP

3V3 Schematic Title FPGA_1V2 FPGA_VCCINT A R300 3V3 A 33R EFM32 Development Kit - Mainboard U56C U57C U7B R72 8 8 4 0R C262 VCC VCC VCC U108B Page Title C409 6 100N 4 4 C40 100N VCC C355 C356 C357 C358 C359 Designed: Approved: Board Control - JTAG / Debug GND GND 2 100N 470N 4U7 4U7 4U7 47U GND JNO 74LVC2G125DC 74LVC2G125DC 3 5 JNO Document number Revision ASFLM1 GND NC Size BOM Doc No: A02 74LVC1G125 A3 BRD3201A GND GND GND Design Created Date: Sheet Created Date Sheet Modified Date Sheet GND GND Wednesday, December 03, 2008 Saturday, March 21, 2009 Thursday, October 13, 2011 10of 22 5 4 3 2 1 5 4 3 2 1

PROD_TEST_UART_EFM_RX PROD_TEST_UART_EFM_TX

RP34 1 8 DISPLAY_TOUCH_Y2 2 7 DISPLAY_TOUCH_Y1 3 6 DISPLAY_TOUCH_X2 4 5 DISPLAY_TOUCH_X1 D 0R D RP36 U17A ETH_#CS 1 8 ETH_SCLK 2 7 3 6 G2 ETH_MISO PA0 / WKUP / USART2_CTS / ADC123_IN0 / TIM2_CH1_ETR / TIM5_CH1 / TIM8_ETR ETH_MOSI 4 5 H2 J2 PA1 / USART2_RTS / ADC123_IN1 / TIM5_CH2 / TIM2_CH2 33R K2 PA2 / USART2_TX / ADC123_IN2 / TIM5_CH3 / TIM2_CH3 G3 PA3 / USART2_RX / ADC123_IN3 / TIM5_CH4 / TIM2_CH4 PORT A H3 PA4 / SPI1_NSS / DAC_OUT1 / USART2_CK / ADC12_IN4 J3 PA5 / SPI1_SCK / DAC_OUT2 / ADC12_IN5 K3 PA6 / SPI1_MISO / TIM8_BKIN / ADC12_IN6 / TIM3_CH1 [TIM1_BKIN] R79 1K5 CTRLMCU_DEBUG_LED D9 PA7 / SPI1_MOSI / TIM8_CH1N / ADC12_IN7 / TIM3_CH2 [TIM1_CH1N] C9 PA8 / USART1_CK / TIM1_CH1 / MCO R80 22R D10 PA9 / USART1_TX / TIM1_CH2 DEBUG_TDO_SWO_IN C10 PA10 / USART1_RX / TIM1_CH3 USBDM B10 PA11 / USART1_CTS / CANRX / TIM1_CH4 / USBDM USBDP A10 PA12 / USART1_RTS / CANTX / TIM1_ETR / USBDP R81 22R A9 PA13 / JTMS-SWDIO C88 C89 A8 PA14 / JTCK-SWCLK PA15 / JTDI 18P 18P J4 DEBUG_EXT_VDD_TARGET K4 PB0 / ADC12_IN8 / TIM3_CH3 / TIM8_CH2N DEBUG_EXT_CABLE_ATTACH G5 PB1 / ADC12_IN9 / TIM3_CH4 / TIM8_CH3N PORT B AEM_VMCU_ENABLE PB2 / BOOT1 GND GND A7 A6 PB3 / JTDO / TRACESWO / SPI3_SCK / I2S3_CK [TIM2_C H2 / SPI1_SCK] PB4 / JNTRST / SPI3_MISO [TIM3_CH2 / SPI1_MISO] DEBUG_BUF_#OE C5 B5 PB5 / I2C1_SMBAI / SPI3_MOSI / I2S3_SD [TIM3_CH2 / SPI1_MOSI] TRACE_MCU_SW_ENABLE PB6 / I2C1_SCL / TIM4_CH1 [USART1_TX] CTRLMCU_FSMC_#ADV A5 C B4 PB7 / I2C1_SDA / FSMC_NADV / TIM4_CH2 [USART1_RX] C TRACE_EXT_CABLE_ATTACH R296 A4 PB8 / TIM4_CH3 / SDIO_D4 [I2C1_SCL / CANRX] EEPROM_WP PB9 / TIM4_CH4 / SDIO_D5 [I2C1_SDA / CANTX ] 0R CTRLMCU_I2C_SCL J7 K7 PB10 / I2C2_SCL / USART3_TX [TIM2_CH3] AEM_SENSE_VOLTAGE CTRLMCU_I2C_SDA PB11 / I2C2_SDA / USART3_RX [TIM2_CH4] AEM_SENSE_CURRENT_RANGE1 CTRLMCU_SPI_#CS K8 J8 PB12 / SPI2_NSS / I2S2_WS / I2C2_SMBAI / USART3_CK / TIM1_BKIN CTRLMCU_SPI_SCK PB13 / SPI2_SCK / I2S2_CK / USART3_CTS / TIM1_CH1N R297 CTRLMCU_SPI_MISO H8 0R G8 PB14 / SPI2_MISO / TIM1_CH2N / USART3_RTS CTRLMCU_SPI_MOSI PB15 / SPI2_MOSI / I2S2_SD / TIM1_CH3N R298 F1 0R F2 PC0 / ADC123_IN10 PC1 / ADC123_IN11 AEM_SENSE_CURRENT_RANGE2 E2 PORT C F3 PC2 / ADC123_IN12 CTRLMCU_TRACE_LED_R G4 PC3 / ADC123_IN13 R359 CTRLMCU_TRACE_LED_G H4 PC4 / ADC12_IN14 0R F10 PC5 / ADC12_IN15 DEBUG_DH_SW_ENABLE PC6 / I2S2_MCK / TIM8_CH1 / SDIO_D6 [TIM3_CH1] AEM_AUX_SENSE_VOLTAGE DEBUG_MCU_SW_ENABLE E10 F9 PC7 / I2S3_MCK / TIM8_CH2 / SDIO_D7 [TIM3_CH2] DEBUG_VTARGET_VMCU_CONNECT PC8 / TIM8_CH3 / SDIO_D0 [TIM3_CH3] TRACE_BUF_#OE E9 B9 PC9 / TIM8_CH4 / SDIO_D1 [TIM3_CH4] CTRLMCU_RS232_TX B8 PC10 / UART4_TX / SDIO_D2 [USART3_TX] CTRLMCU_RS232_RX C8 PC11 / UART4_RX / SDIO_D3 [USART3_RX] PC12 / UART5_TX / SDIO_CK [USART3_CK] CTRLMCU_FPGA_#INT FPGA_CFG_D2 A2 A1 PC13 / TAMPER-RTC B1 PC14 / OSC32_IN CTRLMCU_STATUS_R PC15 / OSC32_OUT Bootloader Halt CTRLMCU_STATUS_G STM32F103VEH TP157 B 3V3 B P21 2 1 4 3 CTRLMCU_#TRST CTRLMCU_JTAG_#TRST 6 5 CTRLMCU_TDI CTRLMCU_JTAG_TDI 8 7 CTRLMCU_TMS_SWDIO CTRLMCU_JTAG_TMS 10 9 CTRLMCU_TCK_SWCLK CTRLMCU_JTAG_TCK 12 11 CTRLMCU_RTCK 14 13 CTRLMCU_TDO_SWD CTRLMCU_JTAG_TDO 16 15 CTRLMCU_DEBUG_#RESET 18 17 20 19

HEADER_2X10_2.54MM_SMD NM

GND GND

3V3 3V3 3V3 3V3 3V3 TOP TRACE LED DEBUG LED STATUS LED Schematic Title R443 R444 R241 R445 R446 A 1K 1K 2K 1K 1K A EFM32 Development Kit 2 1 2 1

LED128 RG 2 LED129 RG Page Title LED_G_R LED123 LED_G_R YELLOW Designed: Approved: Control MCU

JNO JNO Revision

4 3 4 3 Document number CTRLMCU_TRACE_LED_R CTRLMCU_STATUS_R Size BOM Doc No: CTRLMCU_TRACE_LED_G CTRLMCU_DEBUG_LED 1 CTRLMCU_STATUS_G A3 BRD3201A A02 Design Created Date: Sheet Created Date Sheet Modified Date Sheet Wednesday, December 03, 2008 Saturday, March 21, 2009 Tuesday, September 06, 2011 11of 22 5 4 3 2 1 5 4 3 2 Control MCU EEPROM 1

TPJ208 3V3 3V3 3V3 3V3 USB LED

R91 R92 R93 R94 2K 4K7 4K7 10K

2 CTRLMCU_I2C_SDA TP167 CTRLMCU_I2C_SCL EEPROM_WP TP168 LED124 TP169 BLUE U18A TP170 D 5 D 6 SDA 1 SCL CTRLMCU_USB_LED 1 U17B A0 CTRLMCU_DATA[15..0] 2 3 A1 7 CTRLMCU_DATA2 FPGA_CFG_D0 FSMC_D2 D8 A2 WP PD0 / OSC_IN / FSMC_D2 [CANRX] CTRLMCU_DATA3 FPGA_CFG_D1 FSMC_D3 E8 24AA024 FPGA_CFG_D2 B7 PD1 / OSC_OUT / FSMC_D3 [CANTX] CTRLMCU_FSMC_CLK PD2 / TIM3_ETR / UART5_RX / SDIO_CMD FPGA_CFG_D3 FSMC_CLK C7 GND GND CTRLMCU_FSMC_#OE PD3 / FSMC_CLK [USART2_CTS] CTRLMCU_FSMC_#WE FPGA_CFG_D4 FSMC_#OE D7 FPGA_CFG_D5 FSMC_#WE B6 PD4 / FSMC_NOE [USART2_RTS] CTRLMCU_FSMC_#WAIT These test points must be placed exactly C6 PD5 / FSMC_NWE [USART2_TX] CTRLMCU_FSMC_#E1 FPGA_CFG_D6 FSMC_#WAIT where the old header was. FPGA_CFG_D7 FSMC_#E1 D6 PD6 / FSMC_NWAIT [USART2_RX] CTRLMCU_DATA13 FPGA_CFG_D8 FSMC_D13 K9 PD7 / FSMC_NE1 / FSMC_NCE2 [USART2_CK] CTRLMCU_DATA14 FPGA_CFG_D9 FSMC_D14 J9 PD8 / FSMC_D13 [USART3_TX] CTRLMCU_DATA15 FPGA_CFG_D10 FSMC_D15 H9 PD9 / FSMC_D14 [USART3_RX] Control MCU SPI Flash CTRLMCU_ADDR16 FPGA_CFG_D11 FSMC_A16 G9 PD10 / FSMC_D15 [USART3_CK] CTRLMCU_ADDR17 FPGA_CFG_D12 FSMC_A17 K10 PD11 / FSMC_A16 [USART3_CTS] CTRLMCU_ADDR18 FPGA_CFG_D13 FSMC_A18 J10 PD12 / FSMC_A17 [USART3_RTS / TIM4_CH1] PD13 / FSMC_A18 [TIM4_CH2] CTRLMCU_DATA0 FPGA_CFG_D14 FSMC_D0 H10 CTRLMCU_SPI_MISO CTRLMCU_DATA1 FPGA_CFG_D15 FSMC_D1 G10 PD14 / FSMC_D0 [TIM4_CH3] 3V3 3V3 CTRLMCU_SPI_MOSI PD15 / FSMC_D1 [TIM4_CH4] U19A CTRLMCU_SPI_#CS FPGA_CFG_#PROG D4 5 2 FPGA_CFG_#PROG CTRLMCU_SPI_SCK FPGA_CFG_DONE C4 PE0 / TIM4_ETR / FSMC_NBL0 D Q FPGA_CFG_DONE CTRLMCU_ADDR23 FPGA_CFG_#INIT FSMC_A23 A3 PE1 / FSMC_NBL1 1 R95 R96 CTRLMCU_ADDR19 FPGA_CFG_#CS FSMC_A19 B3 PE2 / TRACECK / FSMC_A23 S 100K 100K CTRLMCU_ADDR20 FPGA_CFG_CCLK FSMC_A20 C3 PE3 / TRACED0 / FSMC_A19 7 CTRLMCU_ADDR21 FPGA_CFG_RD#WR FSMC_A21 D3 PE4 / TRACED1 / FSMC_A20 6 HOLD 3 C CTRLMCU_ADDR22 FSMC_A22 E3 PE5 / TRACED2 / FSMC_A21 C W C CTRLMCU_DATA4 FSMC_D4 H5 PE6 / TRACED3 / FSMC_A22 M25PX16 CTRLMCU_DATA5 FSMC_D5 J5 PE7 / FSMC_D4 [TIM1_ETR] R341 CTRLMCU_ADDR[23..16] PE8 / FSMC_D5 [TIM1_CH1N] CTRLMCU_DATA6 FSMC_D6 K5 0R CTRLMCU_DATA7 FSMC_D7 G6 PE9 / FSMC_D6 [TIM1_CH1] CTRLMCU_DATA8 FSMC_D8 H6 PE10 / FSMC_D7 [TIM1_CH2N] NM CTRLMCU_DATA9 FSMC_D9 J6 PE11 / FSMC_D8 [TIM1_CH2] CTRLMCU_DATA10 FSMC_D10 K6 PE12 / FSMC_D9 [TIM1_CH3N] PE13 / FSMC_D10 [TIM1_CH3] CTRLMCU_DATA11 FSMC_D11 G7 GND CTRLMCU_DATA12 FSMC_D12 H7 PE14 / FSMC_D11 [TIM1_CH4] PE15 / FSMC_D12 [TIM1_BKIN]

STM32F103VEH

3V3

R97 4K7

3V3 U19B B 8 B Control MCU Power & Bypass VCC TP160 C90 3V3 ADC_VREF 4 10N VSS M25PX16 R281 R280 U17C 10R 1K

C1 B2 GND

CTRLMCU_CLK 1 D1 OSC_IN VBAT ADC_VREF OSC_OUT C91 C255 C254 D5 CTRLMCU_DEBUG_#RESET 3V3 100N 10U 100N LM4040CIM3-2.5 3V3 TP50 U18B 8 R289 2 VCC L10 R98 0R GND 1R C96 4 C92 VSS 3V3 1 2 K1 F7 GND GND GND 10N G1 VDDA VDD_1 F6 24AA024 R266 BLM21B102S VSSA VDD_2 F5 3V3 0R C95 C97 J1 VDD_3 F4 R203 10U 10N H1 VREF+ VDD_4 D2 C100 C101 C102 C103 VREF- VDD_5 1K GND

3V3 10N C99 C105 TOP 2 GND C263 F8 LED89 NC 100N 10U Schematic Title RED 100P E7 A SW8 R99 VSS_1 E6 A 10K D5 VSS_2 E5 100N 100N 100N 100N BOOT0 VSS_3 EFM32 Development Kit - Mainboard 1 3 GND E4 1 VSS_4 E1 C2 GND 2 4 NRST VSS_5 Page Title C98 R331 STM32F103VEH Designed: Approved: Control MCU - Board Control interface 100N GND 0R JNO JNO Document number Revision Size BOM Doc No: GND A3 BRD3201A A02 GND Design Created Date: Sheet Created Date Sheet Modified Date Sheet Wednesday, December 03, 2008 Saturday, March 21, 2009 Thursday, October 13, 2011 12of 22 5 4 3 2 1 3V3 5 4 3 2 1 DH_VTARGET

DH_#TRST 7 DH_TDI R101 DH_TMS_SWDIO DEBUG_TMS_SWDIO_#OE 10K VMCU VMCU VMCU VMCU 3 5 DH_TCK_SWCLK DEBUG_TMS_SWDIO_OUT DH_TDO_SWO DH_#RESET VTARGET U21B 74LVC2G125DC R204 R205 R206 R208 DEBUG_EXT_CABLE_ATTACH 100K 100K 100K 47K P6 NM NM NM NM R371 0R 74LVC4066 U53A 2 1 DH_VTARGET 2 1 RP3 U20A 4 3 DH_#TRST 3 1Z 1Y 4 SW_#TRST 1 8 2 47 DEBUG_#TRST_OUT 6 5 DH_TDI 9 2Z 2Y 8 SW_TDI 2 7 3 1B1 1A1 46 DEBUG_TDI_OUT D 8 7 DH_TMS_SWDIO 10 3Z 3Y 11 SW_TMS_SWDIO 3 6 5 1B2 1A2 44 D 10 9 DH_TCK_SWCLK 4Z 4Y SW_TCK_SWCLK 4 5 6 1B3 1A3 43 DEBUG_TCK_SWCLK_OUT 12 11 DH_RTCK 8 1B4 1A4 41 14 13 DH_TDO_SWO 13 100R 9 1B5 1A5 40 16 15 DH_#RESET 1E 5 11 1B6 1A6 38 2E 1B7 1A7 18 17 6 VTARGET RP22 12 37 GND 3E 1B8 1A8 20 19 12 1 8 13 36 DEBUG_#TRST_IN 4E 2 7 14 2B1 2A1 35 1 2 3 4 5 6 7 8 2B2 2A2 DEBUG_TDI_IN 2X10 2.54MM 3 6 16 33 DEBUG_TMS_SWDIO_IN R102 4 5 17 2B3 2A3 32 2B4 2A4 DEBUG_TCK_SWCLK_IN GND R106 47K 19 30 DEBUG_TDO_SWO_IN R104 R105 100K 33R R303 100R 20 2B5 2A5 29 2B6 2A6 DEBUG_#RESET_IN 100K 100K VESD05A8A-HNH D8 74LVC4066 U54A SW_TDO_SWO 22 27 9 2 1 23 2B7 2A7 26 3 1Z 1Y 4 2B8 2A8 5V supply here? 9 2Z 2Y 8 33R R304 48 3Z 3Y 1OE DEBUG_BUF_#OE GND GND GND GND 10 11 25 4Z 4Y 2OE GND 1 3V3 1DIR 24 13 2DIR 1E 5 DEBUG_HEADER_EN 74LVC16T245 AEM_H_TDO_SWO 2E DEBUG_DH_SW_EN 6 GND 3E 12 5V 4E

R307

1 DEBUG_DH_SW_ENABLE 4K7

DEBUG_DH_SW_EN 6 2 C MCU_SW_EN C DEBUG_MCU_SW_EN MCUDBG_#TRST 74LVC4066 U58A 2 1 5V U61A GND MCUDBG_TDI 1Z 1Y MCUDBG_TMS_SWDIO 3 4 74LVC2G125DC 9 2Z 2Y 8 MCUDBG_TCK_SWCLK 3Z 3Y MCUDBG_TDO_SWO 10 11 4Z 4Y R306

MCUDBG_#RESET 7 DEBUG_MCU_SW_ENABLE 4K7 13 VTARGET 1E 5 DEBUG_MCU_SW_EN 3 5 2E 6 3E 12 4E R103 74LVC2G125DC U61B GND 100K U21A 74LVC2G125DC R107 SW_#RESET 6 2

100R GND 1 DEBUG_#RESET Power & Decoupling Ext. Debug Voltage Measurement 5V VMCU VTARGET

U107 R37 TS5A3159 BVTARGET 3V3 10R 3 B NC 4 DEBUG_VTARGET_VMCU_CONNECT 1 COM NO VTARGET U20B C407 6 5V L16 7 100N 5 IN BLM21B102S 18 VCCB V+ VTARGET R100 100K 31 VCCB 2 1 2 DEBUG_EXT_VDD_TARGET 42 VCCA GND L26 5V VCCA 4 R209 L25 BLM21B102S C106 GND 10 GND 0R BLM21B102S R197 GND 15 2 1 100K 10N C111 C112 GND 21 1 2 GND 28 U53B U54B U58B U61C GND 100N 100N 34 U21C 14 14 14 8 GND GND 39 8 VCC VCC VCC VCC GND 45 VCC C248 C264 C280 GND C110 C247 7 7 7 4 74LVC16T245 4 GND 100N GND 100N GND 100N GND GND 100N 100N 74LVC4066 74LVC4066 74LVC4066 74LVC2G125DC 74LVC2G125DC

GND GND GND GND TOP Schematic Title A A Mode DEBUG_MCU_SW_ENABLE DEBUG_DH_SW_ENABLE DEBUG_BUF_#OE DH_VTARGET VTARGET EFM32 Development Kit - Mainboard

Debug Out 0 1 0 External voltage External voltage Page Title MCU Debug 1 0 0 Disconnected VMCU Designed: Approved: Debug Interface JNO Debug In 1 1 1 VMCU VMCU JNO Document number Revision Size BOM Doc No: A3 BRD3201A A02 Design Created Date: Sheet Created Date Sheet Modified Date Sheet Wednesday, December 03, 2008 Saturday, March 21, 2009 Thursday, October 13, 2011 13of 22 5 4 3 2 1 5 4 3 2 1

D D

3V3 74LVC4066 U96A MCU_TRACE_CLK 2 1 3 1Z 1Y 4 R434 TH_#TRST R469 9 2Z 2Y 8 22R DH_#TRST R433 100R 10 3Z 3Y 11 10K R473 4Z 4Y DH_TMS_SWDIO 100R DH_VTARGET R470 13 U97A TH_VTARGET DH_TCK_SWCLK 100R 1E 5 C380 2 47 TRACE_CLK_OUT P19 R472 2E 6 8P2 3 1B1 1A1 46 DH_TDO_SWO 1 2 TH_TMS_SWDIO 100R 3E 12 5 1B2 1A2 44 R435 TRACE_DATA[3..0] 3 4 TH_TCK_SWCLK R471 4E 6 1B3 1A3 43 22R DH_TDI 1B4 1A4 5 6 TH_TDO_SWO 100R GND 8 41 7 8 TH_TDI R474 9 1B5 1A5 40 DH_#RESET 1B6 1A6 9 10 TH_#RESET 100R GND 11 38 1B7 1A7 11 12 TH_TRACE_CLK 74LVC4066 U98A RP30 12 37 RP31 13 14 TH_TRACE_DATA_0 2 1 1 8 13 1B8 1A8 36 1 8 TRACE_DATA0 15 16 TH_TRACE_DATA_1 3 1Z 1Y 4 2 7 14 2B1 2A1 35 2 7 TRACE_DATA1 17 18 TH_TRACE_DATA_2 9 2Z 2Y 8 3 6 16 2B2 2A2 33 3 6 TRACE_DATA2 19 20 TH_TRACE_DATA_3 10 3Z 3Y 11 4 5 17 2B3 2A3 32 4 5 TRACE_DATA3 R436 R437 4Z 4Y 19 2B4 2A4 30 100K 100K HEADER_2X10_1.27MM_SMD 22R 20 2B5 2A5 29 22R 13 22 2B6 2A6 27 R438 1E 2B7 2A7 GND TPJ203 5 C381 C382 C383 C384 23 26 4K7 TPJ204 TPJ205 TPJ206 TPJ207 2E 6 8P2 8P2 8P2 8P2 2B8 2A8 3E GND GND 12 48 4E 1OE 25 1 2 3 4 5 6 7 8 GND TRACE_BUF_#OE C 2OE 1 C 1DIR 24 2DIR 74LVC16T245 TRACE_EXT_CABLE_ATTACH GND D11 VESD05A8A-HNH 9 GND GND NM GND

DEBUG_HEADER_EN DEBUG_DH_SW_EN

MCU_TRACE_DATA[3..0] 74LVC4066 U99A MCU_TRACE_DATA0 2 1 MCU_TRACE_DATA1 3 1Z 1Y 4 MCU_TRACE_DATA2 9 2Z 2Y 8 5V MCU_TRACE_DATA3 10 3Z 3Y 11 4Z 4Y TRACE_MCU_SW_ENABLE

13 R498 1E 5 4K7 1 2E 6 B 3E 12 4 2 B 4E

74LVC1G125 U111A GND

Mode DEBUG_MCU_SW_ENABLE DEBUG_TH_SW_ENABLE TRACE_BUF_#OE

Trace OUT 0 1 0 MCU Trace 1 0 0 Trace IN 1 1 1

VTARGET 3V3

U97B 7 5V L36 18 VCCB TOP L35 BLM21B102S 31 VCCB 5V BLM21B102S 42 VCCA Schematic Title VCCA A 2 1 4 A 1 2 GND 10 U111B GND 15 EFM32 Development Kit - Mainboard U96B U98B U99B 6 GND 21 14 14 14 VCC C385 C386 GND 28 VCC VCC VCC C417 100N GND 34 Page Title C388 C389 C390 3 5 100N GND 39 100N 7 100N 7 100N 7 GND NC 100N GND 45 Designed: Approved: Trace Interface GND GND GND GND 74LVC1G125 AG JNO 74LVC4066 74LVC4066 74LVC4066 74LVC16T245 Document number Revision Size BOM Doc No: A3 BRD3201A A02 GND Design Created Date: Sheet Created Date Sheet Modified Date Sheet GND GND Wednesday, December 03, 2008 Monday, February 28, 2011 Thursday, October 13, 2011 14of 22 5 4 3 2 1 5 4 3 2 1 EFM32_B[83..0] U8A TS3A4751 RP15 VMCU 3V3 EFM32_B16 2 1 1 8 BC_BUS_AD0 U9B COM1 NO1 EFM32_B17 4 3 2 7 BC_BUS_AD1 BC_AD[15..0] 7 EFM32_B18 9 COM2 NO2 8 3 6 BC_BUS_AD2 VCCB 18 EFM32_B19 10 COM3 NO3 11 4 5 BC_BUS_AD3 U9A VCCB 31 COM4 NO4 2 47 BC_AD0 VCCA 42 BC_BUS_CONNECT_EBI 13 33R 3 1B1 1A1 46 BC_AD1 4 VCCA BC_BUS_CONNECT_EBI 5 IN1 5 1B2 1A2 44 BC_AD2 10 GND 6 IN2 6 1B3 1A3 43 BC_AD3 15 GND 12 IN3 8 1B4 1A4 41 BC_AD4 21 GND R265 IN4 9 1B5 1A5 40 BC_AD5 28 GND 100K 11 1B6 1A6 38 BC_AD6 34 GND C77 C78 C79 C80 1B7 1A7 GND D U10A TS3A4751 RP16 12 37 BC_AD7 39 D EFM32_B20 2 1 1 8 BC_BUS_AD4 13 1B8 1A8 36 BC_AD8 45 GND 100N 100N 100N 100N EFM32_B21 4 COM1 NO1 3 2 7 BC_BUS_AD5 14 2B1 2A1 35 BC_AD9 GND EFM32_B22 9 COM2 NO2 8 3 6 BC_BUS_AD6 16 2B2 2A2 33 BC_AD10 74LVC16T245 COM3 NO3 2B3 2A3 GND EFM32_B23 10 11 4 5 BC_BUS_AD7 17 32 BC_AD11 COM4 NO4 19 2B4 2A4 30 BC_AD12 2B5 2A5 13 33R 20 29 BC_AD13 GND GND GND 5 IN1 22 2B6 2A6 27 BC_AD14 6 IN2 23 2B7 2A7 26 BC_AD15 3V3 12 IN3 2B8 2A8 IN4 48 1OE 25 2OE U11A TS3A4751 RP17 1 R239 1DIR EFM32_B24 2 1 1 8 BC_BUS_AD8 24 1K8 EFM32_B25 4 COM1 NO1 3 2 7 BC_BUS_AD9 2DIR EFM32_B26 9 COM2 NO2 8 3 6 BC_BUS_AD10 74LVC16T245 EFM32_B27 10 COM3 NO3 11 4 5 BC_BUS_AD11

COM4 NO4 2 13 33R LT_EBI LED86 IN1 5 YELLOW 6 IN2 12 IN3 IN4 1

U12A TS3A4751 RP18 3 EFM32_B28 2 1 1 8 BC_BUS_AD12 1 Q8 BC_BUS_CONNECT_EBI EFM32_B29 4 COM1 NO1 3 2 7 BC_BUS_AD13 BC846AW EFM32_B30 9 COM2 NO2 8 3 6 BC_BUS_AD14 R240 EFM32_B31 10 COM3 NO3 11 4 5 BC_BUS_AD15 10K 2 COM4 NO4 C 13 33R GND C 5 IN1 6 IN2 12 IN3 IN4 3V3

BC_AD_BUF_DIR BC_AD_BUF_#OE BC_ALE BC_#WE R310 BC_#RE 1K8 U14A TS3A4751 RP19 U13A EFM32_B32 2 1 1 8 BC_BUS_ARDY 2 47 LT_BUS_SPI EFM32_B33 4 COM1 NO1 3 2 7 BC_BUS_ALE 3 1B1 1A1 46

COM2 NO2 1B2 1A2 2 EFM32_B34 9 8 3 6 BC_BUS_#WE 5 44 BC_#CS[3..0] EFM32_B35 10 COM3 NO3 11 4 5 BC_BUS_#RE 6 1B3 1A3 43 LT_BUS_SPI LED87 COM4 NO4 1B4 1A4 8 41 BC_#CS0 YELLOW 13 33R 9 1B5 1A5 40 BC_#CS1 5 IN1 11 1B6 1A6 38 BC_#CS2 6 IN2 12 1B7 1A7 37 BC_#CS3 12 IN3 13 1B8 1A8 36 1

IN4 2B1 2A1 BC_SPI_SCLK 3 14 35 BC_SPI_#CS 16 2B2 2A2 33 1 Q7 2B3 2A3 BC_SPI_MOSI BC_BUS_CONNECT_SPI U15A TS3A4751 RP20 17 32 BC846AW EFM32_B36 2 1 1 8 BC_BUS_#CS0 19 2B4 2A4 30 R311 EFM32_B37 4 COM1 NO1 3 2 7 BC_BUS_#CS1 20 2B5 2A5 29 10K 2 EFM32_B38 9 COM2 NO2 8 3 6 BC_BUS_#CS2 22 2B6 2A6 27 COM3 NO3 2B7 2A7 EFM32_B39 10 11 4 5 BC_BUS_#CS3 GND 23 26 GND GND COM4 NO4 2B8 2A8 13 33R 48 B 5 IN1 1OE 25 B 6 IN2 2OE 1 12 IN3 1DIR 24 VMCU 3V3 IN4 2DIR 74LVC16T245 R501 U13B U16A TS3A4751 RP21 R502 0R 7 EFM32_B40 2 1 1 8 BC_BUS_SPI_SCLK 0R NM VCCB 18 EFM32_B41 4 COM1 NO1 3 2 7 BC_BUS_SPI_#CS 3V3 3V3 VMCU VCCB 31 EFM32_B42 9 COM2 NO2 8 3 6 BC_BUS_SPI_MOSI VCCA 42 EFM32_B43 10 COM3 NO3 11 4 5 BC_BUS_SPI_MISO U109B 4 VCCA COM4 NO4 GND U109A GND A1 A2 10 BC_BUS_CONNECT_SPI 13 33R B2 B1 R491 VCCA VCCB 15 GND BC_BUS_CONNECT_SPI BC_ARDY 5 IN1 C2 B1 A1 C1 0R C410 C411 21 GND BC_SPI_MISO 6 IN2 B2 A2 28 GND R312 12 IN3 D2 100N D1 100N 34 GND C73 C74 C75 C76 100K IN4 DIR GND 39 GND GND 74LVC2T45 R492 74LVC2T45 45 100N 100N 100N 100N 0R GND NM 74LVC16T245 GND GND BC_SPI_CTRL_BUF_DIR GND GND GND GND BC_SPI_CTRL_BUF_#OE BC_BUS_CTRL_BUF_#OE

Schematic Title A TOP A 3V6 3V6 3V6 3V6 3V6 3V6 3V6 EFM32 Development Kit - Mainboard U12B U14B U11B U8B U16B U10B U15B 14 14 14 14 14 14 14 V+ V+ V+ V+ V+ V+ V+ Page Title C81 C82 C83 C84 C85 C86 C87 7 7 7 7 7 7 7 Designed: Approved: Board Control - EFM32 bus level shift & switch 100N GND 100N GND 100N GND 100N GND 100N GND 100N GND 100N GND JNO TS3A4751 TS3A4751 TS3A4751 TS3A4751 TS3A4751 TS3A4751 TS3A4751 JNO Document number Revision Size BOM Doc No: A3 BRD3201A A02 Design Created Date: Sheet Created Date Sheet Modified Date Sheet GND GND GND GND GND GND GND Wednesday, December 03, 2008 Saturday, March 21, 2009 Thursday, October 13, 2011 15of 22 5 4 3 2 1 5 4 3 2 1

BC_AD[15..0] BC_ALE A[15:0] Latch TP42 TP43

BC_ADDR[22..0] EFM32_A[83..0] D U91A TS3A4751 RP26 U90A D EFM32_A16 EBI_A16 2 1 1 8 BC_AD0 47 2 BC_ADDR0 EFM32_A17 EBI_A17 4 COM1 NO1 3 2 7 BC_AD1 46 1D1 1Q1 3 BC_ADDR1 EFM32_A18 EBI_A18 9 COM2 NO2 8 3 6 BC_AD2 44 1D2 1Q2 5 BC_ADDR2 EFM32_A19 EBI_A19 10 COM3 NO3 11 4 5 BC_AD3 43 1D3 1Q3 6 BC_ADDR3 COM4 NO4 BC_AD4 41 1D4 1Q4 8 BC_ADDR4 13 33R BC_AD5 40 1D5 1Q5 9 BC_ADDR5 BC_BUS_EXT_ADDR_MODE 5 IN1 BC_AD6 38 1D6 1Q6 11 BC_ADDR6 6 IN2 BC_AD7 37 1D7 1Q7 12 BC_ADDR7 12 IN3 BC_AD8 36 1D8 1Q8 13 BC_ADDR8 IN4 BC_AD9 35 2D1 2Q1 14 BC_ADDR9 R430 BC_AD10 33 2D2 2Q2 16 BC_ADDR10 100K BC_AD11 32 2D3 2Q3 17 BC_ADDR11 2D4 2Q4 U92A TS3A4751 RP27 BC_AD12 30 19 BC_ADDR12 EFM32_A20 EBI_A20 2 1 1 8 BC_AD13 29 2D5 2Q5 20 BC_ADDR13 EFM32_A21 EBI_A21 4 COM1 NO1 3 2 7 BC_AD14 27 2D6 2Q6 22 BC_ADDR14 EFM32_A22 EBI_A22 9 COM2 NO2 8 3 6 BC_AD15 26 2D7 2Q7 23 BC_ADDR15 COM3 NO3 2D8 2Q8 GND 10 11 4 5 COM4 NO4 13 33R 5 IN1 48 1 6 IN2 25 1LE 1OE 24 12 IN3 2LE 2OE 74LVCH16373 IN4 R448 100K GND TP215 EFM32_B[83..0] GND U93A TS3A4751 RP28 EFM32_B10 EBI_BL0 2 1 1 8 COM1 NO1 EFM32_B11 EBI_BL1 4 3 2 7 GND U95A C 9 COM2 NO2 8 3 6 2 47 BC_ADDR16 C 10 COM3 NO3 11 4 5 3 1B1 1A1 46 BC_ADDR17 COM4 NO4 5 1B2 1A2 44 BC_ADDR18 13 33R 6 1B3 1A3 43 BC_ADDR19 BC_BUS_CONNECT_EBI 5 IN1 8 1B4 1A4 41 BC_ADDR20 6 IN2 9 1B5 1A5 40 BC_ADDR21 12 IN3 11 1B6 1A6 38 BC_ADDR22 IN4 1B7 1A7 R431 12 37 BC_#BL[1..0] 100K 13 1B8 1A8 36 BC_#BL0 R432 14 2B1 2A1 35 BC_#BL1

2B2 2A2 8 7 6 5 8 7 6 5 0R GND 16 33 2B3 2A3 U94A TS3A4751 RP29 17 32 RP38 RP39 EFM32_B12 EBI_DCLK 2 1 1 8 19 2B4 2A4 30 100K 100K COM1 NO1 2B5 2A5 DISPLAY_DOTCLK GND EFM32_B13 EBI_DATAEN 4 3 2 7 20 29 DISPLAY_OE EFM32_B14 EBI_VSYNC 9 COM2 NO2 8 3 6 22 2B6 2A6 27 DISPLAY_VSYNC 1 2 3 4 1 2 3 4 EFM32_B15 EBI_HSYNC 10 COM3 NO3 11 4 5 23 2B7 2A7 26 COM4 NO4 2B8 2A8 DISPLAY_HSYNC 13 33R 48 BC_ADDR_BUF_#OE0 5 IN1 1OE 25 BC_ADDR_BUF_#OE1 IN2 2OE 6 1 GND 12 IN3 1DIR 24 IN4 2DIR 74LVC16T245 GND GND A[22:16] / TFT signal buffer

B B

BC_ADDR_BUF_#OE[1..0]

Power & Decoupling

3V6 3V6 U94B U93B 14 14 V+ V+ C368 C369 7 7 100N GND 100N GND TS3A4751 TS3A4751 VMCU 3V3 U95B U90B 7 7 TOP VCCB VCC GND GND 18 18 VCCB 31 VCC 31 Schematic Title VCCA VCC A 42 42 A 4 VCCA 4 VCC 3V3 3V6 3V6 10 GND 10 GND EFM32 Development Kit - Mainboard U91B U92B 15 GND 15 GND 14 14 21 GND 21 GND V+ V+ 28 GND 28 GND Page Title C370 C371 34 GND C372 C373 C374 C375 34 GND C376 C377 C378 C379 7 7 39 GND 39 GND 100N 100N 100N 100N Designed: Approved: Board Control - EFM32 bus level shift & switch 2 100N GND 100N GND 45 GND 100N 100N 100N 100N 45 GND GND GND JNO TS3A4751 TS3A4751 JNO Document number Revision 74LVC16T245 74LVCH16373 Size BOM Doc No: A3 BRD3201A A02 Design Created Date: Sheet Created Date Sheet Modified Date Sheet GND GND GND GND GND GND GND GND Wednesday, December 03, 2008 Wednesday, March 16, 2011 Thursday, October 13, 2011 16of 22 5 4 3 2 1 5 4 3 2 1 EFM32_A[83..0] EXP32_A[83..0] EFM32_B[83..0] EXP32_B[83..0]

EFM32_A80 TRACE_CONNECT EFM32_A81 EEPROM_WP EFM32_A82 CTRLMCU_I2C_SDA EFM32_A83 CTRLMCU_I2C_SCL U44A TS3A4751 EFM32_B64 2 1 EXP32_B64 SPI_BUS_SCLK SPI_BUS_SCLK EFM32_A32 R499 EFM32_B65 4 COM1 NO1 3 EXP32_B65 PROD_TEST_UART_EFM_TX SPI_BUS_#CS SPI_BUS_#CS EFM32_B66 9 COM2 NO2 8 EXP32_B66 0R SPI_BUS_MOSI SPI_BUS_MOSI EFM32_A33 R500 EFM32_B67 10 COM3 NO3 11 EXP32_B67 PROD_TEST_UART_EFM_RX COM4 NO4 SPI_BUS_MISO SPI_BUS_MISO NM 0R 13 SPI_BUS_CONNECT 5 IN1 A: Pins 0 -> 83 NM 6 IN2 EXP32_B68 D I2C_BUS_SDA D R174 12 IN3 EXP32_B69 I2C_BUS_SCL 100K IN4

U40A TS3A4751 TP156 EFM32_B68 2 1 I2C_BUS_SDA EFM32_B69 4 COM1 NO1 3 GND I2C_BUS_SCL 9 COM2 NO2 8 EXP32_B81 EEPROM_WP 10 COM3 NO3 11 EXP32_B82 COM4 NO4 CTRLMCU_I2C_SDA EXP32_B83 CTRLMCU_I2C_SCL 13 IF_I2C_BUS_CONNECT 5 IN1 6 IN2 12 IN3 EFM32_B72 IN4 BC_BUS_CONNECT_EBI EFM32_B73 BC_BUS_CONNECT_SPI EFM32_B74 R166 MCUDBG_#TRST EFM32_B75 100K MCUDBG_#RESET EFM32_B76 MCUDBG_TDI EFM32_B77 MCUDBG_TCK_SWCLK EFM32_B78 MCUDBG_TMS_SWDIO EFM32_B79 MCUDBG_TDO_SWO GND

EFM32_B82 CTRLMCU_I2C_SDA FPGA_#INT EFM32_B81 EFM32_B83 CTRLMCU_I2C_SCL B: Pins 64 -> 83 C C

EFM32_B[83..0] EXP32_B[83..0] EFM32_B0 EXP32_B0 EFM32_B1 EXP32_B1 EFM32_B2 EXP32_B2 EFM32_B3 EXP32_B3 EFM32_B4 EXP32_B4 EFM32_B5 EXP32_B5

EFM32_B8 EXP32_B8 EFM32_B9 EXP32_B9

B B

B: Pins 0 -> 15

3V6 U44B 3V6 14 U40B V+ 14 C166 V+ 100N 7 C165 GND 100N 7 SPI_BUS_CONNECT TS3A4751 GND IF_I2C_BUS_CONNECT TS3A4751

GND R250 R249 TOP GND 2K 2K Schematic Title A A LT_I2C 2 2 LT_SPI EFM32 Development Kit LED92 LED93 YELLOW YELLOW Switch Indicators Page Title Designed: Approved:

1 1 EXP32 signal assignments #1 JNO JNO Document number Revision GND GND Size BOM Doc No: A3 BRD3201A A02 I2C Bus SPI Bus Design Created Date: Sheet Created Date Sheet Modified Date Sheet Wednesday, December 03, 2008 Saturday, March 21, 2009 Thursday, October 13, 2011 17of 22 5 4 3 2 1 5 4 3 2 1 EFM32_B[83..0]

U37A TS3A4751 RP37 EFM32_B57 2 1 1 8 COM1 NO1 I2S_ETH_SPI_#CS EXP32_B[83..0] EFM32_B45 4 3 2 7 I2S_ETH_SPI_CLK EFM32_B46 9 COM2 NO2 8 3 6 EXP32_B48 I2S_ETH_SPI_MOSI AUDIO_OUT_RIGHT EFM32_B47 10 COM3 NO3 11 4 5 EXP32_B49 COM4 NO4 I2S_ETH_SPI_MISO AUDIO_OUT_LEFT EXP32_B50 AUDIO_IN_RIGHT 13 33R EXP32_B51 I2S_ETH_CONNECT AUDIO_IN_LEFT 5 IN1 6 IN2 R151 12 IN3 D 100K IN4 D U4A TS3A4751 EFM32_B44 2 1 ANALOG_SE_A EFM32_B45 4 COM1 NO1 3 EFM32_B46 9 COM2 NO2 8 EXP32_B52 GND ANALOG_DIFF_N IF_RS232_RX EFM32_B47 10 COM3 NO3 11 EXP32_B55 COM4 NO4 ANALOG_DIFF_P IF_RS232_TX 13 5 IN1 ANALOG_SE_CONNECT 6 IN2 EXP32_B72 ANALOG_DIFF_CONNECT I2S_DATA 12 IN3 EXP32_B73 IN4 I2S_WS EXP32_B74 I2S_SCLK R45 R46 U5A TS3A4751 100K 100K EFM32_B48 2 1 AUDIO_OUT_RIGHT EFM32_B49 4 COM1 NO1 3 COM2 NO2 AUDIO_OUT_LEFT EFM32_B50 9 8 AUDIO_IN_RIGHT EFM32_B51 10 COM3 NO3 11 COM4 NO4 AUDIO_IN_LEFT GND GND 13 5 IN1 AUDIO_OUT_CONNECT 6 IN2 AUDIO_IN_CONNECT 12 IN3 IN4 R47 R48 U35A TS3A4751 100K 100K EFM32_B52 2 1 IF_RS232_RX EFM32_B53 4 COM1 NO1 3 EFM32_B54 9 COM2 NO2 8 EFM32_B55 10 COM3 NO3 11 COM4 NO4 IF_RS232_TX GND GND 13 IF_RS232_UART_CONNECT C 5 IN1 C 6 IN2 IF_RS232_LEUART_CONNECT 12 IN3 IN4 U39A TS3A4751 R253 R439 EFM32_B56 2 1 DISPLAY_TOUCH_Y2 100K 100K EFM32_B57 4 COM1 NO1 3 DISPLAY_TOUCH_Y1 EFM32_B58 9 COM2 NO2 8 DISPLAY_TOUCH_X2 EFM32_B71 10 COM3 NO3 11 COM4 NO4 DISPLAY_TOUCH_X1 GND GND 13 5 IN1 6 IN2 12 IN3 TOUCH_CONNECT IN4

MCU_TRACE_DATA[3..0] R152 100K EFM32_B59 MCU_TRACE_DATA0 EFM32_B60 MCU_TRACE_DATA1 EFM32_B61 MCU_TRACE_DATA2 EFM32_B62 MCU_TRACE_DATA3 EFM32_B63 GND MCU_TRACE_CLK B: Pins 44 -> 63

3V6 3V6 3V6 B U39B U35B U37B B DISPLAY_ENTRY_MODE 14 14 14 AUDIO_OUT_SELECT V+ V+ V+ TOUCH_CONNECT ETHERNET_CONNECT C154 C155 C160 100N 7 100N 7 100N 7 IF_RS232_LEUART_CONNECT GND GND GND IF_RS232_UART_CONNECT AUDIO_IN_CONNECT TS3A4751 TS3A4751 TS3A4751 AUDIO_OUT_CONNECT ANALOG_DIFF_CONNECT ANALOG_SE_CONNECT GND GND GND

R233 R234 R235 R236 R247 R248 R246 R467 R440 R468 3V6 2K 2K 2K 2K 2K 2K 2K 2K 2K 2K 0R R238 U5B 3V6 2 1 14 0R R237 U4B V+ 2 1 14 L19 BLM21B102S C39 V+ 7 L18 BLM21B102S C38 100N GND 7 LT_SE LT_DIFF LT_A_OUT LT_A_IN LT_UART LT_LEUART LT_ETH LT_TOUCH LT_I2S LT_TFT TS3A4751 100N GND Power & Bypass TS3A4751

GND GND 2 2 2 2 2 2 2 2 2 2 LED94 LED95 LED96 LED97 LED98 LED101 LED99 LED130 LED127 LED131 TOP YELLOW YELLOW YELLOW YELLOW YELLOW YELLOW YELLOW YELLOW YELLOW YELLOW Schematic Title

A 1 1 1 1 1 1 1 1 1 1 A EFM32 Development Kit - Mainboard GND GND GND GND GND GND GND GND GND GND Page Title Single Ended Differential Audio Out Audio In UART LEUART Ethernet TouchI2S connected TFT Direct Mode Designed: Approved: EXP32 signal assignments #2 JNO JNO Document number Revision Size BOM Doc No: Switch Indicators A3 BRD3201A A02 Design Created Date: Sheet Created Date Sheet Modified Date Sheet Wednesday, December 03, 2008 Saturday, March 21, 2009 Thursday, October 13, 2011 18of 22 5 4 3 2 1 5 4 3 2 1 EFM32_B[83..0]

EFM32_A[83..0] 3V3 VMCU_M_CPU2 P13 VMCU_M_CPU2 3V3 3V3 VMCU_M P14 VMCU_M 3V3

2 1 2 1 4 3 4 3 6 5 6 5 8 7 8 7 10 9 10 9 EFM32_A0 12 11 EFM32_A40 EFM32_B0 12 11 EFM32_B40 EFM32_A1 14 13 EFM32_A41 EFM32_B1 14 13 EFM32_B41 D EFM32_A2 16 15 EFM32_A42 EFM32_B2 16 15 EFM32_B42 D EFM32_A3 18 17 EFM32_A43 EFM32_B3 18 17 EFM32_B43 20 19 EFM32_A44 20 19 EFM32_A4 22 21 EFM32_A45 EFM32_B4 22 21 EFM32_B44 EFM32_A5 24 23 EFM32_A46 EFM32_B5 24 23 EFM32_B45 EFM32_A6 26 25 EFM32_A47 EFM32_B6 26 25 EFM32_B46 EFM32_A7 28 27 RP40 EFM32_B7 28 27 EFM32_B47 30 29 1 8 EFM32_A50 30 29 EFM32_A8 32 31 2 7 EFM32_A49 EFM32_B8 32 31 EFM32_B48 EFM32_A9 34 33 3 6 EFM32_A48 EFM32_B9 34 33 EFM32_B49 EFM32_A10 36 35 4 5 EFM32_B10 36 35 EFM32_B50 EFM32_A11 38 37 EFM32_B11 38 37 EFM32_B51 40 39 0R EFM32_A51 40 39 EFM32_A12 42 41 EFM32_A52 EFM32_B12 42 41 EFM32_B52 EFM32_A13 44 43 EFM32_A53 EFM32_B13 44 43 EFM32_B53 EFM32_A14 46 45 EFM32_A54 EFM32_B14 46 45 EFM32_B54 EFM32_A15 48 47 EFM32_A55 EFM32_B15 48 47 EFM32_B55 50 49 50 49 EFM32_A16 52 51 EFM32_A56 EFM32_B16 52 51 EFM32_B56 EFM32_A17 54 53 EFM32_A57 EFM32_B17 54 53 EFM32_B57 EFM32_A18 56 55 EFM32_A58 EFM32_B18 56 55 EFM32_B58 EFM32_A19 58 57 EFM32_A59 EFM32_B19 58 57 EFM32_B59 60 59 60 59 EFM32_A20 62 61 EFM32_A60 EFM32_B20 62 61 EFM32_B60 EFM32_A21 64 63 EFM32_A61 EFM32_B21 64 63 EFM32_B61 EFM32_A22 66 65 EFM32_A62 EFM32_B22 66 65 EFM32_B62 EFM32_A23 68 67 EFM32_A63 EFM32_B23 68 67 EFM32_B63 70 69 70 69 EFM32_A24 72 71 EFM32_A64 EFM32_B24 72 71 EFM32_B64 EFM32_A25 74 73 EFM32_A65 EFM32_B25 74 73 EFM32_B65 C EFM32_A26 76 75 EFM32_A66 EFM32_B26 76 75 EFM32_B66 C EFM32_A27 78 77 EFM32_A67 EFM32_B27 78 77 EFM32_B67 80 79 RP41 80 79 EFM32_A28 82 81 1 8 EFM32_A68 EFM32_B28 82 81 EFM32_B68 EFM32_A29 84 83 2 7 EFM32_A69 EFM32_B29 84 83 EFM32_B69 EFM32_A30 86 85 3 6 EFM32_A70 EFM32_B30 86 85 EFM32_B70 EFM32_A31 88 87 4 5 EFM32_A71 EFM32_B31 88 87 EFM32_B71 90 89 90 89 EFM32_A32 92 91 EFM32_A72 0R EFM32_B32 92 91 EFM32_B72 EFM32_A33 94 93 EFM32_A73 EFM32_B33 94 93 EFM32_B73 EFM32_A34 96 95 EFM32_A74 EFM32_B34 96 95 EFM32_B74 EFM32_A35 98 97 EFM32_A75 EFM32_B35 98 97 EFM32_B75 100 99 100 99 EFM32_A36 102 101 EFM32_A76 EFM32_B36 102 101 EFM32_B76 EFM32_A37 104 103 EFM32_A77 EFM32_B37 104 103 EFM32_B77 EFM32_A38 106 105 EFM32_A78 EFM32_B38 106 105 EFM32_B78 EFM32_A39 108 107 EFM32_A79 EFM32_B39 108 107 EFM32_B79 110 109 110 109 EFM32_A80 112 111 EFM32_A82 EFM32_B80 112 111 EFM32_B82 EFM32_A81 114 113 EFM32_A83 EFM32_B81 114 113 EFM32_B83 116 115 116 115 118 117 118 117 120 119 120 119 5V 5V GND BTE_060_01_L_D_A GND GND BTE_060_01_L_D_A GND

B B

VMCU_M VMCU_M_CPU2 VMCU_M 3V3 5V

R364 C211 C212 C213 C214 C215 C216 C217 C218 C219 C221 C222 C223 C224 C225

0R 100N 100N 100N 10U 100N 100N 100N 10U 10U 100N 100N 100N 10U 10U NM

GND GND GND TOP Schematic Title

A VMCU_M_CPU2 3V3 5V A EFM32 Development Kit - Mainboard

C227 C228 C229 C230 C231 C232 C233 C234 C235 C237 C238 C239 C240 C241 Page Title

100N 100N 100N 10U 100N 100N 100N 10U 10U 100N 100N 100N 10U 10U Designed: Approved: EFM32 Board Connectors NM JNO JNO Document number Revision Size BOM Doc No: GND GND GND A3 BRD3201A A02 Design Created Date: Sheet Created Date Sheet Modified Date Sheet Wednesday, December 03, 2008 Saturday, March 21, 2009 Thursday, October 13, 2011 19of 22 5 4 3 2 1 5 4 3 2 1

EXP32_B[83..0]

EXP32_A[83..0] 3V3 VMCU_M_EXP2 P11 VMCU_M_EXP2 3V3 3V3 VMCU_M P12 VMCU_M 3V3

2 1 2 1 4 3 4 3 6 5 6 5 8 7 8 7 D 10 9 10 9 D EXP32_A0 12 11 EXP32_A40 EXP32_B0 12 11 EXP32_A1 14 13 EXP32_A41 EXP32_B1 14 13 EXP32_A2 16 15 EXP32_A42 EXP32_B2 16 15 EXP32_A3 18 17 EXP32_A43 EXP32_B3 18 17 20 19 20 19 EXP32_A4 22 21 EXP32_A44 EXP32_B4 22 21 EXP32_A5 24 23 EXP32_A45 EXP32_B5 24 23 EXP32_A6 26 25 EXP32_A46 26 25 EXP32_A7 28 27 EXP32_A47 28 27 30 29 30 29 EXP32_A8 32 31 EXP32_A48 EXP32_B8 32 31 EXP32_B48 EXP32_A9 34 33 EXP32_A49 EXP32_B9 34 33 EXP32_B49 EXP32_A10 36 35 EXP32_A50 36 35 EXP32_B50 EXP32_A11 38 37 EXP32_A51 38 37 EXP32_B51 40 39 40 39 EXP32_A12 42 41 EXP32_A52 42 41 EXP32_B52 EXP32_A13 44 43 EXP32_A53 44 43 EXP32_A14 46 45 EXP32_A54 46 45 EXP32_A15 48 47 EXP32_A55 48 47 EXP32_B55 50 49 50 49 EXP32_A16 52 51 EXP32_A56 52 51 EXP32_A17 54 53 EXP32_A57 54 53 EXP32_A18 56 55 EXP32_A58 56 55 EXP32_A19 58 57 EXP32_A59 58 57 60 59 60 59 EXP32_A20 62 61 EXP32_A60 62 61 EXP32_A21 64 63 EXP32_A61 64 63 EXP32_A22 66 65 EXP32_A62 66 65 C EXP32_A23 68 67 EXP32_A63 68 67 C 70 69 70 69 EXP32_A24 72 71 EXP32_A64 72 71 EXP32_B64 EXP32_A25 74 73 EXP32_A65 74 73 EXP32_B65 EXP32_A26 76 75 EXP32_A66 76 75 EXP32_B66 EXP32_A27 78 77 EXP32_A67 78 77 EXP32_B67 80 79 80 79 EXP32_A28 82 81 EXP32_A68 82 81 EXP32_B68 EXP32_A29 84 83 EXP32_A69 84 83 EXP32_B69 EXP32_A30 86 85 EXP32_A70 86 85 EXP32_A31 88 87 EXP32_A71 88 87 90 89 90 89 EXP32_A32 92 91 EXP32_A72 92 91 EXP32_B72 EXP32_A33 94 93 EXP32_A73 94 93 EXP32_B73 EXP32_A34 96 95 EXP32_A74 96 95 EXP32_B74 EXP32_A35 98 97 EXP32_A75 98 97 100 99 100 99 EXP32_A36 102 101 EXP32_A76 102 101 EXP32_A37 104 103 EXP32_A77 104 103 EXP32_A38 106 105 EXP32_A78 106 105 EXP32_A39 108 107 EXP32_A79 108 107 110 109 110 109 EXP32_A80 112 111 EXP32_A82 112 111 EXP32_B82 EXP32_A81 114 113 EXP32_A83 EXP32_B81 114 113 EXP32_B83 116 115 116 115 118 117 118 117 120 119 5V 120 119 5V

B GND BTE_060_01_L_D_A GND GND BTE_060_01_L_D_A GND B

VMCU_M 3V3 5V

C179 C180 C181 C182 C183 C184 C185 C187 C188 C189 C190 C191 C192 C193 VMCU_M VMCU_M_EXP2 100N 100N 100N 10U 100N 100N 100N 10U 10U 100N 100N 100N 10U 10U NM R365 GND GND GND 0R TOP Schematic Title

A VMCU_M_EXP2 3V3 5V A EFM32 Development Kit - Mainboard

C195 C196 C197 C198 C199 C200 C201 C202 C203 C205 C206 C207 C208 C209 Page Title

100N 100N 100N 10U 100N 100N 100N 10U 10U 100N 100N 100N 10U 10U Designed: Approved: EXP32 Board Connectors NM JNO JNO Document number Revision Size BOM Doc No: GND GND GND A3 BRD3201A A02 Design Created Date: Sheet Created Date Sheet Modified Date Sheet Wednesday, December 03, 2008 Saturday, March 21, 2009 Thursday, October 13, 2011 20of 22 5 4 3 2 1 5 4 3 2 1 Power Input 5V_UNSWITCHED TP117 5V FPGA core voltage regulator J3 5V_CON 5V L4 BLM41P600S TP116 D2 L12 2UH2 Q9 FPGA_1V2 1 1 2 1 D7 ZEN056V130 DMP4051 5V TP121 3 4 1 3 3 2 L15 R231 2 3 R133 0R U73 L7 2UH2 1K 1 2 1 5 12CWQ03FN R217 C244 L17 2UH2 C245 R216 VIN SW 1 RAPC722X 1K 10U 10U 1K BLM41P600S C297 2 GND R372 C136 C137 LED122 2 C138 C139 3 0R 30P GREEN 2 R385 2 EN NM 10U 100N P8 TYCO_292304_1 LED120 GND GND GND LED119 C135 10U 100N 2 4 D 10K GND FB D GREEN GREEN 100N NM 1 GND LM3674MF-1.2 R373 3 6 1 2 5 GND GND GND 0R GND GND 1 Q3 4 3 1 1 NM BC846AW R232 2 GND PWR_FET_ENABLE GND 10K GND 4 3 2 1 L6 3.3V power regulator TPJ200 GND TPJ165 TPJ164 TP119 TP163 3V3 1 2 5V L13 R230 BLM41P600S U72 LM2830ZSD L8 2UH2 1K GND 1 2 5 3 TPJ201 4 VINA SW 1 USBDM BLM41P600S R369 VIND Power switch 100K R138 2 USBDP R386 4K7 C142 C143 6 D9 45K3 LED121 EN C140 C141 GREEN TPJ185 22U 100N 2 1 2 U78B U78A 7 GND FB 22U 100N DAP 3 4 1 6 PWR_FET_ENABLE R139 1 10K GND GND GND GND GND GND GND 74LVC2G14GW 74LVC2G14GW SW11 R387 TPJ202 220K GND C 1 3 3.6V power regulator C 2 4 C301 5V TP166 3V6 R388 1M 100N Power Monitoring U70 2 1 IN OUT1 4 R366 OUT2 R367 GND C145 C294 10K 5 3.64V 130K 7 SET C146 C296 10U 100N SHDN 8 R368 10U 100N FAULT 3 68K 9 GND 6 GND_HEAT CC GND GND C295 PWR_MON_ADC_MOSI LP3982ILD-ADJ PWR_MON_ADC_MISO GND GND GND 33N PWR_MON_ADC_#CS GND PWR_MON_ADC_CLK AEM_CTRL[3..0] GND U106A ADS7959 25 29 AEM_CTRL0 26 SDI GPIO0 / ALARM 30 AEM_CTRL1 23 SDO GPIO1 / ALARM 1 AEM_CTRL2 ADC_VREF 24 CS GPIO2 / RANGE 2 AEM_CTRL3 5V_UNSWITCHED SCLK GPIO3 / PD Decoupling U78C POWERMON_VREF 4 R475 10M 5 B REFP VCC B LT_SE FPGA_1V2_SENSE 20 7 C302 C397 3V3_SENSE 19 CH0 MXO R476 10M 2 100N RAM_VCORE_SENSE 18 CH1 GND 100N LT_DIFF 3V6_SENSE 17 CH2 74LVC2G14GW 5V_CON_SENSE 14 CH3 R477 10M LED_TEST 13 CH4 LT_A_OUT 12 CH5 3V3 R452 3V3 GND DISPLAY_KSENSE GND 11 CH6 R478 10M 1R U106B ADS7959 DISPLAY_ASENSE CH7 3 LED_TEST 5 28 LT_A_IN 8 REFM 9 21 +VA +VBD M2 AINP AINM C416 R479 10M +VA TP81 TP82 TP84 1N C398 C399 C400 M1 LT_UART 10U 100N HOLE_PTH_3MM R480 10M 6 100N 10 AGND HOLE_PTH_3MM M3 LT_LEUART AGND GND 22 27 GND GND GND

AGND NC1 NC2 BDGND GND R481 10M TP85 TP86 TP87 R258 HOLE_PTH_3MM LT_ETH 15 16 GND 0R R482 10M GND M4 LT_TOUCH R483 10M GND GND GND GND HOLE_PTH_3MM LT_I2S FPGA_1V2 RAM_VCORE 3V3 3V6 5V_CON TOP R484 10M Schematic Title LT_TFT A R286 R282 R284 R453 R454 R485 10M A 1K 1K 10K 10K 47K LT_SPI EFM32 Development Kit - Mainboard FPGA_1V2_SENSE RAM_VCORE_SENSE 3V3_SENSE 3V6_SENSE 5V_CON_SENSE R486 10M Page Title LT_I2C C259 C257 C258 C401 C402 R287 R283 R285 R455 R456 R487 10M Designed: Approved: Main Power Regulators 100N 100N 100N 100N 100N 100K 100K 10K 10K 4K7 LT_EBI JNO JNO Document number Revision R488 10M Size BOM Doc No: A02 LT_BUS_SPI A3 BRD3201A Design Created Date: Sheet Created Date Sheet Modified Date Sheet GND GND GND GND GND Wednesday, December 03, 2008 Saturday, March 21, 2009 Thursday, October 13, 2011 21of 22 5 4 3 2 1 MCU power regulators5 4 3 100mA calibration switch 2 5V 1 5V R389 TP112 TP114 VMCU_R VMCU_S U26 0R VMCU_M R120 TS5A3159 TP171 U27 0R Bleeder Resistor 3 2 1 R121 4 NC IN OUT1 4 COM 1 1 2 4R7 R215 OUT2 NO 3 4 10K 5 R358 C121 C122 R390 6 C303 7 SET 10U 100N 10M IN 5 ST3 U101A 1R8

SHDN V+ NM 100N

1 8 U68A VMCU_S_BUF + 3 2 GND FAULT GND C120 C123 3 GND GND C260

GND W 100N 10U 9 6 C287 GND GND GND_HEAT CC R348 100N

D 8 7 1 1 D A B 33N R391

LP3982ILD-ADJ 18K AEM_VMCU_ENABLE

C286 100R TLV272 - 33N R123 2 AEM_H_TDO_SWO 56K AD5245-100K GND GND GND GND GND GND 5V

GND

R128 5V 1K TP172 TP174 TP176 VMCU_S_BUF TP173 TP175 L29

TLV272 R393 U79A TS3A4751 2 5 + 2 1 2 1 BLM21B102S LED102 4 COM1 NO1 3 R392 C304 Q10 3 33R 9 COM2 NO2 8

GREEN COM3 NO3 47K 2 7 1 TP158 VMCU 10 11 1N MCU power switch LED COM4 NO4

BC846AW AEM_CTRL0 13 2 1 6 - AEM_CTRL1 5 IN1 R396 R395 R397 R398

3 IN2 GND Q5 AEM_CTRL2 6 1K 22K 47K 1M U101B C306 1 AEM_CTRL3 12 IN3 AEM_VMCU_ENABLE R402 BC846AW IN4 4K7 10U R242 2 AEM_CTRL[3..0] 10K

C GND GND GND GND C

VMCU_R VMCU_S VMCU_R VMCU_S C194 TP137 C210 TP138 1N 1N VCS VCS R124 R291 R125 R292 1K8 U29 43R R377 R378 4R7 U30 0R R379

10K 10K U75A TLV272 10K U75B TLV272

+ C125 1 8 3 + C126 1 8 5 100N 2 -INS IN+ 100N 2 -INS IN+

L22

5V -INF -INF R380

2 6 C186 1 1 6 10K C204 7 AEM_SENSE_CURRENT_RANGE1 AEM_SENSE_CURRENT_RANGE2

2 1 7 VREG 1N 7 VREG 1N

V+ V+

- BLM21B102S R293 3 2 - 3 6 V- V- 0R 5 4 GND 5 4 GND C261 9 V- OUT 9 V- OUT 10U V- (HEAT) V- (HEAT) R126 R375 R376 R127 R382 LTC6102CDD 12K 1K 0R LTC6102CDD 10K R381 0R GND GND NM GND 1K NM MCU power current sense GND GND GND GND

BPower & Decoupling VMCU voltage sense B

5V L28 BLM21B102S VMCU VMCU_S_BUF 1 2 R374 1R U101C R334 R332 AEM_AUX_SENSE_VOLTAGE AEM_SENSE_VOLTAGE C298 C299 8 1U 100N VDD 47K 47K R335 C273 R333 C272 47K 47K 4 1N 1N GND TLV272

GND GND GND

TOP 5V 5V L27 BLM21B102S Schematic Title L23 A 3V6 A 2 1 R355 1 2 R361 EFM32 Development Kit - Mainboard U79B 1R 1R BLM21B102S U68B U75C 14 C283 R357 2 C282 C291 C278 8 V+ Page Title 1U 10K VDD 1U 100N VDD C391 4 100N 100N 7 Designed: Approved: EFM Power and AEM 5 SCL GND SDA JNO JNO GND 6 3 4 TS3A4751 Document number Revision AD0 GND GND Size BOM Doc No: TLV272 A3 BRD3201A A02 CTRLMCU_I2C_SCL AD5245-100K CTRLMCU_I2C_SDA Design Created Date: Sheet Created Date Sheet Modified Date Sheet GND GND GND Wednesday, December 03, 2008 Wednesday, August 19, 2009 Thursday, October 13, 2011 22of 22 5 4 3 2 1