FDXcellerator and the growing 22FDX ® ecosystem

Dr. Gerd Teepe, Director Marketing for Technology Effects are Accelerating

© 2017 GLOBALFOUNDRIES 2 GLOBALFOUNDRIES Dual Track Roadmap

Markets Markets . Servers High Performance Wireless, . Low & mid-end Computing Battery-powered Computing . HPC / core networking smartphones . Wireless . Graphics EUV . High-end smartphones eNVM . IoT

7nm TM 12FDX . Autonomous vehicles FinFET Premium Tier . Mobile cameras

Features Volume Tier . High performance 7.5T

. Balanced cost RF eNVM Features Auto . Low power 12/14nm 22FDX® FinFET . Cost-effective performance . RF 28nm 40/55nm . Embedded memory

© 2017 GLOBALFOUNDRIES 3 22FDX® Markets: Targeted To Serve Key Segments

Mobility IoT RF & mmWave Automotive AP/MPU/AI BLE/NB-IoT / GPS/NFC 5G/LTE/WiFi MCU/Radar/ADAS/IVI

Body-bias equivalent to +1 node Natural migration from 55/40nm Enables new RF architectures Integration for car of tomorrow • Cortex®-A53 w/ 40% lower power • Lower active (-80%) and standby • Highest ft/fmax • MCU w/ integrated eMRAM and vs. 28HKMG (1pA/cell) power than 40nm • Up to 30-50% area savings vs. 5v MOS device for ADC • Roadmap to 7nm perf. w/ • PA, Switch, PMIC, eMRAM 28nm • mmWave for long-range radar 12FDX™ • Only 36 masks • mmWave PA via SOI-stacking • Low power ADAS

Value Extends Across Multiple Product Lines

© 2017 GLOBALFOUNDRIES 4 Digital Reference Flows, PDK Enablement with Foundation IP

Synopsys Certified Reference Flow Cadence Certified Reference Flow Place & Route Genus SYNTHESIS Design Compiler LVS Ansys SYNTHESIS

Formality PEX Cadence Conformal FORMAL FORMAL (RTL vs Gate Netlist) (RTL vs Gate Netlist) VERIFICATION VERIFICATION DRC Mentor IC Compiler, IC Compiler II Innovus PLACE & ROUTE IC Validator (In-design) SPICE PLACE & ROUTE PVS (In-design)

Formality Fill Conformal FORMAL FORMAL (Gate \vs Routed Netlist) (Gate vs Routed Netlist) VERIFICATION *Some by request VERIFICATION EM/IR *Additional vendor StarRC support available Quantus PEX Custom Design PEX PrimeTime Tempus STA STA Std cell lib PDK

Tape-out GF Digital Design Reference Includes sample block tested at all proven Flow Flow RTL-to-GDS steps with Sign-off

SADP-Aware

Color-Aware FDSOI-Aware Variability-Aware Implant-Aware DFM-Aware

Variability

Path Depth

7LP 7LP, 14LPP, 22FDX® 12FDX® 7LP, 14LPP, 7LP, 14LPP, 7LP, 14LPP, 5 22FDX® 12FDX® 22FDX® 12FDX® 22FDX® 12FDX® 22FDX® 12FDX®

AMS Reference Flow

AMS Design Capabilities Pre-Layout Functional Verification ADE-XL/MMSIM, Hspice

Prelayout Ver Custom Layout Virtuoso/CustomCompiler Ansys

Schematic-XL/Layout-XL Custom Layout Layout-LDE Cadence Accelerated Custom Layout Layout-EAD Virtuoso Mentor

MSOA Interoperability Synopsys Virtuoso/INNOVUS MSOA Interop *Some by request *Additional vendor Physical Verification Calibre, PVS, ICV Physical Verification support available

Parasitic Extraction StarRC, QRC, xRC* Paras Extraction

Post Layout Functional Post-Layout Functional Verification ADE-XL/MMSIM, Hspice Ver

EM/IR EMIR Totem, Voltus-Fi

Fill, DFM FILL, DFM Calibre, PVS, ICV

© 2017 GLOBALFOUNDRIES 6 Ecosystem Partnering for Growth

Reduce time to market and facilitate FDX™ SoC product design

. Easy access to plug and EDA play solutions OSAT IP

Design . Minimizes customer ASIC development costs Services

Embedded System . Lowers barriers of Software IP migration

© 2017 GLOBALFOUNDRIES 7 Bernin, France Building Global Scale for FDX™ . FD-SOI substrates From Substrates to Fabs . 400kw/ year capacity . Already qualified, in mass production

Dresden, Fab 1 . Expanding 22FDX® FD-SOI capacity by 40% by 2020 . Developing 12FDX™ FD-SOI technology Chengdu, China Fab 11 . New 300mm fab . Partnership w/ Chengdu Municipal Government . Existing 180/130nm nodes, GF and SOITEC Partnership Pasir Ris, Singapore 22FDX ramp in 2H 2019 . FD-SOI substrates . Multi-fab sourcing . SOI HVM qualified in 2007 . Multiple substrate supply . FD-SOI production line started . Long term supply agreement . End customer qual, in 1H 2019 . Full capacity of 800kw/ year

GLOBALFOUNDRIES Confidential 8 Manufacturing Strength: Europe’s Largest & Most Advanced Fab

Phase 5 Phase 2 ~ 12.000 m² ~ 2.500 m² (2011) Phase 3 (2002) Phase 1 Phase 4 ~ 14.000 m² ~ 14.000 m² (1999) ~ 10.000 m² (2005) (2007)

• ~3,400 employees • Investment of ~$12B since 1996 • ~2x indirect jobs regionally • ~$6B invested from 2009 alone • Main engine of “Silicon “ Cluster • Extensive R&D network

© 2017 GLOBALFOUNDRIES 9 FDXTM Ecosystem: Collaborative European Supply Chain Model

Design & EDA Partners Memory & OSAT Partners

Thin, BSI Design Mask Sets Substrates Wafer Fab Bump Probe Assembly & Test

© 2017 GLOBALFOUNDRIES 10 Summary

• Market: Growing Client Device Data Traffic requires next Generation Technologies

• GLOBALFOUNDRIES Dual Roadmap

• Design Readiness and -Ecosystem

• 22FDX Supply Chain

© 2017 GLOBALFOUNDRIES 11 Thank you

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