Intel® Atom™ Z8000 Processor Series

Datasheet (Volume 1 of 2)

For Volume 2 of 2 refer Document ID: 332066 March 2016 Revision 003

Document Number: 332065-003 You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps. Tests document performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit http://www.intel.com/performance. Copies of documents which have an order number and are referenced in this document may be obtained by calling 1-800-548-4725 or visit www.intel.com/design/literature.htm. Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, updated BIOS, and virtual machine monitor (VMM). Functionality, performance or other benefits will vary depending on hardware and software configurations. Software applications may not be compatible with all operating systems. Check with your system manufacturer. Learn more at http://www.intel.com/go/virtualization. Intel, Intel Atom and the Intel logo, are trademarks of Intel Corporation in the U.S. and/or other countries. *Other names and brands may be claimed as the property of others. See Trademarks on intel.com for full list of Intel trademarks. © 2015-2016 Intel Corporation.

2 Datasheet 

Contents

1Introduction...... 15 1.1 References ...... 15 1.2 Terminology ...... 15 1.3 SoC Packages ...... 17 1.4 Feature Overview ...... 20 1.4.1 Processor Core...... 20 1.4.2 System Memory Controller...... 20 1.4.3 Display Controller ...... 20 1.4.4 Graphics and Media Engine ...... 21 1.4.5 Image Signal Processor ...... 21 1.4.6 ...... 21 1.4.7 PCI Express* ...... 21 1.4.8 USB Controller ...... 22 1.4.9 Low Power Engine (LPE) Audio Controller...... 22 1.4.10 Storage...... 22 1.4.11 Intel® Trusted Execution Engine (Intel® TXE) ...... 22 1.4.12 Serial I/O (SIO) ...... 23 1.4.13 Platform Control Unit (PCU) ...... 23 1.4.14 Intel®Sensor Hub...... 23 1.4.15 Package ...... 23 1.4.16 SKU List...... 24 2Physical Interfaces ...... 25 2.1 Pin States...... 25 2.2 System Memory Controller Interface Signals ...... 27 2.2.1 DDR3L-RS ...... 27 2.2.2 LPDDR3 ...... 28 2.3 USB Controller Interface Signals...... 30 2.3.1 USB2.0 Interface Signals...... 30 2.3.2 USB HSIC Interface Signals ...... 30 2.3.3 USB3.0 Interface Signals...... 31 2.4 Integrated Clock Interface Signals ...... 32 2.5 Display - Digital Display Interface (DDI) Signals ...... 32 2.6 MIPI DSI Interface Signals...... 33 2.7 MIPI Camera Serial Interface (CSI) and ISP Interface Signals...... 34 2.8 PCI Express Signals ...... 35 2.9 Low Power Engine (LPE) for Audio (I2S) Interface Signals ...... 35 2.10 Storage Interface Signals ...... 36 2.10.1 Storage Controller (eMMC, SDIO, SD) ...... 36 2.11 High Speed UART Interface Signals...... 37 2.12 I2C Interface Signals...... 38 2.13 NFC I2C Interface Signals ...... 39 2.14 PCU- Fast Serial Peripheral Interface (SPI) Signals...... 39 2.15 PCU - Real Time Clock (RTC) Interface Signals ...... 40 2.16 PCU - Low Pin Count (LPC) Bridge Interface Signals ...... 40 2.17 PCU - Power Management Controller (PMC) Interface Signals ...... 41 2.18 Serial Peripheral Interface (SPI) Signals ...... 42 2.19 JTAG Interface Signals ...... 42 2.20 Integrated Sensor Hub Interface Signals...... 42 2.21 PWM Interface Signals ...... 43

Datasheet 3 2.22 SVID Interface Signals ...... 43 2.23 Miscellaneous Signals ...... 44 2.24 Hardware Straps...... 44 2.25 SoC RCOMP List...... 46 2.26 GPIO Muxing...... 47 3 Processor Core...... 74 3.1 Features...... 74 3.1.1 Intel® Virtualization Technology (Intel® VT) ...... 74 3.1.2 Security and Cryptography Technologies...... 76 3.1.3 Power Aware Interrupt Routing...... 77 3.2 Platform Identification and CPUID ...... 77 3.3 References...... 77 4Integrated Clock...... 79 5 Power Up and Reset Sequence ...... 81 5.1 SoC System States ...... 81 5.1.1 System Sleeping States Control (S-states) ...... 81 5.2 Power Up Sequences ...... 81 5.2.1 RTC Power Well Transition (G5 to G3 States Transition) ...... 81 5.2.2 G3 to S4/S5...... 82 5.2.3 S4/S5 to S0 ...... 83 5.3 Power Down Sequences...... 84 5.3.1 S0 to S4/S5 Sequence...... 84 5.3.2 S4/S5 to S0 (Exit Sleep States) ...... 86 5.3.3 Enter S0ix ...... 86 5.3.4 Exit S0ix...... 86 5.3.5 Handling Power Failures...... 88 5.4 Reset Behavior ...... 88 6 Thermal Management ...... 90 6.1 Thermal Sensors...... 90 6.1.1 DTS Timing...... 91 6.2 Hardware Trips...... 92 6.2.1 Catastrophic Trip (THERMTRIP)...... 92 6.3 SoC Programmable Trips ...... 92 6.3.1 Aux3 Trip ...... 92 6.3.2 Aux2, Aux1, Aux0 Trip...... 92 6.4 Platform Trips ...... 92 6.4.1 PROCHOT# ...... 92 6.4.2 EXTTS ...... 93 6.4.3 sVID ...... 93 6.5 Dynamic Platform Thermal Framework (DPTF) ...... 93 6.6 Thermal Status...... 94 7 Power Management ...... 95 7.1 Features...... 95 7.2 States Supported...... 95 7.2.1 System States...... 95 7.2.2 Interface State Combinations ...... 97 7.2.3 Integrated Graphics Display States ...... 98 7.2.4 Integrated Memory Controller States...... 98 7.3 Processor Core Power Management ...... 99 7.3.1 Enhanced Intel SpeedStep® Technology ...... 99

4 Datasheet 

7.3.2 Dynamic Cache Sizing* ...... 100 7.3.3 Low-Power Idle States ...... 100 7.3.4 Processor Core C-States Description ...... 101 7.3.5 Module C-states ...... 103 7.3.6 Module C6 ...... 103 7.3.7 S0i1 ...... 103 7.3.8 Package C-States* ...... 103 7.3.9 Graphics, Video and Display Power Management...... 105 7.4 Memory Power Management ...... 106 7.4.1 Disabling Unused System Memory Outputs ...... 106 7.4.2 DRAM Power Management and Initialization ...... 106 8 System Memory Controller...... 108 8.1 Signal Descriptions ...... 108 8.1.1 DDR3L-RS Interface Signals...... 108 8.1.2 DDR3L-RS Interface Signals ...... 110 8.1.3 LPDDR3 Interface Signals ...... 113 8.1.4 ECC Support ...... 114 8.2 Features ...... 115 8.2.1 System Memory Technology Supported ...... 115 8.3 Register Map ...... 116 9 Graphics, Video and Display...... 117 9.1 Features ...... 117 9.2 SoC Graphics Display ...... 117 9.2.1 Primary Planes A, B and C ...... 118 9.2.2 Video Sprite Planes A, B, C, D, E and F...... 118 9.2.3 Cursors A, B and C ...... 118 9.3 Display Pipes ...... 118 9.4 Display Physical Interfaces...... 118 9.4.1 Digital Display Interfaces...... 120 9.5 References ...... 127 9.6 3D Graphics and Video ...... 127 9.7 Features ...... 128 9.7.1 3D Engine Execution Units ...... 128 9.7.2 3D Pipeline ...... 128 9.7.3 Video Engine ...... 129 9.8 VED (Video Encode/Decode) ...... 129 9.8.1 Features ...... 129 9.9 Register Map ...... 130 10 PCI Express 2.0 ...... 131 10.1 Signal Descriptions ...... 131 10.2 Features ...... 132 10.2.1 Root Port Configurations...... 132 10.2.2 Interrupts and Events ...... 133 10.2.3 Power Management ...... 134 10.3 References ...... 134 10.4 Register Map ...... 134 11 MIPI-Camera Serial Interface (CSI) and ISP ...... 135 11.1 Signal Descriptions ...... 135 11.2 Features ...... 137 11.2.1 Imaging Capabilities ...... 137 11.2.2 Simultaneous Acquisition...... 137

Datasheet 5 11.2.3 Primary Camera Still Image Resolution ...... 138 11.2.4 Burst Mode Support ...... 138 11.2.5 Continuous Mode Capture ...... 138 11.2.6 Secondary Camera Still Image Resolution ...... 138 11.2.7 Primary Camera Video Resolution ...... 138 11.2.8 Secondary Camera Video Resolution...... 138 11.2.9 Bit Depth...... 138 11.3 Imaging Subsystem Integration...... 139 11.3.1 CPU Core...... 139 11.3.2 Imaging Signal Processor (ISP)...... 139 11.4 Functional Description ...... 141 11.4.1 Preview ...... 141 11.4.2 Image Capture ...... 141 11.4.3 Video Capture ...... 141 11.4.4 ISP ...... 141 11.4.5 Memory Management Unit (MMU) ...... 142 11.5 MIPI-CSI-2 Receiver...... 142 11.5.1 MIPI-CSI-2 Receiver Features...... 144 11.6 Register Map...... 144 12 SoC Storage ...... 145 12.1 SoC Storage Overview...... 145 12.1.1 Storage Control Cluster (eMMC, SDIO, SD) ...... 145 12.2 Signal Descriptions ...... 145 12.3 Features...... 148 12.3.1 Memory Capacity ...... 148 12.3.2 SDIO/SD Interface Features...... 148 12.3.3 eMMC Interface Features ...... 148 12.3.4 Storage Interfaces ...... 149 12.4 References...... 151 12.5 Register Map...... 151 13 USB Controller Interfaces ...... 152 13.1 SoC Supports ...... 152 13.2 Signal Descriptions ...... 152 13.3 USB 3.0 xHCI (Extensible Host Controller Interface) ...... 154 13.3.1 USB 3.0 Host Features ...... 154 13.3.2 USB HSIC Features ...... 155 13.4 USB 3.0 xDCI (Extensible Device Controller Interface) ...... 155 13.5 References...... 155 13.5.1 Host Controller Specifications ...... 155 13.6 Register Map...... 156 14 Low Power Engine (LPE) for Audio (I2S) ...... 157 14.1 Signal Descriptions ...... 157 14.2 Features...... 157 14.2.1 Audio Capabilities ...... 159 14.3 Clocks ...... 159 14.3.1 Clock Frequencies ...... 159 14.3.2 38.4 MHz Clock for LPE...... 160 14.3.3 Calibrated Ring Osc (50/100 MHz) Clock for LPE ...... 160 14.3.4 Cache and CCM Clocking...... 160 14.4 SSP (I2S) ...... 160 14.4.1 Features...... 161

6 Datasheet 

14.5 Register Map ...... 161 15 Intel® Trusted Execution Engine (Intel® TXE) ...... 162 15.1 Features ...... 162 15.1.1 Security Features ...... 162 15.1.2 TXE Interaction with NFC...... 163 16 Intel® Sensor Hub ...... 164 16.1 Signal Descriptions ...... 164 16.2 Features ...... 164 16.2.1 Hardware ...... 164 17 Serial IO (SIO) Overview...... 166 17.1 SIO - Serial Peripheral Interface (SPI)...... 167 17.1.1 Signal Descriptions ...... 167 17.1.2 Features ...... 167 17.2 SIO - I2C Interface ...... 170 17.2.1 Signal Descriptions ...... 170 17.2.2 NFC I2C Interface Signals ...... 170 17.2.3 Features ...... 171 17.3 NFC I2C ...... 173 17.3.1 References ...... 173 17.4 SIO - High Speed UART...... 174 17.4.1 Signal Descriptions ...... 174 17.4.2 Features ...... 175 17.4.3 Use ...... 176 17.5 SIO - Pulse Width Modulation (PWM)...... 179 17.5.1 Signal Descriptions ...... 179 17.5.2 Features ...... 179 17.6 Register Map ...... 180 18 Platform Controller Unit (PCU) Overview ...... 181 18.1 Features ...... 181 18.2 PCU - Power Management Controller (PMC)...... 182 18.2.1 Signal Descriptions ...... 182 18.2.2 Features ...... 184 18.2.3 References ...... 191 18.3 PCU - Fast Serial Peripheral Interface (SPI)...... 192 18.3.1 Signal Descriptions ...... 192 18.3.2 Features ...... 192 18.4 PCU - Universal Asynchronous Receiver/Transmitter (UART)...... 196 18.4.1 Signal Descriptions ...... 196 18.4.2 Features ...... 196 18.4.3 Use ...... 199 18.4.4 UART Enable/Disable ...... 199 18.4.5 IO Mapped Registers...... 199 18.5 Register Map ...... 200 18.6 PCU - Intel Legacy Block (iLB) Overview ...... 201 18.6.1 Signal Descriptions ...... 201 18.6.2 Features ...... 201 18.6.3 Use ...... 203 18.7 PCU - iLB - Low Pin Count (LPC) Bridge ...... 204 18.7.1 Signal Descriptions ...... 204 18.7.2 Features ...... 205 18.7.3 Usage ...... 209

Datasheet 7 18.7.4 References...... 210 18.8 PCU - iLB - Real Time Clock (RTC)...... 211 18.8.1 Signal Descriptions ...... 211 18.8.2 Features...... 212 18.8.3 Interrupts...... 212 18.8.4 References...... 214 18.8.5 IO Mapped Registers ...... 214 18.8.6 Indexed Registers...... 214 18.9 PCU - iLB - 8254 Timers