The Differences of CD-R/CD-RW Discs and General CD-ROM 1

INTRODUCTION This service manual provides a variety of service compatible computer. It can write as much as 700 information. Mbytes of digital data into CD-R/RW disc, and can It contains the mechanical structure of the CD- read as much as 650 Mbytes of digital data stored R/RW Drive and the electronic circuits in in a CD-ROM, CD-R and CD-RW disc. schematic form. This CD-R/RW Drive was This CD-R/RW Drive can easily meet the manufactured and assembled under our strict upcoming MPC level 3 specification, and its quality control standards and meets or exceeds Enhanced Intelligent Device Electronics (E-IDE) industry specifications and standards. and ATAPI interface allows Plug and play This CD-R/RW drive is an internal drive unit integration in the majority of today’s PCs without designed for use with IBM PC, HP Vectra, or the need of an additional interface card. FEATURES

1. General 1) Enhanced IDE interface. 2) Internal 5.25 inch, halfheight CD-R/RW Drive. 3) 2Mbytes buffer memory. 4) Audio CD like tray loading of a disc without using a caddy. 5) Power loading and power ejecting of a disc. The disc can also be ejected manually. 6) Supports Power saving mode and Sleep mode. 7) Vertical and Horizontal operation. 8) SuperLink Function. 2. Supported disc formats 1) Reads and writes data in each CD-ROM, CD-ROMXA, CD-I FMV, Video CD, and CD-EXTRA 2) Reads data in Photo CD (Single and Multi session). 3) Reads and writes standard CD-DA. 4) Reads and writes CD-R discs conforming to “Orange Book Part 2”. 5) Reads and writes CD-RW discs conforming to “Orange Book Parts 3”. 3. Supported write method 1) Disc at once (DAO), Session at once (SAO), Track at once (TAO), Variable packet, Fixed packet, and Multi-session. 4. Performance 1) Random 100 ms average access time. 2) CD-R Record speed : 8X, 12X, 16X, 22X~40X (PCAV), 48X CAV. 3) CD-RW Record speed : 4X, 10X, 12X, 16X, X24(PCAV). 4) CD-ROM : Max 7,200 KB/s(Max 48x) Sustained Transfer rate. 5) Supports real time error correction and real time layered error correction at each speed. 6) PIO Mode 4, Multi DMA Mode 2, UDMA Mode 2. 7) Multimedia MPC-3 Spec compliant. 8) Support CD-TEXT read/write. 5. Audio 1) Output 16 bit digital data over ATA interface. 2) 8 Times Digital Filter for CD Audio 3) Software Volume Control 4) Equipped with audio line output and headphone jack for audio CD playback. 5) Front panel Volume Control for Headphone Output.

3 LOCATION OF CUSTOMER CONTROLS

Front Panel

Emergency Eject Hole

Disc Tray

Stop/Eject Button

Volume Drive Activity Indicator Control

Headphone Jack

1. Disc tray 4. Volume control This is the tray for the disc. Place the disc on the This is used to adjust the output volume of the ejected disc tray, then lightly push the tray (or headphone jack. It can’t be used to adjust the push the eject button) and the CD will be loaded. output volume for the audio output connectors on NOTE: Don’t pull out or push in the disc tray the rear panel. forcibly. This might cause damage to the loading NOTE : Turn the volume down before turning on section of the drive. the power. Sudden loud noises can damage your hearing. 2. Stop/Eject button This button is pressed to open the CD tray. 5. Headphone jack This button works only when power is supplied to This jack is for connecting headphones or mini- the drive. speakers. If an Audio CD is playing, pressing this button will 6. Drive activity indicator(Read/Write) stop it, and pressing it again will open the tray. Two colored LED is used to indicate the operation 3. Emergency Eject Hole of CD-R/RW Drive. Insert a paper clip here to eject the Disc tray manually or when there is no power.

6 Rear Panel

Analog Audio Output Connector IDE Interface Connector

POWER +12 +5 GND 1 INTERFACE 2 ANALOG 39 DIGITAL AUDIO 40 AUDIO C S M R G L S L A D G

Jumper Connector Power Connector

Digital Audio Output Connector

1. Power Connector 3. Jumper Connector Connects to the power supply (5-and 12-V DC) of This jumper determines whether the drive is the host computer. configured as a master or slave. Changing the NOTE : Be careful to connect with the proper master-slave configuration takes effect after polarity. Connecting the wrong way may damage power-on reset. the system (and is not guaranteed). Usually this 4. Analog Audio Output Connector connector can only be attached one-way. Provides output to a sound card (analog signal). 2. IDE Interface Connector Generally you need this to play a regular audio Connect to the IDE (Integrated Device CD. Electronics) Interface using a 40-pin flat IDE 5. Digital Audio Output Connector cable. Provides output to a sound card (digital signal). NOTE : Do not connect or disconnect the cable when the power is on, as this could cause a short circuit and damage the system. Always turn the power OFF when connecting or disconnecting the cable.

7 TROUBLESHOOTING GUIDE

1. Connect only the power cable

Power check (Malfunction of LED and Tray).

Check the Reset (Pin 170, 122 of Check the input of oscillation (pin Check the connection of 5V, 12V. IC101, pin2 of IC401). 109 of IC401).

Check SCLK, SDATA, XLAT (pin 122, 123, 124 of IC401).

IC 401 33.8688MHz

MCLK 109

MT1516 74 75 ‘ H ’ RF Amp /XRST 2 55 Wobble ALPC SCLK General port use 122 65 SDATA EEPROM access 123 63 IC 101 XLAT 124 62 MT1508MT1518 IC 501 IC 103 DSP Decoder 10 19 20 Encoder AT49F002NAT49F040 ATIP Demodulator 54 32 512KB Write Strategy BD7907FS Flash ROM Write S/H Signal 6Ch Servo DRIVE I / F 31 IC 202 Micro Processor 32 44 51 30 ‘ L ’ 3 2 170 PRST Reset ‘ H ’ / HRST 122

1 3.3 V 3

IC 502 41 44 SDRAM CN 100 12V 5V IC 102

52 Check the Reference voltage (+/- 10%).

Check voltage of VREF(1.4V) Check VC (1.4V) of Drive IC (pin 53 of IC101, pin 27 of IC501). (pin27 of IC501).

Check voltage of 2VREF(2.8V) (pin 52 of IC101).

Check HAVC/PDVC(2.0V) Check FVREF/FPDVC (2.8V) Check FPDO(2.8V) (pin 34 of IC401, pin 13 of CN201). (pin 52 of IC401, pin22 of CN201). (pin 54, 65 of IC401).

CN 201 IC 401

Optical 2.0 V Pick-up PDVC 13 75 VHAVC IC 101 KRS-340B 34 HAVC 2.8 V MT1516 V28 76 52 2VREF 2.8 V RF Amp FPDVC 22 74 VFVREF 1.4 V Wobble V14 76 53 VREF 52 FVREF ALPC General port use 2.8V EEPROM access MT1518 FPDO 19 54 FPDO LD Drive 65 FPDOLP DSP FPDVcc Decoder 20 Encoder ATIP Demodulator IC 501 IC 506 Write Strategy Write S/H Signal 5 V 1.4 V I / F VC 27 1 NJM 3 Micro Processor 2 3414 BD7907FS 6Ch Servo DRIVE

3.3 V 2 2.5 V 3 17 28 76 134 180

IC 503

53 Check the initial operation (Power-on state)

• Check the operating signal of Sled (pin 28, 29 of IC501 : SLIN1, 2). Sled move to inside. • Check the output signal of Sled (pin 34, 35, 36, 37 of IC501). • Check the Spindle signal (pin 24 of IC501 : SPIN). • Check /SLEDIN_SW. (pin 104 of IC401). Spindle motor rotate. • Check FG input (pin 20 of IC101). • Check the Hall signal (pin 1, 2, 3, 4, 5, 6 of IC501).

Laser On. Check the Laser. • Check the control signal of Driver IC(pin 22, 23 of IC501). • Check the power of DRIVE IC and VC. Focus up / Down. Check the operation of Focus

Laser Off / Spindle Stop. Check SCLK, SDATA, XLAT (pin 122, 123, 124 of IC401). 2 times iteration

IC 401

(From pin 1 of CN402) SCLK 122 65 Optical /SLEDIN_SW MT1516 104 SDATA Pick-up ALPC 123 63 General port use XLA T KRS-340B 124 62 Spindle Motor 101 102 IC 101 STEP Motor MT1518 DSP

DRV-MUTE2 DRV-MUTE1 I / F

34 35 36 37 22 23 U Micro 9 B- B+ A- A+ CTL1 CTL2 V Processor 11 SLIN1 28 26 FMO W 18 IC 501 SLIN2 29 27 FMO2 HB 7 BD7907FS SPIN 24 25 DMO HU+ , HU- 6Ch Servo 1 , 2 HV+ , HV- DRIVE FG 21 20 FG 3 , 4 HW+ , HW- 1.4 V 5 , 6 VC 27

54 1. Waveform when Sled moves to inside

SLIN1 When the sled moves to the inner position, /SLEDINSW the sine wave(refer to Fig1) inputs to A+ SLIN1/SLIN2 (the input pins of drive IC). When Pick-Up unit approached to innermost position, the /SLEDINSW signal(CN402 pin 1) Zoom in becomes 0 V. wave The output pins A+ ,A-, B+, B- of the drive IC is PWM waveform and drives the Stepping Motor.

Fig.1

2. Waveform of Spindle rotation The output signal of Hall(HU+, HU-, HV+, HV, HW+, HW-) comes from a Hall sensor of spindle HU+ motor and they were inputted to pin 1, 2, 3, 4, 5, 6 HV+ of drive IC(BD7907FS) via CN402. When spindle HW+ motor rotate, HU+, HW+, HV+ signals are generated in a regular order with 1200 phase delay Zoom in each other.(Refer Fig 2) wave If waveforms of HU+, HU-, HV+, HV-, HW+, HW- different from Fig 2, check the pin 7(HB signal) of Fig.2 drive IC. The HB signal must be about 5V.

Wave of U,V,W assigned to pin 9,11,18 of Drive IC is a PWM waveform and they drive Spindle motor. When spindle motor rotate, U/W/V signals are generated in a regular order with 1200 phase delay Zoom in each other. (Refer Fig 3) wave

If waveforms different from Fig 3, check pin 27(VC), pin 51(VCC), pin22(CTL1), pin23 (CTL2), Fig.3 R514, R512, R510, R511.

3. Waveform of Spindle Kick

When spindle kick, refer to Fig 4. SPIN FG U

Zoom in wave

Fig.4 55 Check Tray operation.

Check /EJECT KEY (pin 11 of IC101).

• Check the control singal of Drive IC Check the output signal of tray Check operating signal of tray (pin 22, 23 of IC501). (pin 49, 50 of IC501). (pin 26 of IC501). • Check the power of DRIVE IC and VC.

Check operation S/W of tray (/OPEN SW:pin 94 of IC401 /LOAD SW : pin 95 of IC401).

Check operating signal of LED (pin Check SCLK, SDATA, XLAT (pin Check the LED. 96, 98 of IC401). 122, 123, 124 of IC401).

LED1 LED102 Q802 96 IC 401 LED2 LED101 Q801 98 MT1516 RF Amp SCLK 122 65 /OPEN_SW General port use SW103 SDATA 2 94 123 63 XLA T DETECTOR /LOAD_SW 124 62 IC 101 -TRAY 1 95 MT1518 101 102 MT1508

DRV-MUTE2 DRV-MUTE1 DSP Decoder FRONT 22 23 Tray Motor TRAY - Encoder 49 CTL1 CTL2 PWMOUT I / F LDIN 26 24 M BD7907FS Micro 6Ch Servo DRIVE Processor TRAY + 1.4 V 50 IC 501 VC 27 SW102

11 EJECT /EJECT_KEY -SW

56 2. Connection of Power and ATAPI cable

Check identification of Drive. CN101(ATAPI) Pin no. Pin name Pin no. Pin name 39 DASP GND 40 Check the connection of ATAPI 37 CS1 CS3 38 cable. 35 DA0 DA2 36 33 DA1 PDIAG 34 31 INTRQ IO16 32 Check the communication between PC and MT1518 (IC101). 29 DMACK GND 30 27 IORDY CSEL 28 25 IOR GND 26 Check SDRAM. 23 IOW GND 24 (IC102) 21 DMARQ GND 22 19 GND KEY 20

Check Flash ROM 17 HD0 HD15 18 (IC103). 15 HD1 HD14 16 13 HD2 HD13 14 11 HD3 HD12 12 9 HD4 HD11 10 7 HD5 HD10 8 5 HD6 HD9 6 3 HD7 HD8 4

33.8688MHz 1 /HRST GND 2

74 75

IC 103 IC 101 MT1508MT1518 AT49F002NAT49F040 Address 512KB Flash ROM Data DSP Decoder I/F cable H Encoder O ATIP Demodulator S Write Strategy T IC 102 Write S/H Signal I / F Address 8MB SDRAM SDRAM Data Micro Processor

57 Check the identification of CD- ROM Disc (insert Disc). In case of Focus Up/Down

• Check the drive signal of FCS-/+ • Check control signal of Drive IC (pin 1, 2 of CN201). Check the operation of Focus. (pin 22, 23 of IC501: CTL1,2). • Check drive input signal of Focus • Check power and VC of DRIVE IC. (pin 53 of IC501 : FCIN).

• Check the input signal of FE (pin 42 of IC101 : FEI). Check signal of A~H (pin 39, 38, 37, • Check the input signal of SBAD 36, 30, 31, 32, 33 of IC401). (pin 38 of IC101).

• Check the drive signal of TRK+/- (pin 3, 4 of CN201). Check the operation of Tracking. • Check the signal of Tracking (pin 52 of IC501 : TKIN). • Check the signal of SLED (pin 28, 29 of IC501 : SLIN1, 2).

Check the input signal of TE (pin 40 of IC101 : TEI).

• Check the input signal of CSI (pin Check the Jump action. 41 of IC401). • Check the input signal of RFZC (pin 60 of IC101 : HRFZC).

Optical FEO Pick-up 42 42 FEI KRS-340B A ~ D SBAD 49 38 SBAD E ~ H TEO IC 401 45 40 TEI IC 101 MT1516 CSI CN 201 43 41 CSI 1 2 3 4 RF Amp General port use RFZC 126 60 HRFZC MT1518 TRK- FCS- FCS+ TRK+ SCLK 122 65 45 46 47 48 DRV-MUTE2 SDATA CTL1 22 101 123 63 DSP DRV-MUTE1 XLA T Decoder IC 501 CTL2 23 102 124 62 Encoder 1.4 V I / F VC 27 Micro Processor BD7907FS TRSO 52 7 6 23 TRO 6Ch Servo TKIN NJM DRIVE 3404 FOSO FCIN 53 1 2 22 FOO

SLI N1 28 26 FMO IC 505 SLI N2 29 27 FMO2

58 4. Operation of Focus Up/Down

FE Waveform of Focus Search refer to Fig 5. SBAD In Focus Search, FE signal and SBAD signal are FCS+ used to Focus Servo On. Therefore, in case of Focusing Fail, check the FE signal and SBAD signal. Zoom in wave

Fig.5 Focus Search Focus Servo On

5. Waveform of Track Following

Waveform of Track Following(Sequential Read) TE refer to Fig 6. EQRF By Sled Servo, SLIN1, SLIN2 (pin 28, 29 of Drive IC) drive the Sled Motor(Stepping Motor) for CE locating the lens on the center axis of Pick-up. SLIN1

Fig.6

6. Waveform of Track Jump

TE Waveform of Track Jump refer to Fig 7. RFZC Center level of TE,CE is 1.4V. CE SLIN1 SLIN1, SLIN2 signal (pin 28, 29 of Drive IC) assume the form of Pulse. And they drive the Sled Motor(Stepping Motor). Zoom in RFZC(RF Ripple Zero Cross) signal is Pulse form wave and it lags behind TE signal 900. Fig.7

7. Waveform of Spindle Servo On

SPIN FG To maintain constant rpm(CAV) or linear velocity(CLV), the drives control spindle motor. U The Fig 8 shows the waveforms when spindle servo is on.

Zoom in wave

Fig.8

59 Check RF and Spindle Check EQRF input signal Check the signal of A~H (pin 39, 38, (Insert CD-ROM Disc). (pin 45 of IC101) 37, 36, 30, 31, 32, 33, of IC401)

Check FG input (pin 20 of IC101).

• Check the control signal of Drive IC Check the operation signal of Spindle (pin 22, 23, of IC501). (pin 24 of IC501). • Check power/VC of DRIVE IC.

Check the identification of CD-R Disc(Insert Blank CD-R). Check SCLK, SDATA, XLAT (pin 122, 123, 124 of IC401).

Check the input signal of ATFG (pin 69 of IC101).

Check the identification of CD-RW Disc (Insert Blank CD-R).

EQRF IC 401 21 45

MT1516 SCLK Optical 122 65 RF Amp Pick-up SDATA 123 63 KRS-340B Wobble IC 101 A ~ D XLA T Spindle 124 62 General port use Motor E ~ H MT1518 ATFG 116 69 STEP Motor DSP 101 102 Decoder DRV-MUTE2 DRV-MUTE1 Encoder I / F

22 23 U ATIP 9 CTL1 CTL2 Demodulator V 11 W 18 SPIN 24 25 DMO IC 501 HB Micro 7 Processor BD7907FS HU+ , HU- 6Ch Servo 1 , 2 FG 21 20 FG HV+ , HV- DRIVE 3 , 4 HW+ , HW- 1.4 V 5 , 6 VC 27

60 Check point of Writing

Check the compatibility between Drive and Tool.

Check whether or not additional Check whether or not Disc is Check Disc state (Fingerprint, writing is allowed. writeable (CD-R/CD-RW). Scratch, Dust...). (Given in the Disc Info of writing tool)

Check Laser 1 (Check EEPROM)

Activate ‘Addition Func.’ window in Test Tool(GGOOM6).

Execute ‘S/N’ (Identify Serial Number).

Execute ‘ALPC Parameters’ Check the communication line (ALPC initial value before ‘Laser Power Setting’) (Identify ALPC Parameters). of EEPROM.

Check whether or not ‘ALPC Execute ‘C. Laser Power Parameters is initial value. setting’ in Test Tool(GGOOM6). IC 101

CS 1 110 EEP-CS IC 401 MT1508MT1518 SCLK IC 203 122 65 SLK 2 108 EEP-CLK SDATA MT1516 123 63 Decoder AT93C86 XLA T Encoder 2KB DI 3 124 62 ALPC EEPROM 107 EEP-SDATA DO 4 Micro EEPROM access Processor

61 Check Laser 2 (No disc).

Execute ‘D. Laser Inspection’ in Test Tool (GGOOM6).

NG OFF LEVEL. Check Reference voltage.

NG VRDC LEVEL FPD. E

Check Read Laser NG E VWDC1 LEVEL FPD. F

NG VWDC2 FPD. Execute ‘E.ALPC Test for AS’ in G Test Tool (GGOOM6) (select ‘VRDC Loop’, and ‘Trigger’).

Check the input of ENBL (pin 33 of CN201 : ‘H’).

• Check the input of RLDON Check the input of VRDC (pin 128 of IC401 : ‘H’). (pin 25 of CN201 : 0.4~0.8V). • Check SCLK, SDATA, XLAT (pin 122, 123, 124 of IC401).

Check the input of FPDO (pin 54, Initial value of FPDO : 2.8V +/- 10%. 65 of IC401 : FPDO~0.1V).

CN 201 IC 401 IC 101

Optical H ENBL 33 5 ENBL MT1518 Pick-up SCLK KRS-340B 122 65 SDATA Decoder 0.4~0.8V 123 63 VRDC 25 63 VRDCO MT1516 XLAT Encoder 124 62 Write Strategy ALPC Write S/H Signal FPDO-0.1V H FPDO 19 54 FPDO RLDON 128 57 LD Micro Drive 65 FPDOLP Processor

62 Inspection of CD-R Recording Laser Inspection of CD-RW writing Laser F G

Execute ‘E. ALPC Test for AS’ in Execute ‘E.ALPC Test for AS’ in Test Tool (GGOOM6) (Select Test Tool(GGOOM6) (Select ‘CD-RW Rec Mode’, and ‘CD-R Rec Mode’, and ‘Trigger’) ‘Trigger’)

Chect input of ENBL (pin 33 of CN201 : ‘H’).

• Check input of VWDC1 • Check input of WLDON (pin 26 of CN201 : 0.4~1.0V). (pin 27 of IC401 : ‘H‘) • Check input of VWDC2 • Check SCLK, SDATA, XLAT (pin 27 of CN201 : 0.1~0.5V). (pin 122, 123, 124 of IC401)

• Check input of WXR (pin 30 of CN201 : Pulse) CD-R Recording Pulse • Check input of ODON (pin 31 of CN201 : Pulse)

WXR CD-RW Recording Pulse

Check input of FPDO (pin 54, 65 of IC401 : Pulse). WXR ODON Initial value of FPDO : 2.8V/-10%) ODON FPDO

FPDO

CN 201

Optical H ENBL 33 5 ENBL IC 401 IC 101 Pick-up SCLK KRS-340B 0.4~1.0V 122 65 VWDC1 26 62 VWDC1O SDATA 123 63 MT1518 0.1~0.5V XLAT MT1516 124 62 VWDC2 27 61 VWDC2O Decoder ALPC Encoder FPDO 19 54 FPDO Write Strategy H Write S/H Signal WLDON 127 58 65 FPDOLP Micro LD Processor Drive WXR 30 13 WXR

ODON 31 15 ODON

63 Check Audio signal (Insert Audio Disc).

Identify playback of Audio Disc Check SCLK, SDATA, XLAT (Play Mode). (pin 122, 123, 124 of IC401).

Check Output signal of AUIO L/R Check Output signal of AUDIO Check Output signal of (pin 51, 54 of CN100). L/R (pin 165, 167 of IC101). /AUD-MUTE (pin 103 of IC401).

Check Output signal of AUDIO Check Input signal of AUDIO L/R Check Input signal of L/R (pin 1, 7 of IC801). (pin 3, 5 of IC801). /AUD-MUTE (pin 3 of IC801).

Output of Headphone

IC 401 IC 101

SCLK 122 65 MT1516 SDATA RF Amp 123 63 XLAT General port use 124 62 SB MT1508MT1518 IC 801 103 DSP Decoder /AUD-MUTE MUTE 3 Encoder I / F BH3544F Micro Processor LOUT AUDIO LOUT LOUT JK101 1 3 Audio 165 LO AMP ROUT ROUT Mute ROUT H-JACK 7 5 Circuit 167 RO

FRONT 51 54

L-CH R-CH CN 100 AUDIO Line Out

64 • How to use Test Tool (GGOOM6) A. Start 1. Install GCE-8481B -> PC Power ON -> Execute Windows. 2. Execute GGOOM6.exe on Windows (GGOOM6.exe & GGOOM6.cfg should be on the same Directory). 3. If you use GCE-8481B, “GGOOM6(Ver x.xx)” will be displayed on the Window Frame. 4. Select I/F Setup on the menu bar. 5. Select ATAPI I/F and then Click OK. 6. Select Target Select on the menu bar. 7. Select Number of Host(#0 or #1) appropriately, then “GCE-8481B” displays on Target Device. 8. Select “GCE-8481B” on Target Device, and then Click OK.

[I/F Setup Menu] [Target Select window]

B. Check ALPC Parameters 1. Select VIEW on the menu bar. 2. Click Addition Func. on VIEW window -> New frame will be displayed. 3. Click ALPC Para tab. [ALPC Parameters] 1) CD-R READ Reference DAC : 60 ~185 2) CD-RW READ Reference DAC : 60 ~185 3) VWDC1 : 200 ~ 296 4) VWDC1 Offset : 30 ~ 175 5) VWDC2 : 499 ~787 6) VWDC2 Offset : -55 ~ 75 4. Close Calibration window.

[Additional Function Menu] [ALPC Parameters Menu] 65 C. Laser Power Setup (VWDC / VWDC 1, 2 re-setup) 1. Remove disc on the tray. 2. Select ALPC/OPC on the menu bar, and then select Laser Power Setup menu. 3. Setup LD Power meter (Frequency :780nm, Measure Range : 0.01mW unit). 4. Click VRDC button on the Laser Power Setup window. Laser beam will be emitted from LD. 5. Measure LD Power with LD Power meter. Type the result in the blank(Read Power box). [Ex] 2.11mW ->211 6. Click VWDC1 button and follow above step 5. But VWDC1 result should be filled in the Write Power box. [Ex] 19.32mW ->1932 7. Click Setup button, and result will be displayed with OK or NG. 8. Close Laser Power Setup window.

[Laser Power Setup window]

[Laser Power Setup Frame] [Laser Power Setup Result]

66 D. Laser Inspection (VRDC/VWDC1, 2 FPD & Level check) 1. Remove disc on the Tray. 2. Select ALPC/OPC on the menu bar and select Laser Inspection menu, then Laser Power Test window will appear. 3. Click Trigger button, then the result will be displayed with OK or NG separately. 4. Close Laser Power Test window.

[Laser Inspection]

[Laser Power Test Frame] [Laser Power Test Result]

67 E. ALPC Test for AS 1. Remove disc on the Tray. 2. Select ALPC/OPC on the menu bar and select ALPC Test for AS menu, then window will appear. 3. Select specific mode of ALPC Test mode and click Trigger button, then LD will be on. 4. Implement test like measuring LD Power. 5. Click Stop button, then LD Off .

* Caution : Laser beam is emitted continuously on the VRDC Loop and CW Power Test. Pulse_Type Laser output like real writing is emitted on the CD-R Rec Mode and CD-RW Rec Mode.

[ALPC Test For AS]

[ALPC Test Mode]

68 Functional Block Diagram Tray Motor

Motor Spindle DMO M

6Ch Servo DRIVE PWM out PWM BD7907FS TRK FCS

KRS-340B Pick-up Optical

TRO FOO SLO STEP Motor Drive

LD IC 501

Drive Mute

VWDC

VRDC

ABCD

EFGH F PD Pulse Writing

EEPROM AT93C86 IC 203 2KB Mechanism S/W Detect Mechanism S/W ERMac s EEPROM acce General port use LED Control

MT1516 IC 401 RF Amp Wobble ALPC s Flash ROM AT49F002N

AT49F040 IC 103 512KB Reset Data, Clock, XLAT FEI,TEI,CSI RRF, EQRF, Write S/H S Servo S/H, Data Address/ FG ignal Micro Processor ATIP Demodulator Write S/H Signal Write S/H

Write Strategy MT1518 IC 101 Encoder Decoder 33.868MHz DSP I / F Circuit Audio

Mute

Audio L,R Address Data cable I/F Reset 3.3 V 2.5 V

SDRAM IC 102 L,R 2MB T S O H

Line Out

12V 5V

71 MAJOR IC INTERNAL BLOCK DIAGRAM AND PIN DESCRIPTION IC401 (MT1516) : CD-R/RW Analog Signal Processor Block Diagram

VDAC0 MPXOUT2 MCLK DVSS2 VDAC1 V14 VHAVC VREF V28 ATFG WLDON RLDON WFPDSH RFPDSH VRDCO VWDC1O VWDC2O DVDD1 DVDD2 MPXOUT1 AGC1C AGC2C AGC3C ATFM WBLCLK DVSS1 VFVREF

AVSS9 VRDCN AVDD9 P/B AVSS8 Voltage VRDC Detect AVDD8 Ref & DAC ATIP RREF AVSS7 x1 VWDC1N AVDD7 MPX2B AVSS6 VDAC0 VWDC1 VREFMPX MPX2 AVDD6 MPX1 APC WREF1 MPX2B AVSS5 ADO BCO WRFSH ADBCO AVDD5 CE 10-Bit FPDOLP RREF AVSS4 MPX2 FE ADC FPDO AVDD4 WREF1 TE FVREF AVSS3 VRDCO SBAD AVDD3 VWDC1O SBADOLP FPDOX VWDC2O FPDOX AVSS2 VWDC1B AUX1 MPX2 RFRP AVDD2 VRDCB AUX2 AVSS1 AUX3 DRCLP AUX3 AVDD1 AUX2 SPPO SUBGND AUX1 MPPO RFZC1 RFZC1 RFZC XLAT TELP TZC DIG. TZC MPX1 SHBC SDATA DRCMO REG. HSH RFZC1VC SCLK DRCSO GSH SHPC TRCLOSE FVREF TROPEN FSH EQRF RRFX SERVO ATFMX MPX1 RECDIN TRAYOUT# RRFXLP ESH FPDO & SBADLP TRAYIN# DSH ROPCO Detection LED1 CSH DEFECT TEIN RFAGCC LED2 BSH SBAD LIMIT# VCON ASH TE FR CE ENDM General FE MUTE I/O DRCO2 SB DEVSEL EEP_SDATA GAINUP GAINUP EEP_SCLK FEO ADO DRCO BCO

MPPO SPPO RRFX EEP_CS VCON SBADO ADBCO INH ENBL HAVC HAVC HAVC ASPREQ EQRF S/H GIO1~GIO7 IND IND IND & ING INC RRF ROPC INC Data INC MATRIX INF INB INB INB

RRF WRF INE Slicer INA INA INA XRST EQRF

INA INB INC IND

H11T DEFM EQRF HAVC SLPFP SLPFN XDEFM OSTCC RFSUM ROPCC ROPCO EQBIAS RRFXLP WBLSH RFAGCC WRFSUM SERVSH RRF/WRF

RECDIN/RRFSUM

36 • Pin Assignment

Pin Symbol Type Description Numbers RF Signals & S/H Control Pulses 36 INA Analog Input Input of Main Beam Signal (A) 37 INB Analog Input Input of Main Beam Signal (B) 38 INC Analog Input Input of Main Beam Signal (C) 39 IND Analog Input Input of Main Beam Signal (D) 30 INE Analog Input Input of Side Beam Signal (E) 31 INF Analog Input Input of Side Beam Signal (F) 32 ING Analog Input Input of Side Beam Signal (G) 33 INH Analog Input Input of Side Beam Signal (H) 34 HAVC Analog Input Reference Voltage Input of Main and Side Beams (2.0V) Digital Input (TTL), 120 SERVSH S/H Control Pulse of Main and Side Beam Signals SMT Digital Input (TTL), 118 WBLSH S/H Control Pulse of Wobble Signal SMT Focus/Tracking Error & Servo Control Signals 40 DRCO Analog Output Output of Differential Radial Contrast (DRC) Signal 41 DRCO2 Analog Input Re-Input of Differential Radial Contrast (DRC) Signal 42 FE Analog Output Output of Focusing Error Signal 45 TE Analog Output Output of Tracking Error Signal 43 CE Analog Output Output of Center Error Signal 49 SBAD Analog Output Output of SBAD Signal 44 TEIN Analog Input Input of Out-of-Track Detection Circuit 50 SBADLP Analog Input Input of SBAD Signal after LPF for DEFECT Detection 46 SHPC Analog Output External Capacitor Connection for Peak Hold of RFRP Signal 47 RFZC1VC Analog Output Reference Voltage for RFRP Peak/Bottom Hold 48 SHBC Analog Output External Capacitor Connection for Bottom Hold of RFRP Signal Digital Output 126 RFZC Output of RF Zero Crossing Binary Signal (TTL), 4 mA Driving EQRF (RF Equalizer Filter and Data Slicer) Circuit 19 RFSUM Analog Input Input of RF Summing Signal from PUH to EQRF Block 11 EQBIAS Analog Output External Bias Connection for Circuits in EQRF Block External Capacitor Connection for Offset Cancellation Circuit of 13 OSTCC Analog Output Equalizer Output 16 RFAGCC Analog Output External Capacitor Connection for RF AGC in EQRF Block 21 RFOUT Analog Output Output of RF EFM Signal after Equalizer Filter Digital Output 4 DEFM Binary Output of EFM Signal after Slicing (Positive) (TTL), 6 mA Driving Digital Output 3 XDEFM Binary Output of EFM Signal after Slicing (Negative) (TTL), 6 mA Driving 8 SLPFP Analog Input Input ( ) of Auto Slicing Level 9 SLPFN Analog Input Input of Auto Slicing Level RRF & ROPC (Running OPC) Related Signals RECDIN/ (1). Input of RF Signal for Recorded Area Detection 22 Analog Input RRFSUM (2). Input of Read RF Summing Signal from PUH to RRF Block 70 RRFXLP Analog Output Low Pass Output of RRF Signal

37 Pin Symbol Type Description Numbers (1). Output of Read RF (RRF) Signal 24 RRF/WRF Analog Output (2). Output of Write RF (WRF) Signal 26 WRFSUM Analog Input Input of Write RF (WRF) Summing Signal to ROPC Block 27 ROPCO Analog Output Output of Amplified B-Level of Write RF Signal 28 ROPCC Analog Input Vin(-) of Amplifier for Sampled B-Level of WRF Signal Digital Input (TTL), 125 H11T S/H Control Pulse of WRF Signal SMT ATIP (Absolute Time In Pre-groove) 81 AGC1C Analog Output External Capacitor Connection for AGC1 in ATIP Block 82 AGC2C Analog Output External Capacitor Connection for AGC2 in ATIP Block 83 AGC3C Analog Output External Capacitor Connection for AGC3 in ATIP Block 85 ATFM Analog Output Output of Analog Wobble Signal Digital Output 116 ATFG Digital Output of Wobble Signal after Slicing (TTL), 4mA Driving Digital Input (TTL), 114 WBLCLK External Clock Input for Wobble BPF (SCF) SMT APC (Auto Power Control for Laser) 54 FPDO Analog Input Input of Laser Monitor Voltage 65 FPDOLP Analog Input Input of Laser Monitor Voltage after Low Pass Filtering 52 FVREF Analog Input Reference Voltage of APC Loops 128 RLDON Digital Input (TTL) Laser Diode Control for Read Mode 127 WLDON Digital Input (TTL) Laser Diode Control for Write Mode Digital Input (TTL), 112 RFPDSH S/H Control Pulse for Read APC Mode SMT Digital Input (TTL), 111 WFPDSH S/H Control Pulse for Write APC Mode SMT (1). Input of Power Setting Voltage for Read APC; (2). Output of 55 RREF Analog I/O Read APC Reference Voltage Generated by Built -in DAC 59 VRDCN Analog Input Vin(-) of Midcourse Amplifier for Read APC Loop 58 VRDC Analog Output Midcourse Output of Laser Diode Controlling in Read Mode 63 VRDCO Analog Output Output Voltage of Laser Diode Controlling in Read APC (1). Input of Power Setting Voltage for Write APC 1; (2). Output of 53 WREF1 Analog I/O Write APC Reference Voltage Generated by Built-in DAC 57 VWDC1N Analog Input Vin(-) of Midcourse Amplifier for Write APC 1 56 VWDC1 Analog Output Midcourse Output of Laser Diode Controlling in Write APC 62 VWDC1O Analog Output Output Voltage of Laser Diode Controlling in Write APC 61 VWDC2O Analog Output Output Voltage 2 of Laser Diode Controlling in Write APC Reference Voltages & DACs 75 VHAVC Analog Output Output of Voltage Reference (2.0V) 78 VREF Analog Output Output of Voltage Reference (2.0V) 77 V14 Analog Output Output of Voltage Reference (1.4V) 76 V28 Analog Output Output of Voltage Reference (2.8V) 74 VFVREF Analog Output Output of Voltage Reference (2.5V~3.0V) 69 VDAC0 Analog I/O Output of General Purposed 8-Bit DAC (0V ~ 2.0V) 51 VDAC1 Analog Output Output of General Purposed 10-Bit DAC (0V ~ 4V) MPXOUT (Multiplexer Circuit for Various Signals) and Testing Interface 68 AUX1 Analog Input Auxiliary Input 1 for Signal Monitoring 67 AUX2 Analog Input Auxiliary Input 2 for Signal Monitoring 66 AUX3 Analog Input Auxiliary Input 3 for Signal Monitoring

38 Pin Symbol Type Description Numbers 71 MPXOUT1 Analog Output Multiplexer Output 1 for Signal Monitoring 72 MPXOUT2 Analog Output Multiplexer Output 2 for Signal Monitoring Serial Interface & Other Digital Control Signals Digital Output ASP request signal output to MT1508 to send control signals via 1 ASPREQ (TTL), 4 mA Driving serial interface. Digital Input (TTL), 122 SCLK Clock Input for Register Setting SMT Digital I/O (TTL), 123 SDATA Data Input/Output for Register Setting 4 mA Driving Digital Input (TTL), 124 XLAT Latch Input for Register Setting SMT Digital Input (TTL), 2 XRST Digital Input for Register Resetting SMT Digital Input (TTL), 109 MCLK Digital Input of Main Clock SMT Digital Input (TTL), Tr n Input, A Logical Low Indicates the Tray is IN. Feedback 95 TRAYIN# 50K Pull-Up, SMT Flag from Tray Connector. Digital Input (TTL), Tr Input. A Logical Low Indicates the Tray is OUT. 94 TRAYOUT# 50K Pull-Up, SMT Feedback Flag from Tray Connector. Digital Input (TTL), 99 LIMIT# Sledge Inner Limit Input, Active Low. 50K Pull-Up, SMT Digital Input (TTL), Device Select. Cleared to ZERO Indicates the Driver is Master 106 DEVSEL 50K Pull-Up, SMT Device. Set to ONE Indicates the Driver is Slave Device. Digital Input (TTL), 100 FR Spindle Motor Reverse Detection Input. SMT Digital Output 93 TROPEN Tray Open Output. Initial Output. (TTL), 4 mA Driving Digital Output 92 TRCLOSE Tray (TTL), 4 mA Driving Digital Output 96 LED1 LED Control Output. Initial Output. (TTL), 4 mA Driving Digital Output 98 LED2 LED Control Output. Initial Output. (TTL), 4 mA Driving Digital Output Enable/Disable Disk Motor. A Logical High Enables Disk Motor. 101 ENDM (TTL), 4 mA Driving Initial Output. Digital Output 102 MUTE Servo Control Power Driver Enable Output. Initial Output. (TTL), 4 mA Driving Digital Output 103 SB Spindle Motor Short Break Control Output. Initial Output. (TTL), 4 mA Driving Digital Output 110 EEP_CS EEPROM Chip Select Output. (TTL), 4 mA Driving Digital Output 108 EEP_SCLK EEPROM Transmit Clock Output. (TTL), 4 mA Driving Digital I/O (TTL), 107 EEP_SDATA 50K Pull-Down, EEPROM Transmit Data Input/Output. 4mA Driving Digital Output 5 ENBL (TTL), Laser Diode Enable Signal Output 4 mA Driving

39 Digital I/O (TTL), 50K Pull-Up, (1). General I/O 1 for Mass Production Use (Initial Input Mode) 88 GIO1 4 mA Driving (2). Output of Internal Digital Signal ( VWDC1 )

Pin Symbol Type Description Numbers Digital I/O (TTL), (1). General I/O 2 for Mass Production Use (Initial Input Mode) 89 GIO2 50K Pull-Up, (2). Output of Defect Detection Signal ( DEFEC ) 4 mA Driving Digital I/O (TTL), (1). General I/O 3 for Mass Production Use (Initial Input Mode) 90 GIO3 50K Pull-Down, (2). Output of the State of Seeking ON Control Setting 4 mA Driving Digital I/O (TTL), (1). General I/O 4 for Mass Production Use (Initial Input Mode) 91 GIO4 50K Pull-Down, (2). Output of Internal Digital Signal ( ) 4 mA Driving Digital I/O (TTL), (1). General I/O 5 for Mass Production Use (Initial Input Mode) 104 GIO5 50K Pull-Up, (2). Output of Out-of-Track Detection Signal 4 mA Driving Digital I/O (TTL), (1). General I/O 6 for Mass Production Use (Initial Input Mode) 105 GIO6 50K Pull-Up, (2). Output of Out-of-Track Detection Signal ( XTOR ) 4 mA Driving Digital I/O (TTL), (1). General I/O 7 for Mass Production Use (Initial Input Mode) 119 GIO7 50K Pull-Up, (2). Output of Recorded Area Detection Signal ( RECD1 4 mA Driving Power Supplies 86 , 87 SUBGND Analog Ground Ground Pin for Substrate Bias of Internal Digital Circuitry 29 AVDD1 Analog Power Power Pin for Internal Analog Circuitry (5V) 35 AVSS1 Analog Ground Ground Pin for Internal Analog Circuitry 60 AVDD2 Analog Power Power Pin for Internal Analog Circuitry (5V) 64 AVSS2 Analog Ground Ground Pin for Internal Analog Circuitry 80 AVDD3 Analog Power Power Pin for Internal Analog Circuitry (5V) 84 AVSS3 Analog Ground Ground Pin for Internal Analog Circuitry 20 AVDD4 Analog Power Power Pin for Internal Analog Circuitry (5V) 18 AVSS4 Analog Ground Ground Pin for Internal Analog Circuitry 23 AVDD5 Analog Power Power Pin for Internal Analog Circuitry (5V) 25 AVSS5 Analog Ground Ground Pin for Internal Analog Circuitry 79 AVDD6 Analog Power Power Pin for Internal Analog Circuitry (5V) 73 AVSS6 Analog Ground Ground Pin for Internal Analog Circuitry 10 AVDD7 Analog Power Power Pin for Internal Analog Circuitry (5V) 6 , 7 AVSS7 Analog Ground Ground Pin for Internal Analog Circuitry 14 AVDD8 Analog Power Power Pin for Internal Analog Circuitry (5V) 12 AVSS8 Analog Ground Ground Pin for Internal Analog Circuitry 15 AVDD9 Analog Power Power Pin for Internal Analog Circuitry (5V) 17 AVSS9 Analog Ground Ground Pin for Internal Analog Circuitry 121 DVDD1 Digital Power Power Pin for Internal Digital Circuitry (5V) 117 DVSS1 Digital Ground Ground Pin for Internal Digital Circuitry 113 DVDD2 Digital Power Power Pin for Digital I/O Pads Buffer Circuitry (5V) 115 DVSS2 Digital Ground Ground Pin for Digital I/O Pads Buffer Circuitry

40 IC101(MT1518) : CD-R/RW Encoder/Decoder/Write Strategy / DSP /Interface /Micro Processor Block Diagram

RFDTSLVP RFDTSLVN SCOP SCON RFIN RFIP ATFG WBLCLK EFMPLLVDD EFMVCOIN EFMLPFGND EFMPLLVSS WSR_WXR WSR_CFREQ FLAG_OUT1 FLAG_OUT2 WSR_ODON RLDON WLDON WFPDSH RFPDSH WBLSH SERVSH H11T

TEST

Data Wobble EFMPLL Wobble Signal Spindle (efmclk Write Strategy Reset Slicer Interface Logic PRST# Control synthesizer) Interface Logic DPLLVDD Logic IREF LPFIN Sync. EFM LPFIP FM Demodulator DPLLVSS Data Protection Demodulator System XTALO PLL Subcode & Bi-Phase data LPFON Demodulator Clock XTALI LPFOP Demodulator Generator IPLLVDD LPION Servo IPLLVSS LPIOP status ATIP Sync Protection & PWM detection CRC check & DMO DAC CLV/CAV circuit system Target MSF Search clock ENDM Controller FG

VPVDD Varipitch VCOCIN CLV Clock CIRC CIRC Encoder VPVSS Generator C3 C3 Error Corrector DMU EFM modulatoin Decoder Encoder Subcode generator RFZC/ TEZILP TEI TEZC HRFZC Circuit RD[15:0] SRVADCVDD CDROM FEI Servo Buffer RA[11:0] TEI Sync r Servo DSP Memory RAS# CSI Detection SBAD ADC Controller CAS# SRVADCVSS Descrambler CASH#/RWEH# RWE# ROE# CLK CKE FOO 3K DQM BA(1:0) TRO PDM & SRAM FMO CDROM Host ATAPI Audio/Effect FMO2 PWM DAC High-speed Data Packet PWMOUT OPC/ROPC Interface Computation Audio Playback FIFO FIFO PDMVDD Unit PWM2VREF Key/LED EJECT#/STOP# PWMVREF 8032 Interface PLAY#/PAUSE# PDMVSS ASP Laser Power Time to Audio Host Interface Micro-controller Control Control Digital Audio DAC Digital Out Interface Logic Converter

LO RO VSS

SLCK ADGO UALE SDEN URST DIOR# XRST# IORDY INTRQ SDATA DASP# HRST# DIOW# HA[2:0] UA[7:0] PDIAG# CS1FX# CS3FX# DMARQ DAC DACVD HD[15:0] UPSEN# DMACK# IOCS16#

DACVREF

FLAG_OUT1 UA16/UP1_0 UA17/UP1_1 UA18/UP1_2 UP3_7/URD# UP3_6/UWR#

UP3_2/UNIT0# UP3_3/UINT1# UP2_7~UP2_0 UP3_5~UP3_4 UP3_1~UP3_0

UP0[7:0]/UAD[7:0]

41 • Pin Description

Pin Numbers Symbol Type Description Data PLL Interface (9) 29 DPLLVDD Analog Power(3.3V) Power supply for data PLL and related analog circuitry. 30 LPIOP Analog Output Data PLL VCO DAC positive output. 31 LPION Analog Output Data PLL VCO DAC negative output. 32 LPFOP Analog Output The positive output of loop filter amplifier. 33 LPFIN Analog Input The negative input terminal of loop filter amplifier. 34 LPFIP Analog Input The positive input terminal of loop filter amplifier. 35 LPFON Analog Output The negative output of loop filter amplifier. 36 IREF Analog Input Current reference input. It generates reference current for data PLL. Connect an external 15K resistor between this pin and PLLVSS. 37 DPLLVSS Ground Ground pin for data PLL and related analog circuitry. Signal Amplifier Interface (13) 38 SBAD Analog Input Sub-beam add input (E+F+G+H). 39 TEZILP Analog Input Tracking error zero crossing low pass input. 40 TEI Analog Input Tracki ng error input. 41 CSI Analog Input Central servo input. 42 FEI Analog Input Focus error input. 43 SRVADCVSS Ground Ground pin for servo ADC circuitry. 44 RFIN Analog Input RF negative signal input. 45 RFIP Analog Input RF positive signal input. 46 SRVADCVDD Analog Power(3.3V) Power supply for servo ADC circuitry. 47 RFDTSLVN Analog Input Negative input for analog slicer. 48 SCOP Analog Output Positive low pass filter output for analog slicer. 49 SCON Analog Output Negative low pass filter output for analog slicer. 50 RFDTSLVP Analog Input Positive input for analog slicer. Turbo 8032 Interface (37) 171 UP3_7 3.3V LVTTL I/O, Programmable bi-directional I/O. / URD# Slew rate, SMT, Alternate function : RD#. Data write signal. 4mA driving, 75K pull-up 172 UP3_6 3.3V LVTTL I/O, Programmable bi-directional I/O. / UWR# Slew rate, SMT, Alternate function : WR#. Data write signal. 4mA driving, 75K pull-up 173 UP3_3 3.3V LVTTL I/O, Programmable bi-directional I/O. / UINT1# Slew rate, Alternate function : INT1#. External interrupt 1. 4mA driving, 75K pull-up 174 UP3_2 3.3V LVTTL I/O, Programmable bi-directional I/O. / UINT0# Slew rate, Alternate function : INT0#. External interrupt 0. 4mA driving, 75K pull-up

42 175 UP3_1 3.3V LVTTL I/O, Programmable bi-directional I/O. / UTXD Slew rate, Alternate function : TXD. Serial transmit data. 4mA driving, 75K pull-up 176 UP3_0 3.3V LVTTL I/O, Programmable bi-directional I/O. / URXD Slew rate, Alternate function : RXD. Serial receive data. 4mA driving, 75K pull-up 177 UALE 3.3V LVTTL I/O, Address latch enable output during internal µP mode, active Slew rate, SMT, high. And as address latch enable input during ICE mode. 4mA driving, 75K pull-up 178 UPSEN# 3.3V LVTTL I/O, Programmable store enable output during internal µP mode, Slew rate, SMT, active low. UPSEN# enables the external ROM output port. 4mA driving, And as input during ICE mode. 75K pull-up 189,188,186, UA[7:0] 3.3V LVTTL output, Lower address bus output for external device. 185,184,182, Slew rate, Alternate function : Internal monitored signal output. 181,179 2mA, 4mA, 6mA 8mA PDR, 75K pull-up 190,192,193, UP2_[7:0] 3.3V LVTTL I/O, Programmable bi-directional I/O. 194,195,197, / UA[15:8] Slew rate, Alternate function : A[15:8]. Upper address bus input/output. 198,199 2mA, 4mA, 6mA 8mA PDR, 75K pull-up 191 FLASH_WE# 3.3V LVTTL output, Flash memory write enable signal output, low active. 4mA driving 200 UP1_1 3.3V LVTTL I/O, Programmable bi-directional I/O. /UA17 Slew rate, Alternate function : A17. Address bit 17 output. 2mA, 4mA, 6mA 8mA PDR, 75K pull-up 201 UP1_0 3.3V LVTTL I/O, Programmable bi-directional I/O. / UA16 Slew rate, Alternate function : A16. Address bit 16 output. 2mA, 4mA, 6mA 8mA PDR, 75K pull-up 202 FLASH_CS# 3.3V LVTTL I/O, Flash memory chip select signal output, low active. 4mA driving, 75K pull-up 203,204,3, UP0_[7:0] 3.3V LVTTL I/O, Programmable bi-directional I/O. 4,5,6,8,9 / UAD[7:0] Slew rate, Alternate function : AD[7:0]. Lower address/data bus output for 2mA, 4mA, 6mA external device. 8mA PDR 205 UP1_2 3.3V LVTTL I/O, Programmable bi-directional I/O. /UA18 Slew rate, Alternate function : UA18. Address bit 18 output. 4mA driving, 75K pull-up Motor and Actuator Driver Interface (11) 20 FG 3.3V LVTTL Input, Motor Hall sensor input. SMT, 75K pull-up

43 22 FOO Analog Output Focus servo output. PDM output of focus servo compensator. 23 TRO Analog Output Tracking servo output. PDM output of tracking servo compensator. 24 PWMOUT Analog Output General purpose PWM output. 25 DMO Analog Output Disk motor control output. PWM output. 26 FMO Analog Output Feed motor control. PWM output. 27 FMO2 Analog Output Feed motor 2 control. PWM output. 51 PDMVDD Analog Power(3.3V) Power supply for PDM circuitry. 52 2VREF Analog input 2.90 V reference voltage input. 53 VREF Analog input 1.45 V reference voltage input. 54 PDMVSS Ground Ground for PDM circuitry. Mega Interface (2) 11 EJECT# 3.3V LVTTL I/O, Eject/stop key input, active low. 75K pull-up, 4mA driving 12 PLAY# 3.3V LVTTL I/O, Play/pause key input, active low. 75K pull-up, 4mA driving NC (3) 155 NC 156 NC 157 NC IPLL VCO Interface (2)

104 IPLLVDD Analog power(3.3V) Power supply for IPLL circuitry. 105 IPLLVSS Ground Ground pin for IPLL circuitry. EFMPLL VCO Interface (4) 207 EFMPLLVDD Analog power(3.3V) Power supply for EFMPLL circuitry. 208 EFMVCOCIN Analog input EFMPLL VCO input. For external loop filter connection. 1 EFMLPFGND Analog input EFMPLL LPF ground input. 2 EFMPLLVSS Ground Ground pin for EFMPLL circuitry. Audio Output Interface (1) 163 ADGO 3.3V LVTTL I/O, Digital Audio Output. The signal is the Digital Audio Output Slew rate, which supplies the IEC-958 digital audio data. 75K pull-up, Alternate function : HRST_ extension selection input during 4mA, 8mA driving power-on stage (PRST falling edge). A logical low input indicates raw HRST_ is used. A logical high input indicates extended HRST_ is used. Internal Audio DAC Interface (5) 164 AUDACVSS Ground Ground pin for internal audio DAC circuitry. 165 LO Analog Output Left channel of audio. 166 DACVREF Analog Output Reference voltage for external audio filter circuit. 167 RO Analog Output Right channel of audio. 168 AUDACVDD Analog Power(3.3V) Power supply for internal audio DAC circuitry.

44 Write Strategy Interface (5) 13 WXR 3.3V LVTTL output, Laser diode write power control output. (Write/Read mode SW Slew rate, signal) 2mA, 4mA, 6mA, 8mA, 10mA, 12mA, 14mA, 16mA PDR 15 ODON 3.3V LVTTL output, Laser diode over drive control output. (Over drive control SW Slew rate, signal) 2mA, 4mA, 6mA, 8mA, 10mA, 12mA, 14mA, 16mA PDR 16 OUT1/OSCEN 3.3V LVTTL output, Internal flag output. Include : “WSR_OSCEN” signal Slew rate, 8mA driving 18 OUT2/CMOD 3.3V LVTTL output, Internal flag output. Include : “WSR_CMOD” signal Slew rate, 8mA driving 19 CFREQ 3.3V LVTTL output, Frequency selection signal output. Slew rate, 8mA driving Write strategy & ASP transmission Interface (16) 55 XRST# 3.3V LVTTL output, RF reset output. Active low. 4mA driving 56 ASPREQ 3.3V LVTTL Input, ASP request signal input from MT1516 to get RECD1, XTOR, SMT, 75K pull-down DEFECT automatically. 57 RLDON 3.3V LVTTL I/O, Read laser diode on control signal. 75K pull-down, Alternate function : ICE mode selection input during power-on 4mA driving stage (PRST falling edge). A logical low input indicates internal µP is used. A logical high input indicates external µP is connected. 58 WLDON 3.3V LVTTL output, Write laser diode on control signal. 4mA driving 60 HRFZC 3.3V LVTTL Input, High frequency RF ripple zero crossing input. SMT, 75K pull-up 61 H11T 3.3V LVTTL output, EFM 11T indicator for ROPC sampling. Slew rate, 8mA driving 62 XLAT 3.3V LVTTL output, Latch signal output for RF register setting. 4mA driving 63 XDATA 3.3V LVTTL I/O, Data signal output for RF register setting. Slew rate, 75K pull-down, 4mA driving 65 XCLK 3.3V LVTTL output, Carrier clock signal output for RF register setting. Slew rate, 8mA driving 66 SERVSH 3.3V LVTTL output, Sample pulse for servo signal (main beam/ side beam) 2mA, 4mA, 6mA, 8mA, 10mA, 12mA, 14mA, 16mA PDR

45 68 WBLSH 3.3V LVTTL output, Sample pulse for wobble signal. 2mA, 4mA, 6mA, 8mA, 10mA, 12mA, 14mA, 16mA PDR 69 ATFG 3.3V LVTTL Input, Digital wobble signal (22.05 ± 1 K Hz) input SMT 70 WBLCLK 3.3V LVTTL output, Wobble processing clock (432.18K Hz) output for MT1516. Slew rate, 4mA driving 71 RFPDSH 3.3V LVTTL output, Sample pulse control signal for RF read APC. 2mA, 4mA, 6mA, 8mA, 10mA, 12mA, 14mA, 16mA PDR 72 WFPDSH 3.3V LVTTL output, Sample pulse control signal for RF write APC. Slew rate, 2mA, 4mA, 6mA, 8mA, 10mA, 12mA, 14mA, 16mA PDR 206 WRSTOP 3.3V LVTTL Input, Write procedure stop control input. SMT, 75K pull-down Miscellaneous Interface (4) 169 TEST_MODE 3.3V LVTTL input, Test mode, active high 75K pull-down 170 PRST 3.3V LVTTL Input, Power on reset input, high active.

SMT 74 XTALO Output X`tal output. 75 XTALI Input X`tal input. The working frequency is 33.8688 MHz. Host Interface (31) 122 HRST# 3.3V LVTTL Input, Host reset input. The active-low input is referred to as hardware SMT, 75K pull-up reset and is used to reset this chip. 142,140,138, HD15 ~ HD0 3.3V LVTTL I/O, Host Data bus. This is the 8-bit or 16-bit bi-directional data bus 135,132,130, Slew rate, SMT, to the host. The lower 8 bits, HD0–HD7, are used for 8-bit data 127,124,123, 4mA, 6mA, 8mA, transfers. Normally, data transfers are 16-bit wide. 125,128,131, 12mA PDR, Note : All pins except HD7 (no any pull) may be selectively 133,136,139, 40K(15K) PPU, 40K pull-up or pull-down with 40K resistant.(HD6~HD0 is 15K) 141 (15K)PPD 144 DMARQ 3.3V LVTTL output, DMA request. This signal is used for DMA data transfers 12mA driving between host and device and it shall be asserted by the MT1518 when it is ready to transfer data to or from the host. The direction of data transfer is controlled by DIOR# and DIOW#. 145 DIOW# 3.3V LVTTL Input, Device I/O write. Stop ultra DMA burst. SMT, 40K pull-up For Device I/O Write, this signal is the strobe signal asserted by the host to write device register or the data port. For Stop Ultra DMA, this signal shall be negated by the host before data is transferred in an Ultra DMA burst and is asserted by host during an Ultra DMA burst to signal the termination of Ultra DMA burst.

46 68 WBLSH 3.3V LVTTL output, Sample pulse for wobble signal. 2mA, 4mA, 6mA, 8mA, 10mA, 12mA, 14mA, 16mA PDR 69 ATFG 3.3V LVTTL Input, Digital wobble signal (22.05 ± 1 K Hz) input SMT 70 WBLCLK 3.3V LVTTL output, Wobble processing clock (432.18K Hz) output for MT1516. Slew rate, 4mA driving 71 RFPDSH 3.3V LVTTL output, Sample pulse control signal for RF read APC. 2mA, 4mA, 6mA, 8mA, 10mA, 12mA, 14mA, 16mA PDR 72 WFPDSH 3.3V LVTTL output, Sample pulse control signal for RF write APC. Slew rate, 2mA, 4mA, 6mA, 8mA, 10mA, 12mA, 14mA, 16mA PDR 206 WRSTOP 3.3V LVTTL Input, Write procedure stop control input. SMT, 75K pull-down Miscellaneous Interface (4) 169 TEST_MODE 3.3V LVTTL input, Test mode, active high 75K pull-down 170 PRST 3.3V LVTTL Input, Power on reset input, high active. SMT 74 XTALO Output X`tal output. 75 XTALI Input X`tal input. The working frequency is 33.8688 MHz. Host Interface (31) 122 HRST# 3.3V LVTTL Input, Host reset input. The active-low input is referred to as hardware SMT, 75K pull-up reset and is used to reset this chip. 142,140,138, HD15 ~ HD0 3.3V LVTTL I/O, Host Data bus. This is the 8-bit or 16-bit bi-directional data bus 135,132,130, Slew rate, SMT, to the host. The lower 8 bits, HD0–HD7, are used for 8-bit data 127,124,123, 4mA, 6mA, 8mA, transfers. Normally, data transfers are 16-bit wide. 125,128,131, 12mA PDR, Note : All pins except HD7 (no any pull) may be selectively 133,136,139, 40K(15K) PPU, 40K pull-up or pull-down with 40K resistant.(HD6~HD0 is 15K) 141 (15K)PPD 144 DMARQ 3.3V LVTTL output, DMA request. This signal is used for DMA data transfers 12mA driving between host and device and it shall be asserted by the MT1518 when it is ready to transfer data to or from the host. The direction of data transfer is controlled by DIOR# and DIOW#. 145 DIOW# 3.3V LVTTL Input, Device I/O write. Stop ultra DMA burst. SMT, 40K pull-up For Device I/O Write, this signal is the strobe signal asserted by the host to write device register or the data port. For Stop Ultra DMA, this signal shall be negated by the host before data is transferred in an Ultra DMA burst and is asserted by host during an Ultra DMA burst to signal the termination of Ultra DMA burst.

47 84 BA0 3.3V LVTTL Output, SDRAM bank address 0 signal. For SDRAM application only. Slew rate, 2mA, 4mA, 6mA, 8mA, 10mA, 12mA, 14mA, 16mA PDR, 75K PPD 85 ROE# 3.3V LVTTL Output, RAM Output Enable, low active. Slew rate, For SDRAM application, this pin is “Chip Select” signal output 2mA, 4mA, 6mA, connected to “CS#” pin of SDRAM. When two 2-bank SDRAM 8mA, 10mA, 12mA, are used, this pin musts connect to “CS#” pin of first SDRAM. 14mA, 16mA PDR 87 RAS# 3.3V LVTTL Output, RAM Row Address Strobe. This active-low output is the Row Slew rate, Address Strobe signal to the RAM. 2mA, 4mA, 6mA, For SDRAM application, this pin is “row address strobe” signal 8mA, 10mA, 12mA, output connected to SDRAM. 14mA, 16mA PDR 88 CAS# 3.3V LVTTL Output, Column Address Strobe Low / Column Address Strobe. When Slew rate, two column address strobe pins are used, this pin is the Column 2mA, 4mA, 6mA, Address Strobe Low signal for accessing the lower bytes of a 8mA, 10mA, 12mA, two-CAS# 16-bit RAM. When an 8-bit DRAM is used, this pin 14mA, 16mA PDR shall be connected to CAS# of the DRAM. For SDRAM application, this pin is “column address strobe” signal output connected to SDRAM. 89 RWE# 3.3V LVTTL Output, RAM Write Enable/RAM Write Enable Low. RAM write enable Slew rate, signal, low active. When two write enable pins are used, it is the 2mA, 4mA, 6mA, Write Enable Low signal for writing the lower bytes of a 8mA, 10mA, 12mA, two-WE_ 16-bit RAM. 14mA, 16mA PDR For SDRAM application, this pin is dedicated for “Write Enable” usage. 90 DQML 3.3V LVTTL Output, SDRAM low-byte data output mask control signal, high active. Slew rate, For SDRAM application only. 2mA, 4mA, 6mA, 8mA, 10mA, 12mA, 14mA, 16mA PDR, 75K PPD 116 CASH#/ 3.3V LVTTL Output, Column Address Strobe High / RAM Write Enable High. When a RWEH# Slew rate, 16-bit DRAM is used, this active-low pin functions as Column 2mA, 4mA, 6mA, address Strobe High for accessing the upper bytes of a 8mA, 10mA, 12mA, two-CAS# RAM, or as Write Enable High for writing the upper 14mA, 16mA PDR bytes of a two-WE# RAM. For SDRAM application, this pin is changed to DQMH and is used to as SDRAM high-byte data mask control signal, high active. 117 CLK 3.3V LVTTL Output, SDRAM clock output. For SDRAM application only. Slew rate, 2mA, 4mA, 6mA, 8mA, 10mA, 12mA, 14mA, 16mA PDR, 75K PPD

48 118 CKE 3.3V LVTTL Output, SDRAM clock enable signal output. For SDRAM application Slew rate, only. 2mA, 4mA, 6mA, 8mA, 10mA, 12mA, 14mA, 16mA PDR, 75K PPD 106,107,108, RD15 ~ RD0 3.3V LVTTL I/O, RAM Data bus. These pins are the bi-directional upper Buffer 109,110,112, Slew rate, RAM data bus to the external buffer memory. 113,115,92, 2mA, 4mA, 6mA, 93,94,95,96, 8mA, 10mA, 12mA, 97,98,99 14mA, 16mA PDR, 75K PPU, 75K PPD 119,81,120, RA11~ RA0 3.3V LVTTL Output, RAM address bus. 121,103,102. Slew rate, 101,100,77,78, 2mA, 4mA, 6mA, 79,80 8mA, 10mA, 12mA, 14mA, 16mA PDR Power Supply (27) 91,143,196 (3) DVDD33 Power (3.3V) Power supply for input pad buffer circuitry. 17,76,134,180 DVDD25 Power (2.5V) Power supply for internal digital circuitry and general pad buffer (4) circuitry. 14,73,137,183 DVSS Ground Ground pin for internal digital circuitry and input pad buffer (4) circuitry. 7,67,86,111, DVDD33 Power (3.3V) Power supply for output pad buffer circuitry.

129,150 (6) 10,64,83,114, DVSS Ground Ground pin for output pad buffer circuitry. 126,147,187 (7) 28 AVDD25 Power (2.5V) Power supply for dedicated digital circuitry in fully block. 21 AVSS Ground Ground pin for dedicated digital circuitry in fully block. 59 AVDD33 Power (3.3V) Power supply for dedicated digital circuitry in fully block.

49 IC501 (BD7907FS): Spindle Motor and 5ch Actuator Driver

Block Diagram

HU+ 154 DVCC FG HU- 2 53 FCIN DETECT REVERCE HV+ 3 52 TKIN

HV- 4 51 VCC

HW+ 5 SHIFT LEVEL 50 LDO+ 47K

HW- 6 49 LDO- BIAS HALL 47K HB 7 SHIFT LEVEL 48 TKO+ 94K

PGND1 8 94K 47 TKO-

U 9 SHIFT LEVEL 46 FCO+

SPVM1 10 45 FCO-

V 11 44 AVM

GND 12 43 GND OUT PWM MATRIX 3-phase GND 13 42 GND TSD FF GND 14 41 GND COMP Current

GND 15 OSC COMP Polarity 40 GND

GND 16 39 GND

PGND2 17 LIMIT Current 38 AGND

W 18 LOGIC PRE 37 SLO1+ FF

SPVM2 19 36 SLO1-

SPRNF 20 LOGIC PRE 35 SLO2+ FF FG FG 21 OSC 34 SLO2- CONTROL BRAKE CTL1 22 STBY/ 33 SLGND 15K CTL2 23

15K 32 SLRNF2

SPIN 24 31 SLRNF1 LIMIT LIMIT 47K 94K DGND 25 47K

47K 30 SLVDD 47K LDIN 26 29 SLIN2

VC 27 47K 28 SLIN1

50 • Pin Description

Terminal Symbol Description Terminal Symbol Description 1 HU+ Hall amp.U positive input 54 DVCC PWM block control power supply 2 HU- Hall amp.U negative input 53 FCIN Focus driver input 3 HV+ Hall amp.V positive input 52 TKIN Tracking driver input 4 HV- Hall amp.V negative input 51 VCC BTL pre and Loading power supply 5 HW+ Hall amp.W positive input 50 LDO+ Loading driver positive output 6 HW- Hall amp.W negative input 49 LDO- Loading driver negative output 7 HB Hall bias 48 TKO+ Tracking driver positive output 8 PGND1 Spindle driver power ground 1 47 TKO- Tracking driver negative output 9 U Spindle driver output U 46 FCO+ Focus driver positive output 10 SPVM1 Spindle driver power supply 1 45 FCO- Focus driver negative output 11 V Spindle drive output V 44 AVM Actuator driver block power supply 12 GND GND 43 GND GND 13 GND GND 42 GND GND 14 GND GND 41 GND GND 15 GND GND 40 GND GND 16 GND GND 39 GND GND 17 PGND2 Spindle driver power ground 2 38 AGND Ground 18 W Spindle driver output W 37 SLO1+ Sled driver 1 positive output 19 SPVM2 Spindle driver power supply 2 36 SLO1- Sled driver 1 negative output 20 SPRNF Spindle driver current sense 35 SLO2+ Sled driver 2 positive output 21 FG Frequency generator output 34 SLO2- Sled driver 2 negative output 22 CTL1 Driver logic control input 1 33 SLGND Sled driver power ground 23 CTL2 Driver logic control input 2 32 SLRNF2 Sled driver 2 current sense 24 SPIN Spindle driver input 31 SLRNF1 Sled driver 1 current sense 25 DGND PWM block pre-ground 30 SLVDD Sled driver Power MOS pre-supply 26 LDIN Loading driver input 29 SLIN2 Sled driver 2 input 27 VC Reference voltage input 28 SLIN1 Sled driver 1 input

* Positive/negative of the output terminals are determined in reference to those of the input terminals.

• Functional description

O : ON, X : OFF

CTL1(22pin) CTL2(23pin) Spindle Sled Focus Tracking Loading LLXXXXX¥L HLXXXXO¥M _HOOOOX

CTL1(22pin) CTL2(23pin) SPIN > VC SPIN < VC L H Forward-rotation mode Reverse-rotation braking mode ¥N ¥O H H Forward-rotation mode Short-circuit braking mode

¥LStanby mode ¥M Drivers muting ¥N Reverse-rotation mode (spindle) ¥O Short-circuit braking mode (spindle)

51 DISASSEMBLY 1. CABINET and CIRCUIT BOARD 1-3. Cabinet and Main Circuit Board A. Remove the Cabinet in the direction of arrow (4). DISASSEMBLY (See Fig. 1-3) 1-1. Bottom Chassis B. Release 2 hooks (a) and remove the CD Tray A. Release 4 screws (A) and remove the Bottom Chassis drawing forward. in the direction of arrow (1). (See Fig.1-1) C. Remove the Main Circuit Board in the direction of arrow (5). D. At this time, be careful not to damage the 4 connectors, are positioned at right side, of the Main Circuit Board.

Cabinet

(1) Hooks (a) (4)

(A) Bottom Chassis (5) (A) (A) (A) Fig. 1-1 Main Circuit Board 1-2. Front Bezel Assy A. Insert and press a rod in the Emergency Eject Fig. 1-3 Hole and then the CD Tray will open in the direction of arrow (2). B. Remove the Tray Door in the direction of arrow 2. MECHANISM ASSY DISASSEMBLY (3) by pushing the stoppers forward. 2-1. Pick-up Unit C. Release 3 stoppers and remove the Front Bezel Assy. A. Release screws (B). B. Separate the Pick-up Unit in the direction of arrow (6). Tray Door (B) (B)

(3)

Stoppers Pick-up Unit (6)

(2) CD Tray

Front Bezel Assy

Mechanism Assy Emergency Eject Hole Fig. 1-2 Fig. 2-1 8 2-2. Pick-up A. Release 2 screws (C) and remove the Pick-up.

Pick-up Unit

Pick-up

Fig. 2-2

9 GLOSSARY

ATIP Absolute Time In Pre-groove.With an additional modulation of the “Wobble”,the “Groove” contains a time code information Wobble The pre-groove in the Disc is not a perfect spiral but is wobbled with ; - a typical amplitude of 30ns - a spatial period of 54 -64µm (Pre-) groove The guidance track in which clocking and time code information is stored by means of an FM modulated wobble CW Continuous Wave. The laser light output is at a constant level DOW Direct Over-Write. The action in which new information is recorded over previously recorded information in CD-RW disc. Overwrite The action in which new information is recorded over previously recorded information Land Land is characterized in the following way: When radial signals are concerned,land is defined as the area between the groove When HF signal are concerned,land is defined as the area between the marks(pits) in tangential direction Hybrid Disc A Multisession disc of which the first Session is mastered. On a hybrid disc, recorded and mastered information may co-exist Mastered Information Information,stored as pits on the disc during the manufacturing process of the disc (when making the “master”) OPC Optimum Power Control. Procedure is determined optimum recording power according to CD-R/RW Media in recording start step. ROPC Running OPC. The purpose is to continuously adjust the writing power to the optimum power that is required When the optimum power may change because of changed conditions of disc and change in operating temperature, Jitter The 1ø value of the time variation between leading and trailing edges of a specific (Mark) pit or land as measured by Time Interval Analysis Deviation The difference between a fixed value of Pit length and Land length TOC Table Of Contents : in the Lead-in Area the subcode Q-channel contains information about the Track on the disc Packet Writing A method of writing data on a CD in small increments. Two kinds of packets can be written : Fixed-length and Variable-length Write Strategy The shape of the HF write signal used to modulate the power of the laser. The Write Strategy must be used for recordings necessary for disc measurements Information Area Wobble, ATIP, Disc Identification, Write Power, Speed Range OPC Parameters, etc are recorded in the Information area of CD-RW Disc Finalization The action in which (partially) unrecorded or logically erased tracks are finished and the Lead-in and/or Lead-out areas are recorded or overwritten with the appropriate TOC subcode Logical Erase A method to remove information from a disc area by overwriting it with an EFM signal containing mode 0 subco A logically erased area is equivalent to an unrecorded Physical Erase The action in which previously recorded information is erased by overwriting with a CW laser output. After a Physical Erase action ,the erased area on the CD-RW disc is in the unrecorded state again. Session An area on the disc consisting of a Lead-in area ,a Program area,a Lead-out area. Multi session A session that contains or can contain more than one session composed Lead-in and Lead-out

16 The differences of CD-R/CD-RW discs and General CD-ROM 1. Recording Layer Recordable CD has a wobbled pre-groove on the surface of disc for laser beam to follow track.

Track pitch(p) CD-ROMRead-only (READ-ONLY Disc DISC) a=30nm A

Iw O 1.6um Radial Direction a

3~11T

0.4~0.5 um Radial Error Signal Land Groove

CD-R and CD-RW Disc a

Average center (Pit)Groove

Land Actual center

The Groove wobble

2. Disc Specification

ITEM CD-ROM CD-R CD-RW Standard Yellow Book Orange Book II Orange Book III Record Not available Write once Re-Writable

Tracking Signal I11/Itop > 0.6 > 0.6 0.55 > M11> 0.70 (HF Modulation) Read Laser Power(mW) < 0.5 mW < 0.7 mW < 1.0 mW Jitter < 35 nsec < 35 nsec < 35 nsec

Reflectivity (Rtop) 70 % 65 % 15 % ~ 25 %

Remark) Write Laser Power(mW) 14-65 mW 6-45 mW

17 3. Disc Materials 1) CD-ROM disc • It is composed of Silver _ colored aluminum plate and Reflective layer. • Groove (Pit) of aluminum plate make a track. • Laser wavelength : 780 nm, Laser Power (Read): 0.5mW • Signal is detected by the difference of reflective beam intensity between “pit” and “Land” on the disc.

Label Printing Protective Layer

Reflective Layer

Substrate (Polycarbonate)

Pit Laser Beam 2) CD-R disc • It is so-called WORM (Write Once Read Many) CD. • It is composed of polycarbonate layer, Organic dye layer, Reflective layer, and Protective layer.Gold/Silver Reflective layer is used to enhance the reflectivity • According to the kinds of Organic dye layer, it is divided by Green CD, Gold CD, Blue CD. • Laser Wavelength : 780 nm, Laser Power (read) : 0.7 mW • Recording Power : 8x(14~20mW), 12x(15~30mW), 16x(25~35mW), 48x(50~65mW) • When some part of dye layer is exposed to laser heat, it’s color changs black.Therefore, writing and reading is enabled by the difference of reflectivity between changed part and unchanged part. • Polycarbonate layer has Pre_Groove which make a Track.

Pigment Reflective Layer Color Phtalocyanine Gold/Silver Yellow/White Cyanine Gold/Silver Dark Green/Bright Green Azo Gold/Silver Dark Blue

Label Printing Protective Layer Reflective Layer Organic Dye Layer

Substrate (Polycarbonate)

Laser Beam Groove

18 3) CD-RW Disc

Label Printing Protective Layer Dielectric Layer(TL) Recording Layer Dielectric Layer(UL)

Substrate (Polycarbonate)

Laser Beam Groove

• It is composed of polycarbonate layer, alloy(silver, arsenic) layer, aluminum reflectivity layer, protective layer. • An crystalized alloy layer is transformed into noncrystalized by the laser heat. Therefore, writing and reading is enabled by the difference of reflectivity. • It is possible to overwrite about 1000 times. • Laser Wavelength : 780 nm, Laser Power (Read) : 1.0mW • Recording Power : Erase (4~18mW), Write (6~45mW) • When disc rewriting, new data is overwritten previously recorded data. • Polycarbonate layer has a Pre-Groove which make a track.

4. Reading process of Optical Disc

Lens H D θ

Beam Spot Focusing Numerical aperture: NA=nsinθ, Lens n: Refractive index Focus depth : H = λ/NA laser spot diameter : D = λ/NA2 Laser Spot at Constant Read Intensity Previously Recorded Marks

Groove Land Mirror

Reflected Light Signal I11 IG IL I0

I3 Itop Laser Spot Position (Time)

19 5. Writing Process of CD-R Disc

Incident (Write) Laser Power (Read) (Read)

Laser Spot a b c d e f g Position (Time)

Laser b Spot Below "ORP"– Mark Too Short Reflected At Optimum Record Power ("ORP") c Light Signal Above "ORP" – Mark Too Long d

Recorded g Mark Time

Reflected Light Signal

Laser Spot a b c d e f g Position (Time)

6. Writing process of CD-RW Disc

Write Power Crystal phase Amorphous Melting/ quenching Erase Power

Heating/ Read Power gradual cooling Erased state Recorded state (higher reflectivity) (lower reflectivity) Groove

Crystal Amorphous

20 7. Organization of the PCA, PMA and Lead-in Area 1) Layout of CD-ROM disc

Disc Center Diameter 120 mm

Diameter 46 mm

Diameter 15 mm

Center hole Clamping and Label Area Information Area

Read Only Disc

Lead-in Area Program Area Lead-out Area

2) Layout of CD-R/RW disc Disc Center Diameter 120 mm

Diameter 45 mm

Diameter 15 mm

Center hole Clamping and Label Area Information Area

Unrecorded Disc PCA PMA Lead-in Area Program Area Lead-out Area

Test Area : for performing OPC procedures. Count Area : to find the usable area immediately in T.A Test Area Count Area Tsl : start time of the Lead-in Area, as encoded in ATIP in out PMA : Program Memory Area

Tsl-00:35:65 Tsl-00:15:05 Tsl-00:13:25 Tsl 99:59:74 00:00:00

21 8. Function of PCA and PMA area 1) PCA (Power Calibration Area)

• PCA area is used to determine the correct Laser Power for a disc. – Method 1 : PCA area is divided by a track. – Method 2 : The previous Calibration value is referred to. – Method 3 : ROPC is used to determine Laser Power value automatically in data writing. • CD-R Disc can write maximum 99 Tracks but CD-RW Disc can write unlimited tracks because it has a rewritable function. 2) PMA (Program Memory Area)

• It has a track information (track No, track Start/End time) of every track before writing completed. – PMA area has the last written point and the next writable point of a disc. – In case of CD to CD copy, some writer may not write PMA area. * When Disc is Finalized, PMA information is transferred to the Lead_In area so that general Driver can read it.

* Because PCA and PMA area exist before Lead-In area, General CD Player or CD-ROM Drive can’t read these areas.

9. OPC and ROPC 1) OPC (Optimum Power Control) • This is the first step of writing process, because CD writer has its own laser power value and media have different writing characteristics, – This is determined by the Writing characteristic, speed, temperature, and humidity. – Laser wavelength is determined by the environmental temperature (775~795nm) and Optical Laser Power is determined by the test and retry. • Asymmetry and optimum writing Power – EFM signal Asymmetry is determined by the writing power. Therefore, Optical Power which has the same value to the preset power value can be estimated by measuring HF signal Asymmetry on the PCA area. • Measurement of Asymmetry * Parameter setting (Beta) : Using AC coupled HF signal before equalization Beta = (A1+A2)/(A1-A2)

0 HF Signal

A2 P = Po P >> Po Time P << Po Time Time

22 2) ROPC (Running Optimum Power Control) • Variable primary factor of Optimum Power – Change of Power sensitivity on the Disc. (limited to 0.05 *Po) – Wavelength shift of the laser diode due to the operating temperature change. – Change of the Spot aberration due to the Disc skew, Substrate thickness, Defocus. – Change of Disc or Optics conditions due to the long term OPC Incident recording pulse ==> It is necessary to adjust continuously to obtain the Optimum Power. Sampled timing B • Principle of Running OPC – To meet the factors mentioned above, a horizontal direction movement of a curve is uesd. – Beta = f(B-level) = constant on the Recorded Disc – Procedure of ROPC a. Reference B-level is determined during OPC Procedure. b. During Recording, B-level value is controlled to have a close Reflected recording pulse Reference B-level value. c. Normalization of B-level is used to eliminate the effect of reflectivity fluctuation. ==> The reflected B-level value is normalized by the disc reflectivity itself.

Sample Disc Reflectivity Sampled at timing B (Read power) Level B 11T normalized to recording power

Level B with Pwo

Sample B-level (Write Power) Pwo decided by OPC Recording Power

10. Writing Process of DISC

CD-R/RW Media Program Area

Write Strategy PMA Area Determination ROPC

PCA Test Area Lead-In Area OPC

PCA Count Area Lead-out Area

23 11. Recording capacity of CD-R/RW (74min Recording media) • (2048 Byte / Sector ) x ( 75 Sector / Second ) x ( 60 Second / Minute) x 74 Minute = 681,984,000 Bytes = 682 Mbytes • But the actual recording capacity is about 650 Mbytes. (according to the ISO 9660 standard, approximately 30 Mbytes are used to make directory structure and volume names.)

12. Super Link

Super(SUPpressed Error Recording) link method is a new technology to link the interrupted recording by buffer under run. When drive’s buffer will be under, the drive will stop recording and store the stop position. When drive’s buffer receive data from HOST again, the drive will seek to the stop position of last recording and continue writing. In the read procedure, the drive can not find any error in the linking area, the data or audio will be regenerated perfectly.

13. Optimum record speed

To prevent record fail or readability problem of recorded disc, the drive should decide optimum recording speed during the recording for the media.

Writing Speed 22 to 48X CAV(9540 RPM) 48X 40X 32X Normal Case 24X Speed Down Case 16X

48 74 Time[min]

1) All media do not support 48x recording by media quality. Even though a CD-R can be recorded by 48x, there is a possibility to occur fail during recording, especially in high speed writing. 2) So during the recording, Drive checks the Atip and Servo errors, and Drive thinks the current recording status is unstable, then decreases the recording speed for getting stable record. 3) Drive changes the write pulse and power for low speed CLV recording and continuously checks Atip and Servo errors during recording.

24 14. Full/Partial CAV & Zone CLV Recording Comparison

Data transfer rate 48X CAV 40X CLV

40X PCLV 32X 24X 22x 20x Spindle Mode Change 16X CLV Speed change

RPM Time Time 48x CAV 9540 9020 40x PCAV

0 Time 0 Time * Full/Partial CAV * Zone CLV

Full/Partial CAV Zone CLV

1. Reduce Recording time. 1. Increase a stability of Recording. Advantage ( no loss time for speed change ) ( 4 CLV zone : 16, 24, 32, 40x ) 2. Easy to Spindle RPM control 2. High Recording quality compare to P-CAV.

1. It is difficult to control servo 1. Recording time is longer than partial CAV. stability of CAV recording. 2. It needs to control the spindle in speed Disadvantage 2. It has a difficulty in getting change area. the high Recording quality relative to Zone CLV.

25 INTERNAL STRUCTURE OF THE PICK-UP 1. KRS-340B Circuit Diagram

2 Axis Actuator OP output terminal 1 FCS + 2 FCS - 3 TRK + C1 4 TRK - 1 14 Vcc GND 5 LIM 2 13 H G 6 G 3 12 A IC1 D 7 D 4 11 B CXA2660N C 8 C 5 E 10 F 9 E 6 9 Vc RRF 10 RRF 7 8 VLIM WRF 11 WRF 12 PDGND C3 C2 13 PDVC 14 F 15 B 16 A 17 H 18 PDVCC IC2 19 FPDO 1 10 20 FPDVCC 2 9 GND GND 21 FPDGND 3 8 GND GND FPDVC 4 7 22 Vc Vcc 5 6 23 LDVCC OUT Bin L1 R1 24 LDVCC C4 C5 R3 R2 25 VRDC VR1 26 VWDC1 C6 C7 27 VWDC2 28 LDGND 29 LDGND 1 24 VOUT PDIN 30 WE1 2 23 VREF VCC 31 WE2 3 22 GND VCC LD 4 21 32 OSCEN IINR IOUT 5 20 IIN2 IC3 IOUT 33 ENBL 6 EL6215CU 19 VR2 IIN3 GND 34 MODAMP R4 7 18 RFREQ GND 8 17 GND RAMP 9 16 GND ENABLE 10 15 WEN3 OSCEN 11 14 C8 WEN2 VCC 12 13 GND GND

C11 C10 C9 R5 R6 R7

26 2. Signal detection of the P/U

Infrared Iaser

Pick-Up module Focusing

Photo Diode Tracking

1) Focus Error Signal ==> (A+C)-(B+D) This signal is generated in RF IC (IC401 : MT1516) and controls the pick-up’s up and down to focus on Disc.

2) Tracking Error Signal (DPP Method) ==> {(A+D)-(B+C)}- k x {(F+H)-(E+G)} This signal is generated in RF IC (IC401 : MT1516) and controls the pick-up’s left and right shift to find to track on Disc.

3) RF Signal ==> (A+B+C+D) This signal is converted to DATA signal in DSP IC (IC101 : MT1518).

Track Center

Tp/2 Sub1 F,E

Main D,C A,B

Sub2 H,G

k[(F+H) - (E+G)] Offset (A+D) - (B+C)

TE (A+D) - (B+C) - k[(F+H) - (E+G)]

27 DESCRIPTION OF CIRCUIT 1. ALPC (Automatic Laser Power Control) Circuit 1-1. Block Diagram

IC 401 ( MT1516 )

RLDON CN 201 128 57

VRDCO S/H & RFPDSH IC 101

VRDC VRDC - VRDCG & 112 71 25 63 DAC + Level Shift Optical & Gain Pick-up KRS-340B RDAC MT1518 FVREF 22 52 Write FPDO Strategy 19 54 Write 65 FPDOLP WDAC1 S/H Signal & x1/x2

VWDC1O Micro VWDC1 + VWDC1 WFPDSH Processor

26 62 DAC S/H & LD - & Gain VWDC1G & 111 72 Drive Level Shift WLDON VWDC2O 127 58 VWDC2 WDAC2 27 61 & Amplifier

1-2. ALPC(Automatic Laser Power Control) Circuit Operation

ALPC function in CD-R/RW analog front-end is for constant power level control purpose. Based on the accurate power sensor(FMD) in PU, APC feedback loop maintains constant power level against laser diode¡ﬂs temperature variation.

There are two power control loops in MT1516, which are used with different combination for different applications. Generally, the first APC loop is used for read-power control. The 2nd APC loop is used for write(erase) power control for CD-R(CD-RW) disc.

Owing to the small signal level in read-power control mode, the first APC loop amplifies (x5/x10/x15/20x) the FMD signal(FPDO) to enhance the accuracy of read power control. The built-in 8-bit DAC(RDAC) is used to set the read power level. Moreover, the 2nd APC loop is used for high power control. The built-in 10-bit DAC(WDAC1) is used to set the wanted power level. And the register VWDC1G is employed to adjust the gain of FMD signal.

The following potentiometers(VRDCDAC, VWDC1DAC, and WDAC2) and amplifiers(VRDCDAG, VWDC1DAG and WDAC2G) are used to set the wanted levels of the output pins VRDCO, VWDC1O, and VWDC2O. Moreover, the input signal FPDO after low-pass filtering & amplification(x1 or x2) will send the MPXOUT2 for monitoring.

28 2. Focus Circuit 2-1. Block Diagram

-((E+F+G+H)) HAVC LS LPF G 49 SBAD to 0.8V IC401 101 MUTE2 A,B,C,D MT1516 102 MUTE1 HAVC E,F,G,H LS LPF G 42 to FEO -{(A+C)-(B+D)} V14 Disc Optical Motor unit Pick-up KRS-340B

FRO FEI Focusing 22 DAC ADC 42 Compensator

IC101 38 FCS- FCS+ MT1518 SBAD

C562 R560 R149 FCS+ FCIN FRO 46 53

FCS- IC501 45 VC IC505 R566 27 1.4V C188 BD7907 CTL1 22 MUTE2 1.4V CTL2 23 MUTE1

2-2. Focus Servo

The aim of Focus Servo is to maintain the distance between object lens of P/U and disc surface, so that the detected RF signal(A, B, C, D, E, F, G, H) can be maximized.

Focus Error Signal(FE) generates from focus error detection block in RF IC(MT1516) using Astigmatism Method. Focus Gain and path can be changed at the RF IC(MT1516) according to the disc, and the resulting output FE(MT1516 42pin) is input to DSP IC(MT1518 42pin). The SBAD Signal(MT1516 49pin) is from the sum of Side Beam(E, F, G, H), represents Beam Strength and input to DSP IC(MT1518 38pin). The Focus Search operation is using FE, SBAD Signal, therefore check FE, SBAD signals when Focusing is failed.

The role of DSP IC(MT1518) is Focus Digital Controller. The operation path is as follows; FE Signal is input to DSP IC(MT1518 42pin), and after A/D Conversion, Digital Equalizer Block and D/A Conversion in MT1518, the output signal FRO(MT1518 22pin) is input to Drive IC(BD7907 53pin). The drive output signal FCS+/FCS- generated according FCIN(BD7907 53pin), and drives focus actuator in the P/U unit.

29 3. Tracking & Sled Circuit 3-1-1. Block Diagram (Tracking Following)

IC401 101 MUTE2 MPPO MT1516 102 MUTE1 (A+D)-(B+C) A,B,C,D HAVC E,F,G,H L L SPPO LS P G P 45 to F F TEO K*{(F+H)-(E+G)} V14 Disc Optical Motor unit Pick-up KRS-340B

TRO TEI Tracking 23 DAC ADC 40 Compensator

FMO TRK- TRK+ 26 Sled IC101 PWM 27 Compensator MT1518 A+ FMO2 A-

B+

B- SLED MOTOR Unit

C561 R561 R148 TRKIN TRO TRK+ 46 52

TRK- 45 IC501 IC505 R567 C187 CTL1 SLO1+ BD7907 22 MUTE2 A+ 46 CTL2 1.4V SL01- 23 MUTE1 A- 45 C156 C154 SLO2+ SLIN1 R148 B+ 46 28 FMO

SLO2- SLIN2 R148 B- 45 29 FMO2 27 VC 1.4V

30 3-1-2. Block Diagram (Seek)

IC401 101 MUTE2 MPPO MT1516 102 MUTE1 (A+D)-(B+C) A,B,C,D HAVC E,F,G,H L L SPPO - LS P G P 45 to TEO + F F K*{(F+H)-(E+G)} V14 TEO Disc Optical Motor unit Pick-up KRS-340B (A+D)-(B+C) - + K*{(F+H)-(E+G)} DRCO 40 TRK- TRK+ HAVC L C480 LS RFZC 41 P G + to F 126 RFZC A+ DRCO2 V14 -

A- Vref

B+ 46 RF 47 HAVC B- RP L LS SL MPPO G P 43 48 to SLED MOTOR V F Unit V14 R456

CSI

C489

C142 TEZILP 23 IC101 MT1518 R141 TEI Track Counter TEO 26 and Timer HRFZCI RFZC 27

M A Short D TRO Tracking CSI U D Seek A 102 Compensator CSI 27 X C Algorithm C

FMO Loog P Sled 26 Seek W Compensator Algorithm M 27 FMO2

31 3-2-1. Tracking Servo

The aim of tracking servo is to make laser beam trace the data track on disc.

Tracking Error(TE) Signal is generated from tracking error detected block in MT1516 using DPP(Differential Push-Pull) Method. DPP Method uses not only main beam(A, B, C, D) but also side beam(E, F, G, H) for correcting DC offset generated in Push-Pull Method.

The remaining procedure of TE signal processing in MT1518 is similar to Focus Servo. The role of DSP IC(MT1518) is Tracking Digital Controller. TE Signal is input to DSP IC(MT1518 40pin), and after A/D Conversion, Digital Equalizer Block and D/A Conversion in MT1518, the output signal TRO(MT1518 22pin) is input to Drive IC(BD7907 23pin).

The drive output signal TRK+/TRK- generated according TKIN(BD7907 52pin), and drives tracking actuator in the P/U unit.

3-2-2. Sled Servo

The working distance of tracking actuator is too short to cover whole disc radius. Sled Servo make P/U move by little and little so that the laser beam keep tracing the data track on disc continuously when tracking actuator reaches the working limit.

TE Signal is input to DSP IC(MT1518 40pin), and after A/D Conversion, Digital Tracking Equalizer Block, Digital Sled Compensator Block and PWM Conversion in MT1518, the output signal FMO, FMO2(MT1518 26,27pin) is input to Drive IC(BD7907 28,29pin) after Low-Pass filtering. The PWM output signal A+, A-, B+, B- generated according to SLIN1, SLIN2(BD7907 28,29pin), and drives the sled motor.

32 4. Spindle Circuit 4-1-1. Block Diagram (EFMCLV Servo)

IC401 101 MUTE2 MT1516 102 MUTE1 RFSUM RFOUT 19 G EQRF G 21 -{(A+C)-(B+D)} Disc Optical Offset OSTCC Motor unit Pick-up Adj. 13 KRS-340B C430 C410

1.4V IC101 PCK4M Data 45 MT1518 Data RFIP PLL Slicer 44 C153 RFIN

SPIN DMO C141 P M CLV FD PCK4M 25 W U + R146 M X CLV PD VCK4M

Motor Kick REG

SPIN U 9 IC501 24 SPIN V 11 VC BD7907 27 1.4V W 18 CTL1 22 MUTE2 C507 HV+ 3 CTL2 23 MUTE1 C506 HV- 4 1 HU+ C508 HW+ 5 2 HU-

HW- 6 21 FG FG

4-1-2. EFM CLV Servo : 4x, 8x

When drive read PRESS CD at the speed of 4x, 8x, the spindle motor is controlled using EFM CLV Spindle Servo.

The equalized RFOUT Signal(MT1516 21pin) is generated using RFSUM signal from P/U, and input to DSP IC (MT1518 45pin) as RFIP. The spindle controller in MT1518 uses RFOUT signal as linear velocity feedback, therefore the EFM CLV servo doesn¡ﬂt work well if RFOUT signal is abnormal. The spindle controller PWM output signal DMO (MT1518 25pin) input to SPIN in Drive IC(BD7907 24pin) after Low-Pass Filtering. The PWM output signal U, V, W signal(BD7907 9, 11, 18) drives Spindle Motor using Hall Sensor Output signal (HU+, HU-, HV+, HV-, HW+, HW-) and SPIN.

33 4-2-1. Block Diagram (FGCAV Servo)

Optical Pick-up KRS-340B Disc Motor unit X101 33.8688MHz 1.4V IC101 VCK4M XTALO 74 MT1518 Control Clock XTALI Generator 75 C153 PCK4M DMO SPIN P M CAV FD 20 25 W U + R146 M X CAV PD VCK4M R543

Motor Kick REG 3.3V

SPIN U 9 IC501 24 SPIN V 11 VC BD7907 27 1.4V W 18 CTL1 22 MUTE2 C507 HV+ 3 CTL2 23 MUTE1 C506 HV- 4 1 HU+ C508 HW+ 5 2 HU-

HW- 6 21 FG FG

4-2-2. FG CAV Servo

1) CD 15x CAV : Eccentric CD-R/RW, Video CD, CD-DA 2) CD 32x CAV : (CD-RW) 3) CD 40x CAV : CD-R, CD-RW 4) CD 48x CAV : CD-ROM

When drive read PRESS CD, Closed Session CD-R/RW, the spindle motor is controlled using FG CAV Spindle Servo. FG signal(BD7907 21pin) input to FGIN in DSP IC(MT1518 20pin). The spindle controller in DSP IC uses FGIN as spindle rotation frequency feedback, therefore the FG CAV Spindle Servo doesn't work well if FG generation is abnormal.

The spindle controller PWM output signal DMO(MT1518 25pin) input to SPIN in Drive IC(BD7907 24pin) after Low-Pass Filtering. The PWM output signal U, V, W signal(BD7907 9,11,18) drives Spindle Motor using Hall Sensor Output signal (HU+, HU-, HV+, HV-, HW+, HW-) and SPIN, and FG pulse output is generated as 18 pulses/rotation.

34 4-3-1. Block Diagram (Wobble CLV Servo)

5V C485 C486 C487

HAVC VHAVC AGC1C AGC2C AGC3C 34 75 81 82 83 D INA 36 ADO A INB 39 S HPF AGC1 - C INC / LPF 37 H HPF AGC2 + B IND Disc 38 BCO Motor unit Optical Pick-up ATFM KRS-340B BPF LPF AGC3 85

WBLSH WBLSH 118 HPF + IC401 116 MT1516 VREF -

IC101 Reference CLK33M MT1518 FD Clock Gen. EFMCLK4 M + U PD Tracking ATFG 1.4V X Clock Gen. ATFG _SYNC ATIP_ C153 BLOCK_CLK 69 FD DMO ATFG SPIN P M + 25 W U PD R146 M X EFM_BLOCK_CLK

Motor Kick REG

4-3-2. Wobble CLV Servo : 4x, 10x, 12x, 16x, 24x, 32x, 40x, 48x. (Blank Area in CD-R/CD-RW)

When drive read/write blank CD-R/RW or read open-session CD-R/CD-RW, the spindle motor is controlled using Wobble CLV Spindle Servo.

The ATFG signal(MT1516 116pin) input to DSP IC(MT1516 69pin). The DSP Controller in MT1518 uses ATFG as linear velocity feed back, therefore the Wobble CLV Spindle Servo doesn¡ﬂt work well when ATFG signal is abnormal. The two types are in the Wobble CLV Spindle Servo. The one is pre-sync mode, the other is sync mode. When Wobble CLV Spindle Servo drives the spindle motor, the pre-sync mode type of Wobble CLV spindle controller controls the spindle motor. After being stabilized, the pre-sync mode is switched to the sync-mode type of Wobble CLV spindle controller.

The spindle controller PWM output signal DMO(MT1518 25pin) input to SPIN in Drive IC(BD7907 24pin) after Low-Pass Filtering. The PWM output signal U,V, W signal(BD7907 9,11,18) drives Spindle Motor using Hall Sensor Output signal (HU+, HU-, HV+, HV-, HW+, HW-) and SPIN.

35 035 004 005 013 5 EXPLODED VIEW 008 006 014

009 015 PBM00 (MAIN C.B.A)

4 012

016

400 A01 010

3 011 031

001

034 026 027

007 025

430

400 400 2 419 A02 021 030 430 030 413

028 003 029 021 413 413 002 050 020 032 413 033 017 400 1 400 020

A B C D E F GH 11 12