DOCSLIB.ORG

A Compilation Flow for Parametric Dataflow: Programming Model

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
A Compilation Flow for Parametric Dataflow: Programming Model A Compilation Flow for Parametric Dataflow: Programming Model, Scheduling, and Application to Heterogeneous MPSoC Mickaël Dardaillon, Kevin Marquet, Tanguy Risset, Jérôme Martin, Henri-Pierre Charles To cite this version: Mickaël Dardaillon, Kevin Marquet, Tanguy Risset, Jérôme Martin, Henri-Pierre Charles. A Compi- lation Flow for Parametric Dataflow: Programming Model, Scheduling, and Application to Hetero- geneous MPSoC. International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), Oct 2014, New Dehli, India. pp.1-10, 10.1145/2656106.2656110. hal-01048649 HAL Id: hal-01048649 https://hal.archives-ouvertes.fr/hal-01048649 Submitted on 5 Aug 2014 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. A Compilation Flow for Parametric Dataflow: Programming Model, Scheduling, and Application to Heterogeneous MPSoC Mickael¨ Dardaillon ∗ Kevin Jer´ omeˆ Martin Henri-Pierre Charles Marquet Tanguy Risset Univ. Grenoble Alpes, Univ. Grenoble Alpes, Universite´ de Lyon, Inria, F-38000 Grenoble, France F-38000 Grenoble, France INSA-Lyon, CITI-Inria, CEA, LETI, Minatec campus, CEA, LIST, Minatec campus, F-69621 Villeurbanne, France F-38054 Grenoble, France F-38054 Grenoble, France fi[email protected] [email protected] [email protected] Abstract 1. Introduction Efficient programming of signal processing applications on embed- Implementation of signal processing algorithms in the dataflow ded systems is a complex problem. High level models such as Syn- programming model is an active research area, and many popular chronous dataflow (SDF) have been privileged candidates for deal- signal processing environments (Simulink, Labview, etc.) already ing with this complexity. These models permit to express inherent use this paradigm. Dataflow programming models are natural can- application parallelism, as well as analysis for both verification and didates for streaming applications. They allow both static analy- optimization. Parametric dataflow models aim at providing suffi- sis and explicit parallelism, making them suitable for embedded cient dynamicity to model new applications, while at the same time applications such as packet processing, cryptography, telecommu- maintaining the high level of analyzability needed for efficient real nications, video decoding, etc. This is of particular interest in the life implementations. wireless digital telecommunication domain where implementation This paper presents a new compilation flow that targets para- of wireless protocol has to be computationally efficient and pre- metric dataflows. Built on the LLVM compiler infrastructure, it of- dictable for real time communication, but also energy efficient to fers an actor based C++ programming model to describe paramet- be embedded in mobile phones. ric graphs, a compilation front-end providing graph analysis fea- “Advanced” 4G (e.g. LTE-Advanced) and forthcoming 5G wire- tures, and a retargetable back-end to map the application on real less protocols, the advent of SDR technologies and the development hardware. This paper gives an overview of this flow, with a spe- of cognitive radio networks reveal new challenges for expressing cific focus on scheduling. The crucial gap between dataflow mod- and compiling wireless applications. The physical layer of wire- els and real hardware on which actor firing is not atomic, as well less protocols have a dynamic behavior and require fast dynamic as the consequences on FIFOs sizing and execution pipelining are reconfigurations which are not possible with today’s wireless de- taken into account.The experimental results illustrate our compila- vices. These technological trends have re-activated past research tion flow applied to compilation of 3GPP LTE-Advanced demodu- axes such as dynamic dataflow compiling or distributed signal pro- lation on a heterogeneous MPSoC with distributed scheduling fea- cessing algorithm. In particular, the need for flexible but still ver- tures. This achieves performances similar to time-consuming hand ifiable programs has led very recently to the appearance of new made optimizations. parametric dataflow Models of Computation (MoC). A typical example to illustrate dataflow dynamicity comes from Categories and Subject Descriptors D.3.2 [Programming Lan- LTE-Advanced: the type of modulation used to decode samples guages]: Language Classifications—Data-flow languages; D.3.3 in a LTE-Advanced frame (i.e. QPSK, 16-QAM, etc.) is indicated [Programming Languages]: Processors—Retargetable compilers within the frame itself. Hence the hardware should be able to adapt to this modulation within a few micro-seconds. Classical dataflow programming models that cannot express dynamic behavior need Keywords data flow, programming model, heterogeneous MP- to be extended [7]. SoC, compiler, scheduling LTE-Advanced decoding, as well as 5G telecommunications protocols, will run on dedicated system on chip (SoC) with suffi- ∗ cient processing power (order of 40 GOPS for LTE-Advanced [12, This work is sponsored by Region´ Rhoneˆ Alpes ADR 11 01302401. 31]) and reasonable power consumption (less than 500 mW). The challenge with these SoCs is to set up a real compilation flow that takes advantage of the hardware acceleration while retaining porta- bility. There already exist some implementations of LTE-Advanced being commercially deployed. Unfortunately these implementa- tions are highly dedicated to a single architecture and are usually manually tuned to meet the hard performance and power-efficiency constraints. Our proposal is a step towards a more generic ap- proach: compiling SDR waveforms from high level dataflow rep- resentations rather than manual tuning. The contributions provided by this work are: 1 2014/8/5 1. A new high level format for expressing parametric dataflow Front-End Back-End graphs based on semi-static actors. This format permits to ex- Reduced dataflow press parametrized dataflow graphs in an high level program- Mapping ming model so as to describe, for instance, a MIMO receiver graph (c++) with N antennas (detailed hereafter). As N should be known before compilation we refer to this format as semi-static. C++ Front-End Scheduling 2. A new static analysis paradigm called micro-schedule that (CLang) permits a more precise analysis of deadlock when mapping parametrized data-flow graph to real architecture. We have used model checking to show the applicability of our micro- Reduced dataflow buffer check schedule paradigm to the specific problem of advanced actor graph (LLVM IR) (SPIN) pipelining in the context of dedicated target architecture with small buffers. dataflow graph Code 3. The first complete compilation flow for the Magali platform [11]. construction generation Magali programs are usually tuned by hand. Our compilation framework has been instantiated for the Magali architecture (with part of it still being manual, such as mapping for in- Extended dataflow SoC code stance) and we obtain performance of the compiled programs graph (ASM) which are roughly equivalent to manually tuned programs. This highlights the fact that our generic compilation framework can adapt to very dedicated architectures such as Magali. Figure 1. Proposed compilation flow from dataflow to heteroge- neous SoC. The paper is organized as follows: section 2 present our compi- lation framework, sections 3 and 4 present parametric synchonous dataflow and the micro-schedule proposal. Experimental results are 2.1.1 Parametric Dataflow Format presented in section 5 and related work are presented in section 6. The input format follows the Schedulable Parametric DataFlow (SPDF) model of computation propose by Fradet et al. in [16]. 2. Overview of Compilation Framework In a dataflow graph (DFG), from the classical dataflow model of In this section, we describe simultaneously the input format used to computation, the integers on the arcs represent the number of express parametric dataflow graphs and the compilation flow that samples produced or consumed by the actor at each execution. we have built to compile these programs. A dataflow compilation In SPDF, this number can be a symbolic parameter whose value framework should compile high level specifications of a dataflow is produced by an actor. A simple SPDF graph is represented on representation (we use the parametric dataflow paradigm) and pro- Fig. 2b, the set p[1] indicates that the actor A produces a new duce the executable codes needed to program the target platform. value for parameter p each time it fires. Also, the graph indicates To be retargetable, it should also take as input a description of the that actor A defines p and then output 2p data. target architecture. As the target architecture often contains dedi- cated processors, we use the term “hardware IP” (or simply IP for //actors declaration intellectual property) to refer the various kind of processors (gen- class A : public Actor { eral or dedicated) that are present in the target machine. public: Our dataflow compilation framework, illustrated in Fig. 1, is PortOut<int> out; ParamOut p; split into two phases:
Load more

Recommended publications
  • Integrating Stream Parallelism and Task Parallelism in a Dataflow Programming Model
    RICE UNIVERSITY Integrating Stream Parallelism and Task Parallelism in a Dataflow Programming Model by Drago¸sDumitru Sb^ırlea A Thesis Submitted in Partial Fulfillment of the Requirements for the Degree Master of Science Approved, Thesis Committee: Vivek Sarkar Professor of Computer Science E.D. Butcher Chair in Engineering Keith D. Cooper L. John and Ann H. Doerr Professor of Computational Engineering Lin Zhong Associate Professor of Electrical and Computer Engineering Jun Shirako Research Scientist Computer Science Department Houston, Texas September 3rd, 2011 ABSTRACT Integrating Stream Parallelism and Task Parallelism in a Dataflow Programming Model by Drago¸sDumitru Sb^ırlea As multicore computing becomes the norm, exploiting parallelism in applications becomes a requirement for all software. Many applications exhibit different kinds of parallelism, but most parallel programming languages are biased towards a specific paradigm, of which two common ones are task and streaming parallelism. This results in a dilemma for programmers who would prefer to use the same language to exploit different paradigms for different applications. Our thesis is an integration of stream- parallel and task-parallel paradigms can be achieved in a single language with high programmability and high resource efficiency, when a general dataflow programming model is used as the foundation. The dataflow model used in this thesis is Intel's Concurrent Collections (CnC). While CnC is general enough to express both task-parallel and stream-parallel paradigms, all current implementations of CnC use task-based runtime systems that do not de- liver the resource efficiency expected from stream-parallel programs. For streaming programs, this use of a task-based runtime system is wasteful of computing cycles and makes memory management more difficult than it needs to be.
    [Show full text]
  • Dataflow Programming Model for Reconfigurable Computing Laurent Gantel, Amel Khiar, Benoît Miramond, Mohamed El Amine Benkhelifa, Fabrice Lemonnier, Lounis Kessal
    Dataflow Programming Model For Reconfigurable Computing Laurent Gantel, Amel Khiar, Benoît Miramond, Mohamed El Amine Benkhelifa, Fabrice Lemonnier, Lounis Kessal To cite this version: Laurent Gantel, Amel Khiar, Benoît Miramond, Mohamed El Amine Benkhelifa, Fabrice Lemonnier, et al.. Dataflow Programming Model For Reconfigurable Computing. 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Jun 2011, Montpellier, France. pp.1-8, 10.1109/ReCoSoC.2011.5981505. hal-00623674 HAL Id: hal-00623674 https://hal.archives-ouvertes.fr/hal-00623674 Submitted on 14 Sep 2011 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Dataflow Programming Model For Reconfigurable Computing L. Gantel∗† and A. Khiar∗ and B. Miramond∗ and A. Benkhelifa∗ and F. Lemonnier† and L. Kessal∗ ∗ ETIS Laboratory – UMR CNRS 8051 † Embedded System Lab Universityof Cergy-Pontoise/ ENSEA Thales Research and Technology 6,avenueduPonceau 1,avenueAugustinFresnel 95014 Cergy-Pontoise, FRANCE 91767 Palaiseau, FRANCE Email {firstname.name}@ensea.fr Email {firstname.name}@thalesgroup.com Abstract—This paper addresses the problem of image process- system, such as sockets. ing algorithms implementation onto dynamically and reconfig- It reduces significantly the work of application programmers urable architectures. Today, these Systems-on-Chip (SoC), offer by relieving them of tedious and error-prone programming.
    [Show full text]
  • Machine Learning with Multiscale Dataflow Computing for High Energy Physics
    Machine Learning with Multiscale Dataflow Computing for High Energy Physics 10.7.2019 Outline • Dataflow Concept and Maxeler • Dataflow for ML and Use Cases • Dataflow Programming Introduction • Hands-on Example 2 Dataflow Concept and Maxeler 10.7.2019 Programmable Spectrum Control-flow processors Dataflow processor GK110 Single-Core CPU Multi-Core Several-Cores Many-Cores Dataflow Increasing Parallelism (#cores) Increasing Core Complexity ( Hardware Clock Frequency ) GPU (NVIDIA, AMD) Intel, AMD Tilera, XMOS etc... Maxeler Hybrid e.g. AMD Fusion, IBM Cell 4 Maxeler Dataflow Engines (DFEs) • Largest Reconfigurable DataflowLMEM Engine (DFE) (Large Memory) Chip 4-96GB MaxRing • O(1k) multipliers High bandwidth memory link Interconnect • O(100k) logic cells Reconfigurable compute fabric • O(10MB) of on-chip SRAM MaxRing Dataflow cores & * links FMEM (fast • O(10GB) of on-card DRAM memory) • DFE-to-DFE interconnect Link to main data network * approaching 128GB on a ¾, single slot PCIe card 5 5 Maxeler Dataflow Engines (DFEs) CPU DFE (Dataflow Engine) 6 Control Flow versus Data Flow • Control Flow: • It is all about how instructions “move” • Data may move along with instructions (secondary issue) • Order of computation is the key • Data Flow: • It is about how data moves through a set of “instructions” in 2D space • Data moves will trigger control • Data availability, transformations and operation latencies are the key 7 Area Utilisation of Modern Chips AMD Bulldozer CPU Nvidia Tesla V100 GPU 8 DFE Area Utilisation 9 Dataflow Computing • A custom chip for a specific application • No instructions ➝ no instruction decode logic • No branches ➝ no branch prediction • Explicit parallelism ➝ no out-of-order scheduling • Data streamed onto-chip ➝ no multi-level caches Memory (Lots (Lots of) Rest of the My Dataflow world Engine 10 Dataflow Computing • Single worker builds a single • Each component is added to bicycle from a group of parts the bicycle in a production line.
    [Show full text]
  • Graceful Language Extensions and Interfaces
    Graceful Language Extensions and Interfaces by Michael Homer A thesis submitted to the Victoria University of Wellington in fulfilment of the requirements for the degree of Doctor of Philosophy Victoria University of Wellington 2014 Abstract Grace is a programming language under development aimed at ed- ucation. Grace is object-oriented, imperative, and block-structured, and intended for use in first- and second-year object-oriented programming courses. We present a number of language features we have designed for Grace and implemented in our self-hosted compiler. We describe the design of a pattern-matching system with object-oriented structure and minimal extension to the language. We give a design for an object-based module system, which we use to build dialects, a means of extending and restricting the language available to the programmer, and of implementing domain-specific languages. We show a visual programming interface that melds visual editing (à la Scratch) with textual editing, and that uses our dialect system, and we give the results of a user experiment we performed to evaluate the usability of our interface. ii ii Acknowledgments The author wishes to acknowledge: • James Noble and David Pearce, his supervisors; • Andrew P. Black and Kim B. Bruce, the other designers of Grace; • Timothy Jones, a coauthor on a paper forming part of this thesis and contributor to Minigrace; • Amy Ruskin, Richard Yannow, and Jameson McCowan, coauthors on other papers; • Daniel Gibbs, Jan Larres, Scott Weston, Bart Jacobs, Charlie Paucard, and Alex Sandilands, other contributors to Minigrace; • Gilad Bracha, Matthias Felleisen, and the other (anonymous) review- ers of papers forming part of this thesis; • the participants in his user study; • David Streader, John Grundy, and Laurence Tratt, examiners of the thesis; • and Alexandra Donnison, Amy Chard, Juanri Barnard, Roma Kla- paukh, and Timothy Jones, for providing feedback on drafts of this thesis.
    [Show full text]
  • Graceful Language Extensions and Interfaces
    Graceful Language Extensions and Interfaces by Michael Homer A thesis submitted to the Victoria University of Wellington in fulfilment of the requirements for the degree of Doctor of Philosophy Victoria University of Wellington 2014 Abstract Grace is a programming language under development aimed at ed- ucation. Grace is object-oriented, imperative, and block-structured, and intended for use in first- and second-year object-oriented programming courses. We present a number of language features we have designed for Grace and implemented in our self-hosted compiler. We describe the design of a pattern-matching system with object-oriented structure and minimal extension to the language. We give a design for an object-based module system, which we use to build dialects, a means of extending and restricting the language available to the programmer, and of implementing domain-specific languages. We show a visual programming interface that melds visual editing (à la Scratch) with textual editing, and that uses our dialect system, and we give the results of a user experiment we performed to evaluate the usability of our interface. ii ii Acknowledgments The author wishes to acknowledge: • James Noble and David Pearce, his supervisors; • Andrew P. Black and Kim B. Bruce, the other designers of Grace; • Timothy Jones, a coauthor on a paper forming part of this thesis and contributor to Minigrace; • Amy Ruskin, Richard Yannow, and Jameson McCowan, coauthors on other papers; • Daniel Gibbs, Jan Larres, Scott Weston, Bart Jacobs, Charlie Paucard, and Alex Sandilands, other contributors to Minigrace; • Gilad Bracha, Matthias Felleisen, and the other (anonymous) review- ers of papers forming part of this thesis; • the participants in his user study; • and Roma Klapaukh, Juanri Barnard, Alexandra Donnison, Amy Chard, and Timothy Jones for providing feedback on drafts of this thesis.
    [Show full text]
  • Proceedings of the 8Th European Lisp Symposium Goldsmiths, University of London, April 20-21, 2015 Julian Padget (Ed.) Sponsors
    Proceedings of the 8th European Lisp Symposium Goldsmiths, University of London, April 20-21, 2015 Julian Padget (ed.) Sponsors We gratefully acknowledge the support given to the 8th European Lisp Symposium by the following sponsors: WWWLISPWORKSCOM i Organization Programme Committee Julian Padget – University of Bath, UK (chair) Giuseppe Attardi — University of Pisa, Italy Sacha Chua — Toronto, Canada Stephen Eglen — University of Cambridge, UK Marc Feeley — University of Montreal, Canada Matthew Flatt — University of Utah, USA Rainer Joswig — Hamburg, Germany Nick Levine — RavenPack, Spain Henry Lieberman — MIT, USA Christian Queinnec — University Pierre et Marie Curie, Paris 6, France Robert Strandh — University of Bordeaux, France Edmund Weitz — University of Applied Sciences, Hamburg, Germany Local Organization Christophe Rhodes – Goldsmiths, University of London, UK (chair) Richard Lewis – Goldsmiths, University of London, UK Shivi Hotwani – Goldsmiths, University of London, UK Didier Verna – EPITA Research and Development Laboratory, France ii Contents Acknowledgments i Messages from the chairs v Invited contributions Quicklisp: On Beyond Beta 2 Zach Beane µKanren: Running the Little Things Backwards 3 Bodil Stokke Escaping the Heap 4 Ahmon Dancy Unwanted Memory Retention 5 Martin Cracauer Peer-reviewed papers Efficient Applicative Programming Environments for Computer Vision Applications 7 Benjamin Seppke and Leonie Dreschler-Fischer Keyboard? How quaint. Visual Dataflow Implemented in Lisp 15 Donald Fisk P2R: Implementation of
    [Show full text]
  • Visualocv: Refined Dataflow Programming Interface for Opencv
    Southern Adventist University KnowledgeExchange@Southern MS in Computer Science Project Reports School of Computing Summer 8-17-2020 VisualOCV: Refined Dataflow ogrPr amming Interface for OpenCV John Boggess [email protected] Follow this and additional works at: https://knowledge.e.southern.edu/mscs_reports Part of the Graphics and Human Computer Interfaces Commons, and the Programming Languages and Compilers Commons Recommended Citation Boggess, John, "VisualOCV: Refined Dataflow ogrPr amming Interface for OpenCV" (2020). MS in Computer Science Project Reports. 5. https://knowledge.e.southern.edu/mscs_reports/5 This Article is brought to you for free and open access by the School of Computing at KnowledgeExchange@Southern. It has been accepted for inclusion in MS in Computer Science Project Reports by an authorized administrator of KnowledgeExchange@Southern. For more information, please contact [email protected]. VISUALOCV: REFINED DATAFLOW PROGRAMMING INTERFACE FOR OPENCV by John R. W. Boggess A PROJECT DEFENSE Presented to the Faculty of The School of Computing at the Southern Adventist University In Partial Fulfilment of Requirements For the Degree of Master of Science Major: Computer Science Under the Supervision of Professor Hall Collegedale, Tennessee August 4, 2020 VisualOVC: Refined Dataflow Programming Interface for OpenCV Approved by: Professor Tyson Hall, Adviser Professor Scot Anderson Professor Robert Ord´o˜nez Date Approved VISUALOCV: REFINED DATAFLOW PROGRAMMING INTERFACE FOR OPENCV John R. W. Boggess Southern Adventist University, 2020 Adviser: Tyson Hall, Ph.D. OpenCV is a popular tool for developing computer vision algorithms; however, prototyping OpenCV-based algorithms is a time consuming and iterative process. VisualOCV is an open source tool to help users better understand and create computer vision algorithms.
    [Show full text]
  • Synchronous Functional Programming: the Lucid Synchrone Experiment ∗
    Synchronous Functional Programming: The Lucid Synchrone Experiment ∗ Paul Caspi † Gr´egoire Hamon Marc Pouzet ‡ VERIMAG The MathWorks LRI, Univ. Paris-Sud 11 Grenoble Boston Orsay 1 Introduction Lucid Synchrone is a programming language dedicated to the design of reactive systems. It is based on the synchronous model of Lustre [25] which it extends with features usually found in functional languages such as higher-order or constructed data-types. The language is equipped with several static analysis, all expressed as special type-systems and used to ensure the absence of certain run-time errors on the final application. It provides, in particular, automatic type and clock inference and statically detects initialization issues or dead-locks. Finally, the language offers both data-flow and automata-based programming inside a unique framework. This chapter is a tutorial introduction to the language. Its aim is to show that techniques can be applied, at the language level, to ease the specification, implementation, and verification of reactive systems. 1.1 Programming Reactive Systems We are interested in programming languages dedicated to the design of reactive systems [31]. Such systems interact continuously with their external environment and have to meet strong temporal constraints: emergency braking systems, plane autopilots, electronic stopwatches, etc. In the mid-70’s, with the shift from mechanical and electronic systems to logical systems, the question of the computer-based implementation of reactive systems arose. At first, these implementations used available general-purpose programming languages, such as assembly, C, or Ada. Low-level languages were prominent as they give strong and precise control over the resources.
    [Show full text]
  • Network Programming Languages
    1 Network Programming Languages Robert Soulé University of Lugano 2 Languages A programming language provides abstractions and ways to compose those abstractions The programming languages you are familiar with are models of computer systems They provide abstractions for data and computation 3 Abstractions abstractions compositions addresses, registers, Assembly languages sequences of instructions instructions, labels booleans, arithmetic, loops, sequences of statements, Procedural languages arrays, procedures procedure calls objects, methods, fields, method invocation, OO languages classes inheritance first-class functions, function application, type Functional languages algebraic data types constructors 4 Domain Specific Languages A general-purpose language provides abstractions for modeling computation A domain-specific language provides abstractions for other domains 5 Benefits of a DSL Can enable optimizations Can ensure program correctness Provide abstractions tailored to a particular domain Allow programmers to use emerging technologies 6 Enabling Optimizations StreamIt: a streaming language designed for static optimization … float->float pipeline ABC { A add float->float filter A() { FIFO queue work pop … push 2 { 2 /*details elided*/ } 3 B pops 3 per firing } B add float->float filter B() { B pushes 1 per firing work pop 3 push 1 { 1 /*details elided*/ } 2 } C add float->float filter C() { work pop 2 push … { … /*details elided*/ } } } Statically known push/pop rates for every operator. 7 Enabling Optimizations … A A A A A A 2 3 B
    [Show full text]
  • Dataflow Supercomputers
    Dataflow Supercomputers Michael J. Flynn Maxeler Technologies and Stanford University Outline ◦ History • Dataflow as a supercomputer technology • openSPL: generalizing the dataflow programming model • Optimizing the hardware for dataflow 3 The great parallel precessor debate of 1967 • Amdahl espouses to sequential machine and posits Amdahl’s law • Danial Slotnick (father of ILLIAC IV) posits the parallel approach while recognizing the problem of programming 4Slotnick’s law “The parallel approach to computing does require that some original thinking be done about numerical analysis and data management in order to secure efficient use. In an environment which has represented the absence of the need to think as the highest virtue this is a decided disadvantage.” -Daniel Slotnick (1967) ….Speedup in parallel processing is achieved by programming effort…… Michael J Flynn The (multi core) Parallel Processor Problem • Efficient distribution of tasks • Inter-node communications (data assembly & dispatch) reduces computational efficiency: speedup/nodes • Memory bottleneck limitations • The sequential programming model: Layers of abstraction hide critical sources of and limits to efficient parallel execution Is there a magic compiler bullet? May’s laws May’s first law: Software efficiency halves every 18 months, exactly compensating for Moore’s Law May’s second law: Compiler technology doubles efficiency no faster than once a decade David May 7 Dataflow as a supercomputer technology • Looking for another way. Some experience from Maxeler • Dataflow is an old technology (70’s and 80’s), conceptually creates and ideal machine to match the program but the interconnect problem was insurmountable for the day. • Today’s FPGAs have come a long way and enable an emulation of the dataflow machine.
    [Show full text]
  • Developments in Dataflow Programming
    University of Exeter Department of Computer Science Developments in Dataflow Programming Daniel Julius Maxwell April 2018 Supervised by Dr Antony Galton & Prof. Jonathan Fieldsend Submitted by Daniel Julius Maxwell to the University of Exeter as a thesis for the degree of Doctor of Philosophy in Computer Science, April 2018. This thesis is available for Library use on the understanding that it is copyright material and that no quotation from the thesis may be published without proper acknowledgement. I certify that all material in this thesis which is not my own work has been identi- fied and that no material has previously been submitted and approved for the award of a degree by this or any other University. (signature) ................................................................................................. Abstract Dataflow has historically been motivated either by parallelism or programmability or some combination of the two. This work, rather than being directed primarily at parallelism or programmability, is instead aimed at maximising the overall utility to the programmer of the system at large. This means that it aims to result in a system in which it is easy to create well-constructed, flexible programs that comply with the principles of software engineering and architecture, but also that the proposed system should be capable at performing practical real-life tasks and should be as widely applicable as can be achieved. With those aims in mind, this project has four goals: • to argue for a unified global dataflow coordination system, extensible to be able to accommodate components of any form that may exist now or in the future; • to establish a link between the design of such a system and the principles of software engineering and architecture; • to design a dataflow coordination system based on those principles, aiming where possible to embed them in the design so that they become easy or unthinking for programmers to apply; and • to implement and test components of the proposed system, using it to build a set of three sample algorithms.
    [Show full text]
  • Easy Dataflow Programming in Clusters with UPC++ Depspawn
    This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication. The final version of record is available at http://dx.doi.org/10.1109/TPDS.2018.2884716 IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 1 Easy Dataflow Programming in Clusters with UPC++ DepSpawn Basilio B. Fraguela, Diego Andrade Abstract—The Partitioned Global Address Space (PGAS) programming model is one of the most relevant proposals to improve the ability of developers to exploit distributed memory systems. However, despite its important advantages with respect to the traditional message-passing paradigm, PGAS has not been yet widely adopted. We think that PGAS libraries are more promising than languages because they avoid the requirement to (re)write the applications using them, with the implied uncertainties related to portability and interoperability with the vast amount of APIs and libraries that exist for widespread languages. Nevertheless, the need to embed these libraries within a host language can limit their expressiveness and very useful features can be missing. This paper contributes to the advance of PGAS by enabling the simple development of arbitrarily complex task-parallel codes following a dataflow approach on top of the PGAS UPC++ library, implemented in C++. In addition, our proposal, called UPC++ DepSpawn, relies on an optimized multithreaded runtime that provides very competitive performance, as our experimental evaluation shows. Index Terms—libraries, parallel programming models, distributed memory, multithreading, programmability, dataflow F 1 INTRODUCTION HILE the exploitation of parallelism is never trivial, Namely, the private space is always the one that can be more W this is particularly true in the case of distributed efficiently accessed and the shared local space is accessible memory systems such as clusters.
    [Show full text]