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Enhanced V2t and Inductor Current Sense Accuracy
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APPLICATION NOTE
Introduction The use of Enhanced V2 control and inductor current dependent (always present) and their combined contribution sense for producing single and multi–phase buck converters to the error budget of the design need to be considered. is an established concept. There are several references one To do this, we must generate the basics behind the design can review for a better understanding of this concept. and then identify the error components. The intent of this document is to shed light on the accuracy one can expect to obtain with a given design. All of the error Basic System Design components and their relationship to the overall accuracy of The following block diagram in Figure 1 shows all of the the system are laid out for the user to see and understand. components that contribute error to the output voltage of the These errors are both random (independent statistically) and converter:
Output Inductor VI
L RI IO/N VO @ IO
PWM Oscillator Power Sw. RC
+ A – S + – Current (N Phases) Sense Amp Vf
Error Amp + – Vf Ibias
Rd Rb Ra Vd VO
Cb Ca
Figure 1. Block Diagram of Enhanced System
Semiconductor Components Industries, LLC, 2001 1 Publication Order Number: July, 2001 – Rev. 0 AND8071/D AND8071/D
The output voltage of the converter is given by the Output Load Line following relationship in terms of the factors in Figure 1. Figure 2 shows a typical load line and the design Each factor is also described. parameters that describe it. It is this load line that one designs to and it is specified for the design: Ra(1 ) sCbRb) Vo + Vf * Ib(Ra ) RȀd ) * Vd Rb(1 ) sCaRa) Vout (1 ) s L ) V + I A R Rl ) V d o s l (1 ) sCR) os Vu Ra Ve RȀd + Rd ǒ1 ) Ǔ Rb VnI Ib – Feedback Bias Current Vf – Feedback Voltage DAC/Offset Set Point Vfl Vi – Input Voltage Vo – Output Voltage Ve V – Current Sense Amp Output Voltage VI d I V – Current Sense Amp Output Offset Voltage out os 0 Im R – Inductor Resistance l Upper Output Voltage Limit – V A – Current Sense Amplifier Gain u s Lower Output Voltage Limit – V I – Output Load Current l o Maximum Output Current – Im N – Number of Phases Nominal Output (No Load) – Vnl Nominal Output (Full Load) – Vfl Another error factor to take into account is the output Output Voltage Error – V ripple, which is given by the following: e Figure 2. Output Load Line Characteristics Vo NVo Vr + · ǒ1 * Ǔ ·|Zo(w + 2pNfs)| (2fs·L) Vi One needs to determine the load line characteristics based w + p |Zo( 2 Nfs)| – Output impedance of output capacitors on the platform. Then the following terms can be computed: at output ripple frequency. Vout (loadline) + Vnl * IoutRo Thus, combining all of the factors together, we get the Ve + Vu * Vnl + Vfl * Vl following expression for the overall output voltage: Vd + Vnl * Vfl V Ra R + d NVo + Vf ) Vr * Ib (Ra ) RȀd ) * Vos * IoAsRl o I Rb m * L Droop voltage Vd Ra (1 ) sCbRb) (1 ) s ) Rl Droop resistance * Ro R (1 ) sC R ) (1 ) sCR) b a a Before proceeding, let’s define a new function called the Let’s define the design’s output droop impedance (Roa) as error load line: follows: Verr + Vout (loadline) * Vo R (1 ) sC R ) (1 ) s L ) R a b b Rl + * * ) Ȁ * a Roa + AsRl (Vnl Vf Ib(Ra Rd ) Vos) Rb (1 ) sCaRa) (1 ) sCR) Rb * Io(Ro * Roa) ) Vr Ra NVo + Vf ) Vr * Ib (Ra ) RȀd ) * Vos * IoRoa From this expression, we can see there is a term dependent Rb on output current and one that is not, as well as the ripple L Let CbRb + CR and + CaRa. term. Let’s analyze the constant term in more detail. The Rl components of the initial set point error (constant term) are Ra as follows: Roa (static) + AsRl Rb evfVf * Feedback Voltage DAC Set Point Error e Ȁ ) * C ibIb(Rd Ra) Feedback Bias Current Error + b L Ȁ Roa (dynamic) As eraIb(Rd ) Ra) * Resistor (a) Error Ca CR Ȁ erdIb(Rd ) Ra) * Resistor (d) Error Notice that Roa is dependent on different factors Ra Vos * VDRP Offset Error depending on if the output is static or dynamic. The static Rb value will determine the set point of the output load line Thus, we can define the no load error voltage as follows: based on the average output load current (Io) and the dynamic value determines how the output load line tracks Vnlerr + changing output currents (DIo). More on this impact to the Ǹ Ȁ Ra (evfVf)2 ) (eib2 ) era2 ) erd2)Ib2(Ra ) Rd )2 ) ǒ VosǓ2 accuracy of the output later. First we must introduce the load Rb line and its associated parameters.
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For the current dependent component, there are both static In this design, Rt is an NTC thermistor, which is typically and dynamic errors. The static and dynamic droop resistance non–linear. The parallel combination of all three resistors is errors are described below (subscript on each error describes used to produce a value for Ra that is nominally the correct source of error). value for the overall design at room temp and to have the same but opposite in sign TC as the copper wire of the inductor. The NOTE: following expression shows the interaction of the temperature Since the current information is summed over all phases, dependent components on the droop resistance: errors associated with components that are used on a per ) L ) phase basis will be statistically reduced by the number of (1 s R ) As(1 sCbRb) Roa + (RlRa) l phases. These components are As, L, Rl, R and C. This factor (1 ) sCaRa) Rb(1 ) sCR) is included in the following expressions, where N is the L L + CaRa å (RlRa) + number of phases. Rl Ca e 2 e 2 RlRa + Rlo (1 ) òlDT) Rao (1 * òaDT) DRo (static) + Ǹǒ as ) rl ) e 2 ) e 2Ǔ N N ra rb [ RloRao [1 ) (òl * òa)DT] @ R (static) ) e (T)R (static) oa rlt oa Testing has shown that this method of compensation Ǹ e 2 e 2 e 2 e 2 tracks temperature changes to within $20% of actual. DRo (dynamic) + ǒ as ) ecb2 ) eca2 ) l ) c ) r N N N N Assuming: @ Roa(dynamic) 1. The inductors DT maximum is $50C over all ambient and operating conditions. The ε (T) term describes the temperature dependent rlt 2. The TC of annealed copper wire is 0.00383%/C. function of the droop resistance (this will be analyzed later). 3. The temperature compensation is good to $20% The error anywhere on the load line as a function of and statistically random. current depends on the static level you are at and the We can conclude the error factor e (T) = e = $4%. The dynamic current step that got you there. The current step size rlt rt correct expression now for DR (static) would be, where e is a function of where you started at and ended up. Based on o rao is the initial error associated with Ra: never exceeding the maximum (Icc max) or minimum (Icc stop–grant), one can statistically describe the current step DRo (static)+ size as a function of these two parameters as follows: eas2 erl2 DIo + 0.7(Iccmax * Iccstopgrant) Ǹǒ ) ) e 2 ) e 2 ) e 2Ǔ Ro (static) N N rao rb rt Thus, the error associated with the dynamic response of the system is basically independent of the static load current A side affect of this method of compensation is on the no and can be given as: load set point, since it is a function of (RȀd ) Ra). + Ȁ ) + Ȁ ) * ò D Verodyn + DIoDRo (dynamic) Rnl Rd Ra Rd Rao (1 a T) The static error term depends on the output current and is + Ȁ ) * Rao ò D (Rd Rao)(1 Ȁ ) a T) described as follows: (Rd Rao) We can generate an error term for Rnl based on the change Verosta + IoDRo (static) in Ra and the error associated with R′d (each being Determining Temperature Dependence Function statistically random). Based on our assumptions, the term To analyze the temperature dependence of the design, we ρaDT = $0.19 and: must first introduce a thermistor to compensate for the Rao RȀd erat + òaDT and erd + erdo temperature dependent change of the inductor’s resistance (RȀd ) Rao) (RȀd ) Rao) Rl. Figure 3 shows the design, which is to make Ra become The expression for the no load error now becomes: an NTC based resistor with the same magnitude TC as V + copper: nlerr Ǹ e 2 ) e 2 ) e 2 ) e 2 ) e 2 2 Ȁ ) 2 Rt – Locate at Inductor, ( vfVf) ( ib rao rat rd )Ib (Rd Ra) Ry – Locate Near IC Tied to Vout at Inductor Ra ) ǒ VosǓ 2 Rb
Connect to V at Rx – Locate Near I out C Socket
Replaces Ra Figure 3. Ra Replacement for Inductor Temperature Compensation
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Determining Overall System Error for assisting in determining the error of the system. The The overall error function for the output can now be following design example will demonstrate the results of a generated from all of the previous terms to yield the particular design. following: Design Example + ) Ǹ ) ) Verr Vr Veronl2 Verodyn2 Verosta2 Using the CS5323, a design for the Willamette FMB is All of the related factors involved for performing the produced. The spreadsheet shown in Figure 5 shows the load calculation of the system error are described throughout this line requirements, the parameters and errors associated with document. A spreadsheet for performing the system design the controller, and the design values for the components used and indicating the error associated with it has been created in conjunction with the controller.
Figure 4. Design Example Spreadsheet
Figure 5 shows the circuit and Figure 6 shows the output error values as well as the design target and actual errors graphically.
http://onsemi.com 4 AND8071/D F F F µ µ F µ µ C2 = 0.022 Rm = 1.5 k Rn = 1.0 k C1 = 0.027 Rc = 8.2 k Ca = 0.18 Cb = 0.082 V–Core Return uP Socket F, 6.3 V F, m F µ Ω High Freq: 10 X5R, 1206 (27 pl) = 56.2 k F + µ Qh – NTD4302 Ql – NTD4302–001 OSC R L = 550 nH RI = 2.4 m R = 24.3 k C = 0.022 Ra = 1.27 k Rb = 6.34 k 4 V OSCON (10 pl) Bulk 560 Rt L and RI L and RI L and RI 180 u 180 u 180 u Qh Qh Qh
QI QI QI
Gnd Gnd Gnd DRN DRN DRN
BG BG 1.0 BG TG TG TG
100 n
VS VS VS CST CST CST
1205 1205 1205 CO CO CO EN EN EN BAT54 1.0 BAT54 1.0 BAT54 1.0 1.0 1.0 R 10 k R R 1.0 k Rb x Cb 27 R Ry Ca C Rc CCC C2 C1 Qn Rx = 1.50 k Ry = 2.21 k Rt = 6.8 k Rn Rm 0.1 20 k FB LIM I REF V DRP OSC CS2 CS1 CS3 REF C Qp V R OSC COMP R 20 k 5323 0.1 ID2 ID0 ID3 ID1 ID4 CC 10 V V GATE 3 GATE GATE 2 GATE GATE 1 GATE V V GND V V 10 k 5 V 12 V Figure 5. Design Example Circuit
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40 Upper Load Line Limit STATIC 20 CURRENT ERROR ERROR Output Upper Error Limit 0 0 22.72 0 5 0.65 23.73 –20 10 1.31 22.77 15 1.96 22.83 –40 20 2.62 22.91 –60 Output Lower 25 3.27 23.02 Error Limit 30 3.92 23.15 –80 35 4.58 23.30 Lower Load Line Limit –100 40 5.23 23.47 45 5.88 23.66
OUTPUT VOLTAGE DROP (mV) OUTPUT VOLTAGE –120 Nominal Load Line 50 6.54 23.88 –140 55 7.19 24.11 0 10 20 30 40 50 60 60 7.85 24.36 OUTPUT CURRENT (A)
Figure 6. Design Example Output Error
It can be seen that the system design meets or exceeds the error requirements for the design.
Design Assistance A free design assistance spreadsheet is available on our website at: http://www.onsemi.com/pub/Collateral/CS53X3DESIGN.XLS
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V2 is a trademark of Switch Power, Inc.
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