6.012 - Microelectronic Devices and Circuits Lecture 20 - Diff-Amp Anal. I: Metrics, Max. Gain - Outline • Announcements Announcements - D.P.: No Early effect in large signal analysis; just LECs. Lec. 21 foils useful; Sp 06 DP foils, too (on Stellar) Do PS #10: free points while working on D.P. • Review - Differential Basics

Difference- and common-mode signals: vID = vIN1- vIN 2, vIC = (vIN1+ vIN2)/2 Half-circuits: half of original with wires shorted or cut (familiar, easy analyses) • Performance metrics - specific to diff. amps. Difference- and common-mode gains Common-mode rejection ratio Input and output voltage swings • Non-linear loads The limitation of resistive loads: Gain limited by voltage supply Non-linear loads: High incremental resistance/small voltage drop • Active loads Lee load load Clif Fonstad, 11/19/09 Lecture 20 - Slide 1 Differential - overview of features and properties Intrinsic advantages and features: - large difference mode gain - small common mode gain - easy to cascade stages; no coupling capacitors - no emitter/source capacitors in CS/CE stages Performance metrics:

- difference mode voltage gain, Avd Today - common mode voltage gain, Avc Today - input resistance, Rin ∞ - output resistance, Rout Lec 21 - common mode input voltage range Today - output voltage swing Today - DC offset on output Lec 21 - Power dissipation Lec 18

Clif Fonstad, 11/19/09 Lecture 20 - Slide 2 Differential Amplifiers - common-mode input range

(VC,min ≤ vC ≤ VC,max)

vGS stays constant + 1.5 V We have said the output changes very little for + + Q4 Q5 Q7 common-mode inputs. Q6 This is true as long as the Q8, Q9 forced out of vC doesn't push the out of - - saturation if vC too high saturation. vDS gets vC + smaller + vC There are a minimum and up Q8 Q9 up maxiumum v : vDS vDS C + + vC - - vc VC, max: As vC increases, vGS down - - vGS down vDS8 and vDS9 decrease + vDS gets until Q8 and Q9 are no vGS stays constant vDS smaller longer in saturation. B + Q10 Q10 forced out VC, min: As vC decreases, of saturation - if vc too low vDS10 decreases until Q10 - is no longer in saturation. - 1.5 V

The node between Q8/Q9 and Q10 moves up and down with vC. Clif Fonstad, 11/19/09 Lecture 20 - Slide 3 Differential Amplifiers - output voltage range (V ≤ v ≤ V ) Fixed + 1.5 V OUT,min OUT OUT,max + vSG16 + vSD12 and vSD16 decrease as + + vOUT goes up, so Q 12 and/or Q16 vSG12 - A vSD16 may be forced out of vSD12 - saturation if v OUT is too high Q16 Q12 - - Q20 + vOUT + 0.6V up 0.6V - - Q18 + Q13 Q17 + vOUT + 0.6V 0.6V 0.6V - down - Q21 - + Q19 + vDS15 vDS19 B vDS15 and vDS19 decrease + Q15 + as vOUT goes down, so vGS15 Fixed vGS19 - - - - Q15 and/or Q19 may be forced out of saturation if - 1.5 V vOUT is too low

As vOUT goes down, Q15 and/or Q19 may go out of saturation; as vOUT goes up, the same may happen to Q12 and/or Q16. Clif Fonstad, 11/19/09 Lecture 20 - Slide 4 Differential Amplifier Analysis - incremental analysis exploiting symmetry and superposition

a LEHC: a LEHC: a LEHC: + one half one half + + one half vid of sym. of sym. -vid vid of sym. - LEC LEC - - LEC

+ + + vod No voltage on -vod vod = Avdvid common links, so - incrementally they - - are grounded.

a LEHC: a LEHC: a LEHC: + one half one half + + one half vic of sym. of sym. vic vic of sym. - LEC LEC - - LEC

No current in + common links, so + + voc incrementally they voc voc = Avcvic - are open. - -

Clif Fonstad, 11/19/09 Lecture 20 - Slide 5 Looking at the design problem circuit: Lesson - Draw the difference and common mode half circuits.

roLL dm roCM Difference mode dm half circuit: Q17 Q20

Q Q + + 8 12 roQ vod R vid 16 LOAD - -

roLLcm Common mode roCMcm half circuit: Q17 Q20 Q + 8 Q12 + r R vic oQ16 voc LOAD 2roQ10 - -

We have reduced the count from 22 to 4, and we see that our complex amplifier is a just cascade of 4 single-transistor stages. Clif Fonstad, 11/19/09 Lecture 20 - Slide 6 What's with these active, nonlinear loads? V+ Why doesn't the design problem use ? RSL Linear Loads: the limit on maximum stage gain CO - with linear resistor loads we must + make a compromise between the Q voltage gain and the size of the + vout vin - output voltage swing. - Maximum voltage gains IBIAS g d + + CS

v in = v gs go v out GSL gmv gs V - - (=1/RSL) - s,b s,b " 2ID RSL 2[ID RSL ]max MOSFET : Av,max = gm RSL = $ [VGS #VT ] [VGS #VT ]min

qIC RSL [IC RSL ]max Bipolar : Av,max = gm RSL = $ kT VThermal

What are [ICRSL]max, [IDRSL]max, and [VGS - VT]min ?

* For a MOSFET, g = (2KI / )1/2 = K(V -V )/ = 2I /(V -V ) Clif Fonstad,! 11/19/09 m D α GS T α D GS T Lecture 20 - Slide 7 Resistor Loads: cont.

- What are [IDRSL]max, [ICRSL]max, and [VGS - VT]min?

[IDRSL]max, [ICRSL]max: V+

- [IDRSL]max and [ICRSL]max are determined by the desired RSL voltage swing at the output and/or by the common- mode input voltage range. CO - The ultimate limit is the + power supply. Q + vout vin - [VGS -V T]min: -

- [VGS - VT]min is set by how close IBIAS to threshold the gate can safely CS be biased before the strong inversion, drift model fails. We V- will say more about this shortly (Slide 23).

Clif Fonstad, 11/19/09 Lecture 20 - Slide 8 Loads: Incrementally large resistance Relatively small quiescent voltage drop - - transistors with a DC input voltage, i.e. set up as sources/sinks -

MOSFET: g d d + + VREF gmbv bs v gs = 0 gmv gs go go - s - = 0 = 0 + - s s, b, g VREF v bs = 0 - ID + b g = " I = o D V Bipolar: A + c c VREF b + v != - gmv ! g! ! 0 go go + = 0 - e e, b VREF e - IC go = " IC = VA Clif Fonstad, 11/19/09 Lecture 20 - Slide 9

! V+ Current Source Loads: the limit on the maximum IStage Load stage gain CO - current source loads eliminate the need to compromise between the + voltage gain and the output Q voltage swing + vout vin - Maximum voltage gains - g d IBIAS + +

v in = v gs go v out CS gmv gs gsl - - s,b s,b V-

" gm 2ID [VGS #VT ] 2VA,eff MOSFET : Av,max = = $ go + gsl ID VA,Q + ID VA,SL [VGS #VT ]min

gm qIC kT VA,eff Bipolar : Av,max = = = go + gsl IC VA,Q + IC VA,SL Vt

VA,QVA,SL kT with VA,eff , Vt Typically V >> [I R ] q A,eff D SL max [VA,Q + VA,SL ] 1/2 !Clif Fonstad, 11/19/09 * For a MOSFET, gm = (2KID/α) = K(VGS -V T)/α = 2ID/(VGS -V T) Lecture 20 - Slide 10

Current Source Loads: the maximum stage gain, cont.

- the similarity in the results for BJT's g d and MOSFETs operating in strong + +

inversion extends to MOSFETs v in = v gs go v out gmv gs gsl operating sub-threshold and in - - velocity saturation, also: s,b s,b The MOSFET LEC: the same for all. Maximum voltage gains

(vGS "VT ) nVt ID MOSFET sub - threshold : iD = IS,s"te , gm = nVt

gm ID nVt VA,eff Av,max = = = go + gsl ID VA,Q + ID VA,SL nVt

* * ID MOSFET w. velocity saturation : iD = W ssat Cox (vGS "VT ), gm = W ssat Cox = (vGS "VT )

gm ID (vGS "VT ) VA,eff Av,max = = # go + gsl ID VA,Q + ID VA,SL (vGS "VT )min

VA,QVA,SL with VA,eff " [VA,Q + VA,SL ] ! Clif Fonstad, 11/19/09 Lecture 20 - Slide 11

! Current Source Loads: Example - biasing a source-coupled pair differential amplifer stage

Want: Build: V+ V+

Q1 Q2 Q3

ILOAD ILOAD

+ + + + v v vO1 vO2 Q4 O1 O2 Q Q4 Q5 - - 5 - - R1 + + + + v vIN1 vIN2 IN1 - - - -

IBIAS Q7 V- Q6 Note: I = I /2 LOAD BIAS V - Note: W1 = W2 = W3 W7 = 2W6 This is nice…can we do even better? Yes, with active loads. Consider… Clif Fonstad, 11/19/09 Lecture 20 - Slide 12 Active Loads: Loads that don't just sit there and look pretty. First example: the current mirror load

V +

Q1 Q2 Signal actively fed from left side to right side, and applied inputs to "stage load" MOSFETs.

+ Q3 Q4 vOUT + + - Now "single ended," i.e. vI1 vI2 only one output, but it - - is twice as large: IBIAS, vout = 2vout1 rob V - Load self-adjusting; circuit forces ILOAD = IBIAS/2.

Clif Fonstad, 11/19/09 Lecture 20 - Slide 13 Active Loads: The current mirror load, cont.

V + Large differential-mode gain, small common-mode Q1 Q2 gain. Also provides high gain conversion from double- id id 2id ended to single-ended output. id id +

The circuit is no Q3 Q4 vOUT + + longer symmetrical, so - half-circuit techniques vid/2 -vid/2 can not be applied. - - The full analysis is IBIAS, found in the course rob text. We find: V - 2g Difference-mode inputs m 3 vout,d = vid 2 (go2 + go4 + gel )

Clif Fonstad, 11/19/09 Lecture 20 - Slide 14 ! Active Loads: The current mirror load

V +

Common-mode inputs Q1 Q2

g v ob v out,c = ic ic ic 0 2gm2 ic ic +

Q3 Q4 vOUT + + - ! vic vic - - IBIAS, rob V - With both inputs:

2gm3 (vin1 " vin 2) gob (vin1 + vin 2) vout = " (go2 + go4 + gel ) 2 2gm2 2

Note: In D.P. the output goes to the base of two BJTs; gel ≠ 0 and can Clif Fonstad, 11/19/09 be important. Lecture 20 - Slide 15

! What if we want an active load and yet stay differential?

Active Loads - The Lee load V + A load for a fully- differential stage Q1 Q2 Q3 Q4 that looks like a large resistance in difference-mode and small resis- tance in common- mode) + + Q5 vO2 Q6 The conventional vO1 + + schematic is drawn - - here, but the coup- vI1 vI2 ling of the load and - - IBIAS, what is happening is made clearer by rob redrawing the V - circuit (next slide.) Normal format

Clif Fonstad, 11/19/09 Lecture 20 - Slide 16 Active Loads - The Lee load. cont. V + Drawn as on the right we see that Q1 Q3 Q2 Q4 the load MOSFETs on each side are + + vO1 + vO2 + vO2 driven by both out- - - puts. The result is - vO1 - different if the two outputs are equal + + Q5 and opposite (diff- Q6 vO1 vO2 mode operation) or + + - - if they are equal vI1 vI2 (common-mode). - - The next few slides IBIAS, give the results for rob each mode. V - Drawn to highlight cross-coupling and demonstrate symmetry Clif Fonstad, 11/19/09 Lecture 20 - Slide 17 V +

Q1 Q3 Q2 Q4 The Lee load:

analysis for + + vod + -vod + -vod difference-mode - - inputs - vod - + + Q5 Q6 vod -vod + + - - vid -vid - - IBIAS, rob V - LEHC: difference-mode

+ +

v id /2 = v gs5 go5 go1 go3 v od /2 gel g v /2 -g v /2 - m5 id gm1v od /2 m3 od -

goLLd

Clif Fonstad, 11/19/09 Lecture 20 - Slide 18 The Lee load: analysis for difference-mode inputs, cont LEHC: difference-mode

+ +

v id /2 = v gs5 go5 go1 go3 v od /2 gel g v /2 -g v /2 - m5 id gm1v od /2 m3 od -

+ +

v id /2 = v gs5 go5 gm1 go1 -gm1 go1 v od /2 gel g v /2 - m5 id -

g d + +

v id /2 = v gs5 go5 goLLd v od /2 gel g = 2g g v oLLd o1 - m5 gs5 - s,b s,b

vod "gm5 Avd = = vid (go5 + 2go1 + ge!1)

Clif Fonstad, 11/19/09 Note: In D.P., the outputs go to MOSFET gates so gel = 0. Lecture 20 - Slide 19

! V +

Q1 Q3 Q2 Q4 The Lee load: + + analysis for voc + voc + voc - - common-mode - voc - inputs + + Q5 Q6 voc voc + + - - voc vI2 - - IBIAS, rob LEHC: common-mode V - + + + v gs5 go5 gm5v gs5 v - go1 go3 ic v oc gel gm1v oc gm3v oc gob /2 - - g Clif Fonstad, 11/19/09 oLLc Lecture 20 - Slide 20 The Lee load: analysis for common-mode inputs, cont LEHC: common-mode

+ + +

v gs5 go5 g v - m5 gs5 v ic v oc gel gm1 go1 gm1 go1

gob /2 - -

g d + + + v gs5 go5 goLLc = 2(gm1 + go1) g v - m5 gs5 v ic v oc g " 2gm1 s,b s,b goLLc el

gob /2 - -

voc "gob ! gob Avc = = # " vic 2[2(gm1 + go1) + ge1] 4gm1

Clif Fonstad, 11/19/09 Note: In D.P., the outputs go to MOSFET gates so gel = 0. Lecture 20 - Slide 21

! Achieving the maximum gain: Comparing linear resistors, current sources, and active loads

Maximum Gains MOSFET (SI) Bipolar-like (BJT and Sub-VT MOS) 2[ID RSL ] [IC RSL ] Linear resistor loads " max " max [vGS #VT ]min n Vt 2V V Current source loads " A,eff " A,eff [vGS #VT ]min n Vt Active loads 2V V Difference mode $ A,eff $ A,eff [vGS #VT ]min n Vt

[vGS #VT ] n V Common mode $ min $ t 2V V Observations: A,bias A,bias - Non-linear (current source) loads typically yield much higher gain than

linear resistors, i.e. VA,eff >> [IDRSL]max. - The bias point is not !as important to BJT-type stage gain. - An SI MOSFET should be biased just above threshold for highest gain.

- For active loads what increases Avd, decreases Avc. Clif Fonstad, 11/19/09 Lecture 20 - Slide 22 Achieving the maximum gain: (vGS-VT)min = ?

For SI-MOSFETs, maximizing the voltage gain (Av or Avd) requires minimizing (VGS-VT). What is the limit?

Sub - threshold : A 1 v = VA n Vt Strong inversion : A 2 v = VA (VGS "VT )

? Av/VA is a smooth ! curve, so clearly (VGS-VT)min > 2nVt.

Note: n = 1.25 was assumed. Clif Fonstad, 11/19/09 Lecture 20 - Slide 23 6.012 - Microelectronic Devices and Circuits Lecture 20 - Diff-Amp Analysis I - Summary • Performance metrics - specific to diff. amps.

Difference- and common-mode gains: Avd = vod/vid, Avc = voc/vic Common-mode rejection ratio: CMRR = Avd/Avc Common-mode input range • Non-linear loads Transistors biased in their constant current regions: MOSFETs in saturation BJTs in their FAR • Active loads Current mirror load: Achieves double- to single-ended conversion without loss of gain Has high resistance for difference-mode signals Has low resistance for common-mode signals Lee Load: Maintains differential signals Has high resistance for difference-mode signals Has low resistance for common-mode signals

Clif Fonstad, 11/19/09 Lecture 20 - Slide 24 MIT OpenCourseWare http://ocw.mit.edu

6.012 Microelectronic Devices and Circuits Fall 2009

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