6.012 - Microelectronic Devices and Circuits Lecture 20 - Diff-Amp Anal. I: Metrics, Max. Gain - Outline • Announcements Announcements - D.P.: No Early effect in large signal analysis; just LECs. Lec. 21 foils useful; Sp 06 DP foils, too (on Stellar) Do PS #10: free points while working on D.P. • Review - Differential Amplifier Basics
Difference- and common-mode signals: vID = vIN1- vIN 2, vIC = (vIN1+ vIN2)/2 Half-circuits: half of original with wires shorted or cut (familiar, easy analyses) • Performance metrics - specific to diff. amps. Difference- and common-mode gains Common-mode rejection ratio Input and output voltage swings • Non-linear loads The limitation of resistive loads: Gain limited by voltage supply Non-linear loads: High incremental resistance/small voltage drop • Active loads Lee load Current mirror load Clif Fonstad, 11/19/09 Lecture 20 - Slide 1 Differential Amplifiers - overview of features and properties Intrinsic advantages and features: - large difference mode gain - small common mode gain - easy to cascade stages; no coupling capacitors - no emitter/source capacitors in CS/CE stages Performance metrics:
- difference mode voltage gain, Avd Today - common mode voltage gain, Avc Today - input resistance, Rin ∞ - output resistance, Rout Lec 21 - common mode input voltage range Today - output voltage swing Today - DC offset on output Lec 21 - Power dissipation Lec 18
Clif Fonstad, 11/19/09 Lecture 20 - Slide 2 Differential Amplifiers - common-mode input range
(VC,min ≤ vC ≤ VC,max)
vGS stays constant + 1.5 V We have said the output changes very little for + + Q4 Q5 Q7 common-mode inputs. Q6 This is true as long as the Q8, Q9 forced out of vC doesn't push the transistors out of - - saturation if vC too high saturation. vDS gets vC + smaller + vC There are a minimum and up Q8 Q9 up maxiumum v : vDS vDS C + + vC - - vc VC, max: As vC increases, vGS down - - vGS down vDS8 and vDS9 decrease + vDS gets until Q8 and Q9 are no vGS stays constant vDS smaller longer in saturation. B + Q10 Q10 forced out VC, min: As vC decreases, of saturation - if vc too low vDS10 decreases until Q10 - is no longer in saturation. - 1.5 V
The node between Q8/Q9 and Q10 moves up and down with vC. Clif Fonstad, 11/19/09 Lecture 20 - Slide 3 Differential Amplifiers - output voltage range (V ≤ v ≤ V ) Fixed + 1.5 V OUT,min OUT OUT,max + vSG16 + vSD12 and vSD16 decrease as + + vOUT goes up, so Q 12 and/or Q16 vSG12 - A vSD16 may be forced out of vSD12 - saturation if v OUT is too high Q16 Q12 - - Q20 + vOUT + 0.6V up 0.6V - - Q18 + Q13 Q17 + vOUT + 0.6V 0.6V 0.6V - down - Q21 - + Q19 + vDS15 vDS19 B vDS15 and vDS19 decrease + Q15 + as vOUT goes down, so vGS15 Fixed vGS19 - - - - Q15 and/or Q19 may be forced out of saturation if - 1.5 V vOUT is too low
As vOUT goes down, Q15 and/or Q19 may go out of saturation; as vOUT goes up, the same may happen to Q12 and/or Q16. Clif Fonstad, 11/19/09 Lecture 20 - Slide 4 Differential Amplifier Analysis - incremental analysis exploiting symmetry and superposition
a LEHC: a LEHC: a LEHC: + one half one half + + one half vid of sym. of sym. -vid vid of sym. - LEC LEC - - LEC
+ + + vod No voltage on -vod vod = Avdvid common links, so - incrementally they - - are grounded.
a LEHC: a LEHC: a LEHC: + one half one half + + one half vic of sym. of sym. vic vic of sym. - LEC LEC - - LEC
No current in + common links, so + + voc incrementally they voc voc = Avcvic - are open. - -
Clif Fonstad, 11/19/09 Lecture 20 - Slide 5 Looking at the design problem circuit: Lesson - Draw the difference and common mode half circuits.
roLL dm roCM Difference mode dm half circuit: Q17 Q20
Q Q + + 8 12 roQ vod R vid 16 LOAD - -
roLLcm Common mode roCMcm half circuit: Q17 Q20 Q + 8 Q12 + r R vic oQ16 voc LOAD 2roQ10 - -
We have reduced the transistor count from 22 to 4, and we see that our complex amplifier is a just cascade of 4 single-transistor stages. Clif Fonstad, 11/19/09 Lecture 20 - Slide 6 What's with these active, nonlinear loads? V+ Why doesn't the design problem use resistors? RSL Linear Resistor Loads: the limit on maximum stage gain CO - with linear resistor loads we must + make a compromise between the Q voltage gain and the size of the + vout vin - output voltage swing. - Maximum voltage gains IBIAS g d + + CS
v in = v gs go v out GSL gmv gs V - - (=1/RSL) - s,b s,b " 2ID RSL 2[ID RSL ]max MOSFET : Av,max = gm RSL = $ [VGS #VT ] [VGS #VT ]min
qIC RSL [IC RSL ]max Bipolar : Av,max = gm RSL = $ kT VThermal
What are [ICRSL]max, [IDRSL]max, and [VGS - VT]min ?
* For a MOSFET, g = (2KI / )1/2 = K(V -V )/ = 2I /(V -V ) Clif Fonstad,! 11/19/09 m D α GS T α D GS T Lecture 20 - Slide 7 Resistor Loads: cont.
- What are [IDRSL]max, [ICRSL]max, and [VGS - VT]min?
[IDRSL]max, [ICRSL]max: V+
- [IDRSL]max and [ICRSL]max are determined by the desired RSL voltage swing at the output and/or by the common- mode input voltage range. CO - The ultimate limit is the + power supply. Q + vout vin - [VGS -V T]min: -
- [VGS - VT]min is set by how close IBIAS to threshold the gate can safely CS be biased before the strong inversion, drift model fails. We V- will say more about this shortly (Slide 23).
Clif Fonstad, 11/19/09 Lecture 20 - Slide 8 Current Source Loads: Incrementally large resistance Relatively small quiescent voltage drop - - transistors with a DC input voltage, i.e. set up as sources/sinks -
MOSFET: g d d + + VREF gmbv bs v gs = 0 gmv gs go go - s - = 0 = 0 + - s s, b, g VREF v bs = 0 - ID + b g = " I = o D V Bipolar: A + c c VREF b + v != - gmv ! g! ! 0 go go + = 0 - e e, b VREF e - IC go = " IC = VA Clif Fonstad, 11/19/09 Lecture 20 - Slide 9
! V+ Current Source Loads: the limit on the maximum IStage Load stage gain CO - current source loads eliminate the need to compromise between the + voltage gain and the output Q voltage swing + vout vin - Maximum voltage gains - g d IBIAS + +
v in = v gs go v out CS gmv gs gsl - - s,b s,b V-
" gm 2ID [VGS #VT ] 2VA,eff MOSFET : Av,max = = $ go + gsl ID VA,Q + ID VA,SL [VGS #VT ]min
gm qIC kT VA,eff Bipolar : Av,max = = = go + gsl IC VA,Q + IC VA,SL Vt
VA,QVA,SL kT with VA,eff , Vt Typically V >> [I R ] q A,eff D SL max [VA,Q + VA,SL ] 1/2 !Clif Fonstad, 11/19/09 * For a MOSFET, gm = (2KID/α) = K(VGS -V T)/α = 2ID/(VGS -V T) Lecture 20 - Slide 10