ECEN326: Electronic Circuits Fall 2017
Lecture 4: Cascode Stages and Current Mirrors
Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements
• HW3 due 10/4 • Exam 1 10/9 • 9:10-10:10 (10 extra minutes) • Closed book w/ one standard note sheet • 8.5”x11” front & back • Bring your calculator • Covers through half of Lecture 4 (cascode material) • Sample Exam1 posted on website • Reading • Razavi Chapter 9
2 Agenda
• Differential Amplifier (Lab 4) Simulation Tips
• Cascode Stages
• Current Mirrors
3 Simulating Differential Amplifiers
• To simulate differential amplifiers, I like to use voltage-controlled voltage sources (VCVS or “E” elements) to generate the differential input signal and combine the differential output into a single-ended signal Note: This example VCVS to combine doesn’t meet the Lab 4 differential output gain spec
Single-ended input source
DC voltage source to 2 VCVS to generate set input DC level differential or common-mode inputs 4 VCVS or E Elements
In_p Out_p Out_p – Out_n = Gain*(In_p – In_n) In_n Out_n
5 Simulating Differential Gain
• Set Inputs E1 Gain=0.5 and E2 Gain=-0.5, Output E3 Gain=1 • With input source AC=1, simply plot the output of E3 (Vo) to get the differential AC gain Gain=1
Single-ended input source DC=0 AC=1
DC voltage source to Gain=0.5 Gain=-0.5 set input DC level
6 Simulating Differential Gain
• Adm = 30.7 V/V = 29.7dB
7 Simulating Differential Rind
• The differential input resistance is equivalent to the differential input (Vi) divided by the input current, where I use the base current of Q1 or IB(Q1)
• Rind = 25.5k
8 Simulating THD
• Set input source to Differential Output Amplitude/Adm
• For Lab 4, that is 5V/Adm • In this example I set the differential input VAMPL = 5V/30.7 = 163mV
• Note that the even-order harmonics (HD2, HD4, …) are very small (ideally zero) • A nice property of ideal differential amplifiers is that they reject even- order harmonics 9 Simulating Common-Mode Gain
• Set Inputs E1 Gain=1 and E2 Gain=1, Output E3 Gain=1 • With input source AC=1, plot one of the single-ended outputs (Vo1 or Vo2) to get the common-mode gain
Single-ended input source DC=0 AC=1
DC voltage source to Gain=1 Gain=1 set input DC level
10 Simulating Common-Mode Gain
• Acm = -57.5dB at 1kHz
11 CMRR Definitions
• CMRR is the ratio of the differential-mode gain (ADM) over the common-mode to differential conversion gain (ACM-DM) A CMRR DM ACM DM • However, this can be hard to simulate without
introducing variations in the circuit, as ACM-DM will be zero without variations • Thus, the lab uses an alternative CMRR definition which is
the ratio of the differential-mode gain (ADM) over the common-mode gain (ACM), which is also a useful figure of
merit ADM CMRRlab ACM
• Using the previous simulation data, the CMRRlab would be 29.7dB – (-57.5db) = 87.2dB 12 Agenda
• Differential Amplifier (Lab 4) Simulation Tips
• Cascode Stages
• Current Mirrors
13 Boosted Output Impedances
Rout1 1 g m RE || r rO RE || r
Rout 2 1 g m RS rO RS
CH 9 Cascode Stages and Current Mirrors 14 Bipolar Cascode Stage
Rout [1 gm (rO2 ||r 1 )]rO1 rO2 || r 1
Rout gm1rO1 rO2 || r1
CH 9 Cascode Stages and Current Mirrors 15 Maximum Bipolar Cascode Output Impedance
R g r r out,max m1 O1 1
Rout,max 1rO1
The maximum output impedance of a bipolar cascode is
bounded by the ever-present r between emitter and ground of Q1.
CH 9 Cascode Stages and Current Mirrors 16 Example: Trying to double Output Impedance
using RE Relative to a simple bottom Q2 cascode, lets
try and double this by adding an additional RE
Rout gm1ro1ro2 r1 RoutA ro2 RE r 2 gm2ro2 RE r 2 gm2ro2RE r 2
In order to roughly double Rout we need Typically r is smaller than rO, so RoutA r 1 2ro2 r 1 in general it is impossible to After some algebra, we find that double the output impedance by
2ro2r 1 degenerating Q2 with a resistor. RoutA CH 9 Cascode Stagesr and1 Currentro2 Mirrors 17 PNP Cascode Stage
Rout [1 gm (rO2 ||r 1 )]rO1 rO2 || r 1
Rout gm1rO1 rO2 || r1
CH 9 Cascode Stages and Current Mirrors 18 Another Interpretation of Bipolar Cascode
Instead of treating cascode as Q2 degenerating Q1, we can also think of it as Q1 stacking on top of Q2 (current source) to boost Q2’s output impedance.
CH 9 Cascode Stages and Current Mirrors 19 False Cascodes
r 2
r 2
1 1 Rout 1 g m1 || rO 2 || r 2 || r 1 rO1 || rO 2 || r 2 || r 1 g m 2 g m 2
g m1 1 Rout 1 rO1 2rO1 g m 2 g m 2
When the emitter of Q1 is connected to the emitter of Q2, it’s no longer a cascode since Q2 becomes a diode-connected device instead of a current source. CH 9 Cascode Stages and Current Mirrors 20 MOS Cascode Stage
Rout 1 gm1rO2 rO1 rO2
Rout gm1rO1rO2
CH 9 Cascode Stages and Current Mirrors 21 Another Interpretation of MOS Cascode
Similar to its bipolar counterpart, MOS cascode can be thought of as stacking a transistor on top of a current source. Unlike bipolar cascode, the output impedance is not limited by .
CH 9 Cascode Stages and Current Mirrors 22 PMOS Cascode Stage
Rout 1 gm1rO2 rO1 rO2
Rout gm1rO1rO2
CH 9 Cascode Stages and Current Mirrors 23 Example: Parasitic Resistance
Rout (1 gm1rO2 )(rO1 || RP ) rO2
RP will lower the output impedance, since its parallel combination with rO1 will always be lower than rO1.
CH 9 Cascode Stages and Current Mirrors 24 Short-Circuit Transconductance – Book Convention
i G out m v in vout 0
The short-circuit transconductance of a circuit measures its strength in converting input voltage to output current. Note, in Lecture 2 we defined Gm with iout flowing out of the circuit. – Either convention is OK, as long as the appropriate Av expression is used
CH 9 Cascode Stages and Current Mirrors 25 Transconductance Example
Gm gm1
CH 9 Cascode Stages and Current Mirrors 26 Derivation of Voltage Gain
vout iout Rout Gm vin Rout
vout vin Gm Rout
Note: If you define Gm with isc flowing outward, then Av=GmRout
By representing a linear circuit with its Norton equivalent,
the relationship between Vout and Vin can be expressed by the product of Gm and Rout.
CH 9 Cascode Stages and Current Mirrors 27 Example: Voltage Gain
Av gm1rO1
CH 9 Cascode Stages and Current Mirrors 28 Comparison between Bipolar Cascode and CE Stage
Since the output impedance of bipolar cascode is higher than that of the CE stage, we would expect its voltage gain to be higher as well.
CH 9 Cascode Stages and Current Mirrors 29 Voltage Gain of Bipolar Cascode Amplifier
Gm gm1
Av gm1rO2gm2(rO1 ||r2)
Since rO is much larger than 1/gm, most of IC,Q1 flows into the diode-connected Q2. Using Rout as before, AV is easily calculated.
CH 9 Cascode Stages and Current Mirrors 30 Practical Cascode Stage
Rout rO3 || gm2rO2 (rO1 || r 2 )
Since no current source can be ideal, the output impedance drops.
CH 9 Cascode Stages and Current Mirrors 31 Improved Cascode Stage
Rout gm3rO3 (rO4 || r 3 ) || gm2rO2 (rO1 || r 2 )
In order to preserve the high output impedance, a cascode PNP current source is used.
CH 9 Cascode Stages and Current Mirrors 32 MOS Cascode Amplifier
Av Gm Rout
Av gm1(1 gm2rO2 )rO1 rO2
Av gm1gm2rO2rO1
CH 9 Cascode Stages and Current Mirrors 33 Improved MOS Cascode Amplifier
Ron gm2rO2rO1
Rop gm3rO3rO4
Rout Ron || Rop
Similar to its bipolar counterpart, the output impedance of a MOS cascode amplifier can be improved by using a PMOS cascode current source.
CH 9 Cascode Stages and Current Mirrors 34 Agenda
• Differential Amplifier (Lab 4) Simulation Tips
• Cascode Stages
• Current Mirrors • BJT Current Mirror Basics • MOS Current Mirrors Basics
35 Temperature and Supply Dependence of Bias Current
R2V CC (R1 R2 ) VT ln(I1 I S ) 2 1 W R2 I1 nCox VDD VTH 2 L R1 R2
Since VT, IS, n, and VTH all depend on temperature, I1 for both bipolar and MOS depends on temperature and supply.
CH 9 Cascode Stages and Current Mirrors 36 Concept of Current Mirror
The motivation behind a current mirror is to sense the current from a “golden current source” and duplicate this “golden current” to other locations.
CH 9 Cascode Stages and Current Mirrors 37 Bipolar Current Mirror Circuitry
Neglecting base current for now (assuming high ), I from the IC expression I S1 I VBE VBE copy REF VT VT IC IS e 1 ISe I S ,REF the voltage produced by the diode connected transistor is The diode-connected Q IREF REF V1 VT ln IS,REF produces an output voltage this voltage forms the V of the output current source to produce BE V1 that forces Icopy1 = IREF, if I V ln REF T Q = Q . IS ,REF 1 REF VT IS1 Icopy IS1e IREF IS,REF CH 9 Cascode Stages and Current Mirrors 38 Multiple Copies of IREF
I Neglecting I S , j B I copy, j I REF I S ,REF
Multiple copies of IREF can be generated at different locations by simply applying the idea of current mirror to more transistors.
CH 9 Cascode Stages and Current Mirrors 39 Current Scaling
Neglecting I B I copy, j nI REF
By scaling the emitter area of Qj n times with respect to QREF, Icopy,j is also n times larger than IREF. This is equivalent to placing n unit-size transistors in parallel.
CH 9 Cascode Stages and Current Mirrors 40 Example: Scaled Current
Neglecting IB
CH 9 Cascode Stages and Current Mirrors 41 Fractional Scaling
Neglecting I 1 B I I copy 3 REF
A fraction of IREF can be created on Q1 by scaling up the emitter area of QREF.
CH 9 Cascode Stages and Current Mirrors 42 Example: Different Mirroring Ratio
Neglecting IB
Using the idea of current scaling and fractional scaling, Icopy2 is 0.5mA and Icopy1 is 0.05mA respectively. All coming from a source of 0.2mA.
CH 9 Cascode Stages and Current Mirrors 43 Mirroring Error Due to Base Currents
Icopy IB1
Icopy I B,REF n
From a KCL at the base/collector of QREF I I I I copy copy copy nI REF n n REF I copy nI I REF 1 copy 1 1 n 1 1 n 1
CH 9 Cascode Stages and Current Mirrors 44 Improved Mirroring Accuracy
From a KCL at the base of Q1 and QREF Icopy 1 IE,F IC,F 1 n
Icopy 1 IB,F 1 2 n
From a KCL at the collector of QREF
Icopy 1 Icopy IREF IB,F IC,REF 1 2 n n nI I REF copy 1 1 n 1 nI REF 2 I copy 1 Because of QF, the base currents of 1 2 n 1 QREF and Q1 are mostly supplied by QF rather than IREF. Mirroring error is reduced times. Q is often called a “ helper” CH 9 Cascode Stages and Current Mirrors F 45 Example: Different Mirroring Ratio Accuracy
The key to finding the copied currents is to first compute the total current copied using 11 IREF n I 4 11I I total REF REF copy,total 1 1 11 15 1 n 1 4 2 total 1 2 1 2 4 Then scale the individual output currents
1 IREF Icopy1 Icopy,total 11 15 4 2
10 10I I I REF copy2 copy,total 15 11 4 2
CH 9 Cascode Stages and Current Mirrors 46 PNP Current Mirror
PNP current mirror is used as a current source load to an NPN amplifier stage. But what if we only have 1 ideal reference current that flows
from VCC, as in all the previous NPN current mirror examples?
CH 9 Cascode Stages and Current Mirrors 47 Generation of IREF for PNP Current Mirror
CH 9 Cascode Stages and Current Mirrors 48 Example: Current Mirror with Discrete Devices
Let QREF and Q1 be discrete NPN devices. IREF and Icopy1 can vary in large magnitude due to IS mismatch. Thus, current mirrors may not be used that often in discrete (board-level) design, but are pervasive in integrated circuit (IC) design
CH 9 Cascode Stages and Current Mirrors 49 Agenda
• Differential Amplifier (Lab 4) Simulation Tips
• Cascode Stages
• Current Mirrors • BJT Current Mirror Basics • MOS Current Mirrors Basics
50 MOS Current Mirror
From the saturation current equation C W I n ox V V 2 D 2 L GS TH ,n the voltage produced by the diode connected transistor is W 2IREF VX VTH ,n L 1 W Icopy IREF nCox W L REF this voltage forms the VGS of the output current source to produce L REF 2 W nCox W 2IREF L 1 Icopy VTH ,n VTH ,n IREF 2 L 1 W W nCox L REF L REF CH 9 Cascode Stages and Current Mirrors 51 Example: Current Scaling
Similar to their bipolar counterpart, MOS current mirrors
can also scale IREF up or down (I1 = 0.2mA, I2 = 0.5mA).
CH 9 Cascode Stages and Current Mirrors 52 CMOS Current Mirror
The idea of combining NMOS and PMOS to produce CMOS current mirror is shown above. CH 9 Cascode Stages and Current Mirrors 53 Next Time
• Frequency response • Razavi Chapter 11
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