DOCSLIB.ORG

VIBNN: Hardware Acceleration of Bayesian Neural Networks

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
VIBNN: Hardware Acceleration of Bayesian Neural Networks VIBNN: Hardware Acceleration of Bayesian Neural Networks Ruizhe Cai∗ Luhao Wang Yanzhi Wang Ao Ren∗ Xuehai Qian Department of Electrical Engineering Ning Liu Massoud Pedram and Computer Science, Syracuse Caiwen Ding Department of Electrical Engineering, University Syracuse, New York Department of Electrical Engineering University of Southern California [email protected] and Computer Science, Syracuse Los Angeles, California University {luhaowan,xuehai.qian,pedram}@usc. Syracuse, New York edu {rcai100,aren,nliu03,cading}@syr.edu ABSTRACT of Bayesian Neural Networks. In ASPLOS ’18: 2018 Architectural Support Bayesian Neural Networks (BNNs) have been proposed to address for Programming Languages and Operating Systems, March 24–28, 2018, the problem of model uncertainty in training and inference. By Williamsburg, VA, USA. ACM, New York, NY, USA, 13 pages. https://doi.org/ 10.1145/3173162.3173212 introducing weights associated with conditioned probability distri- butions, BNNs are capable of resolving the overfitting issue com- monly seen in conventional neural networks and allow for small- 1 INTRODUCTION data training, through the variational inference process. Frequent As a key branch of machine learning and artificial intelligence tech- usage of Gaussian random variables in this process requires a prop- niques, Artificial Neural Networks (ANNs) have been introduced to erly optimized Gaussian Random Number Generator (GRNG). The create machines that can learn and inference [22]. Many different high hardware cost of conventional GRNG makes the hardware types and models of ANNs have been developed for a variety of ap- implementation of BNNs challenging. plications and higher performance, including Convolutional Neural In this paper, we propose VIBNN, an FPGA-based hardware Networks (CNNs), Multi-Layer Perceptron Networks (MLPs), Recur- accelerator design for variational inference on BNNs. We explore rent Neural Networks (RNNs), etc. [44]. With the development and the design space for massive amount of Gaussian variable sampling broad applications of deep learning algorithms, neural networks tasks in BNNs. Specifically, we introduce two high performance have recently achieved tremendous success in various fields, such Gaussian (pseudo) random number generators: 1) the RAM-based as image classification, object recognition, natural language pro- Linear Feedback Gaussian Random Number Generator (RLF-GRNG), cessing, autonomous driving, cancer detection, etc. [1, 14, 45, 47]. which is inspired by the properties of binomial distribution and With the success of deep learning, a rising amount of recent linear feedback logics; and 2) the Bayesian Neural Network-oriented works studied the highly parallel computing paradigm and the Wallace Gaussian Random Number Generator. To achieve high hardware implementations of neural networks[2, 12, 13, 24, 29, scalability and efficient memory access, we propose a deep pipelined 40, 42, 46]. These hardware approaches typically accelerate the accelerator architecture with fast execution and good hardware inference process of neural networks and have shown promising utilization. Experimental results demonstrate that the proposed performances in terms of speed, energy efficiency, and accuracy, VIBNN implementations on an FPGA can achieve throughput of making this approach ideal for embedded and IoT systems. Despite 321,543.4 Images/s and energy efficiency upto 52,694.8 Images/J the significant progress of neural network acceleration , it is well while maintaining similar accuracy as its software counterpart. known that conventional neural networks are prone to the over- fitting issue — situations where the model fail to generalize well KEYWORDS from the training data to the test data [20]. The fundamental reason Bayesian Neural Network, Neural Network, FPGA is that traditional neural network models fail to provide estimates with uncertainty information [9]. This missing characteristic is cru- ACM Reference Format: cial to avoid making over-confident decisions, especially for many Ruizhe Cai, Ao Ren, Ning Liu, Caiwen Ding, Luhao Wang, Xuehai Qian, Massoud Pedram, and Yanzhi Wang. 2018. VIBNN: Hardware Acceleration supervised learning applications with missing or noisy training data. ∗Ruizhe Cai and Ao Ren contributed equally to this work. To solve this issue, the ensemble model has been introduced [17, 21] to combine the results from multiple neural network models, Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed so that the degraded generalization performance can be avoided. for profit or commercial advantage and that copies bear this notice and the full citation As a key example, Bayesian Neural Network (BNNs) are capable of on the first page. Copyrights for components of this work owned by others than ACM forming ensemble models while maintaining limited memory space must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a overhead [32, 58]. In addition, unlike conventional neural networks fee. Request permissions from [email protected]. that rely on huge amount of data for training, BNNs can easily learn ASPLOS ’18, March 24–28, 2018, Williamsburg, VA, USA from small datasets, with the ability to offer uncertainty estimates © 2018 Association for Computing Machinery. ACM ISBN 978-1-4503-4911-6/18/03...$15.00 and the robustness to mitigate over-fitting issues[20]. Moreover, https://doi.org/10.1145/3173162.3173212 the overall accuracy can be improved as well. Specifically, BNNs apply Bayesian inference to provide the prin- of VIBNN are orthogonal to the optimization techniques on convo- cipled uncertainty estimates. In contrast to traditional neural net- lutional layers in previous works [16, 27, 36], and can be applied to works whose weights are fixed values, each weight in BNNs isa CNNs and RNNs as well. random number following a posterior probability distribution, which Experimental results suggest that the proposed VIBNN can achieve is conditioned on a prior probability and its observed data. Unfor- similar accuracy as its software counterpart (BNNs) with very high tunately, the exact Bayesian inference in general is an intractable energy efficiency of 52694:9 images/J thanks to the proposed GRNG problem and obtaining closed-form solutions requires either the structure. assumption of special families of models[11] or the availability of probability distributions [21]. Therefore, an approximation method 2 BNNS USING VARIATIONAL INFERENCE of Bayesian inference is generally used to ensure low computational 2.1 Bayesian Model, Variational Inference, and complexity and high degree of generality [8, 48]. Among various approximation techniques, variational approximation, or variational Gaussian Approximation inference, tends to be faster and easier to implement. Besides, the For a general Bayesian model, the latent variables are w and observed variational inference method offers better scalability with large data points are D. From the Bayes rule, the posterior probability can models, especially for large-scale neural networks in deep learning be calculated as: applications[26], compared with other commonly adopted Bayesian P¹DjwºP¹wº P¹wjDº = (1) inference methods such as Markov Chain Monte Carlo (MCMC) [4]. P¹Dº In addition to faster computation, the variational inference method can efficiently represent weights (probability distributions) with where P¹wº is called the prior probability that indicates the proba- limited amount of parameters. The Bayes-by-Backprop algorithm bility of latent variables w before any data observations. P¹Djwº is proposed by Bluendell et al.[9], for instance, only doubles the pa- called the likelihood, which is the probability of the data D based rameters compared to ANNs while achieving an infinitely large on the latent variable observations w. The denominator P¹Dº is ensemble of models. calculated as the integral of sum over all possible latent variables, ¯ Our focused BNNs in this work belong to the category of feed- i.e., P¹Dº = P¹DjwºP¹wºdw. forward neural networks (FNNs) that have achieved great successes For most of applications of interests, this integral process is in many important fields, such as the HIGGS challenge, the Merck intractable, therefore effective approaches are needed to approxi- Molecular Activity challenge, and the Tox21 Data challenge [30]. mately estimate/evaluate the posterior probability. Variational in- Despite the tremendous attentions on CNNs and RNNs, the accel- ference[28, 52] is a machine learning method for approximating the erators for FNN models are imperative as well, which is noted in posterior probability densities in Bayesian inference models, with a the recent Google paper [29] and the very recently invented SeLU higher convergence rate (compared to MCMC method) and scala- technique [30]. With the recent shift in various fields towards the bility to large problems. As shown in [21], the variational inference deployment of BNNs [9, 19, 50], hardware acceleration for BNNs method posits a family of probability distributions q¹w;θº with becomes critical and has not been well considered in prior works. variation parameters θ to approximate the posterior distribution However, hardware realizations of BNNs pose a fundamental chal- p¹wjDº. lenge compared to the traditional ANNs: the frequent operations
Load more

Recommended publications
  • Space Expansion of Feature Selection for Designing More Accurate Error Predictors
    Space Expansion of Feature Selection for Designing more Accurate Error Predictors Shayan Tabatabaei Nikkhah Mehdi Kamal Ali Afzali-Kusha Department of Electrical School of Electrical and Computer School of Electrical and Computer Engineering Engineering Engineering Eindhoven University of University of Tehran University of Tehran Technology Tehran, Iran Tehran, Iran Eindhoven, The Netherlands [email protected] [email protected] [email protected] Massoud Pedram Department of Electrical Engineering University of Southern California Los Angeles, CA, USA [email protected] ABSTRACT outputs. These errors strongly depend on application inputs [6], putting an extra emphasis on quality control in approximate Approximate computing is being considered as a promising computing. One of the proposed solutions for managing the design paradigm to overcome the energy and performance output quality is sampling the output elements and changing the challenges in computationally demanding applications. If the case approximate configuration accordingly to meet the quality where the accuracy can be configured, the quality level versus requirements [3], [7]. Given that output errors are strongly energy efficiency or delay also may be traded-off. For this dependent to the inputs, this approach is highly susceptible to technique to be used, one needs to make sure a satisfactory user missing the output elements with large errors [6]. experience. This requires employing error predictors to detect There is another approach emphasized in recent works (e.g., unacceptable approximation errors. In this work, we propose a [6], [8], [9]) which leverages light-weight quality checkers to scheduling-aware feature selection method which leverages the dynamically manage the output quality.
    [Show full text]
  • Design and Development MIPS Processor Based on a High Performance and Low Power Architecture on FPGA
    I.J.Modern Education and Computer Science, 2013, 5, 49-59 Published Online June 2013 in MECS (http://www.mecs-press.org/) DOI: 10.5815/ ijmecs.2013.05.06 Design and Development MIPS Processor Based on a High Performance and Low Power Architecture on FPGA Tina Daghooghi Shahid Chamran University, Ahvaz, Iran E-ma il: [email protected] Abstract— This paper presents the design and architecture must contain all of this state. Based on the development of a high performance and low power current architectural state, the processor executes a MIPS microprocessor and implementation on FPGA. In particular instruction with a particular set of data to this method we for achieving high performance and low produce a new architectural state. Some power in the operation of the proposed microprocessor microarchitectures contain additional nonarchitectural use different methods including, unfolding state to either simplify the logic or improve performance transformation (parallel processing), C-slow retiming [2]. The IBM System z10™ microprocessor is currently technique, and double edge registers are used to get even the fastest running 64-bit CISC (co mple x instruction set reduce power consumption. Also others blocks designed computer) microprocessor. This microprocessor operates based on high speed digital circuits. Because of at 4.4 GHz and provides up to two times performance feedback loop in the proposed architecture C-slo w improvement compared with its predecessor, the System retiming can enhance designs that contain feedback z9® microprocessor. In addition to its ultrahigh- loops. The C-slow retiming is well-known for frequency pipeline, the z10™ microprocessor offers optimization and high performance technique, it such performance enhancements as a sophisticated automatically rebalances the registers in the proposed branch-prediction structure, a large second-level private design.
    [Show full text]
  • Model-Order Reduction Using Variational Balanced Truncation with Spectral Shaping Payam Heydari, Member, IEEE, and Massoud Pedram, Fellow, IEEE
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 4, APRIL 2006 879 Model-Order Reduction Using Variational Balanced Truncation With Spectral Shaping Payam Heydari, Member, IEEE, and Massoud Pedram, Fellow, IEEE Abstract—This paper presents a spectrally weighted balanced the reduced system. Extensions of explicit moment-matching truncation (SBT) technique for tightly coupled integrated circuit techniques have been proposed recently, to reduce the linear interconnects, when the interconnect circuit parameters change as time-varying (LTV) as well as nonlinear dynamic systems [7], a result of statistical variations in the manufacturing process. The salient features of this algorithm are the inclusion of the parameter [8]. variation in the RLCK interconnect, the guaranteed passivity of the An alternative model reduction technique is the balanced reduced transfer function, and the availability of provable spec- realization [9]–[11]. While being widely investigated in con- trally weighted error bounds for the reduced-order system. This trol system theory, balanced realization techniques have not paper shows that the variational balanced truncation technique received the same attention as Krylov-based and Pade-based produces reduced systems that accurately follow the time- and fre- quency-domain responses of the original system when variations in model reduction techniques in the context of interconnect the circuit parameters are taken into consideration. Experimental analysis, partly because these methods involve computation-in- results show that the new variational SBT attains, in average, 30% tensive algorithms [9], [11], [12]. Furthermore, it is well known more accuracy than the variational Krylov-subspace-based model- that the balancing transformation may be poorly conditioned order reduction techniques.
    [Show full text]
  • Design Technologies for Low Power VLSI
    To appear in Encyclopedia of Computer Science and Technology, 1995 Design Technologies for Low Power VLSI Massoud Pedram Department of EE-Systems University of Southern California Los Angeles , CA 90089 Abstract Low power has emerged as a principal theme in today’s electronics indus- try. The need for low power has caused a major paradigm shift where power dis- sipation has become as important a consideration as performance and area. This article reviews various strategies and methodologies for designing low power cir- cuits and systems. It describes the many issues facing designers at architectural, logic, circuit and device levels and presents some of the techniques that have been proposed to overcome these difficulties. The article concludes with the future challenges that must be met to design low power, high performance systems. 1. Motivation In the past, the major concerns of the VLSI designer were area, perfor- mance, cost and reliability; power consideration was mostly of only secondary importance. In recent years, however, this has begun to change and, increasingly, power is being given comparable weight to area and speed considerations. Sev- eral factors have contributed to this trend. Perhaps the primary driving factor has been the remarkable success and growth of the class of personal computing devices (portable desktops, audio- and video-based multimedia products) and wireless communications systems (personal digital assistants and personal com- municators) which demand high-speed computation and complex functionality with low power consumption. In these applications, average power consumption is a critical design con- cern. The projected power budget for a battery-powered, A4 format, portable multimedia terminal, when implemented using off-the-shelf components not opti- 2 Design Technologies for Low Power VLSI mized for low-power operation, is about 40 W.
    [Show full text]
  • Block Level Voltage/Frequency Scheduling for Low Power Consumption Under Timing Constraints
    BLOCK LEVEL VOLTAGE/FREQUENCY SCHEDULING FOR LOW POWER CONSUMPTION UNDER TIMING CONSTRAINTS A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF RESEARCH MASTER in the School of Electronic Engineering by Li-Chuan Weng B.Sc. ECE, National Chiao-Tung University, Taiwan September 2004 ©Li-Chuan Weng 2004 DUBLIN CITY UNIVERSITY, IRELAND All rights reserved. No part of this work shall be reproduced, in any form or by any means without the permission from the author. BLOCK LEVEL VOLTAGE/FREQUENCY SCHEDULING FOR LOW POWER CONSUMPTION UNDER TIMING CONSTRAINTS Dissertation of Research Master Degree School of Electronic Engineering Dublin City University Ireland by Li-Chuan Weng September 2004 Supervisor: Dr. XiaoJun Wang, Lecturer, Dublin City University Interanl Examiner: Dr. Noel O’Connor, Lecturer, Dublin City University External Examiner: Dr. Steve Grainger, Professor, Staffordshire University Declaration I hereby certify that this material, which I now submit for assessment on the program of study leading to the award of Research Master Degree of Electronic Engineering is entirely my own work and has not been taken from the work of others save and to the extent that such work has been cited and acknowledged within the text of my work. Signed : ID No, MM* Date : ^ To my parents Acknowledgements This thesis would not have been possible without my advisors, Dr. XiaoJun Wang and Dr. Alan P. Su. Many thanks to Dr. Wang for his inspiration and the time and patience spent in reading this thesis, thanks to Dr. Su for the discussions regarding to my research. Dr. Wang allowing me the freedom to work on topics that I enjoyed.
    [Show full text]
  • SLA-Based, Energy-Efficient Resource Management In
    SLA-based, Energy-Efficient Resource Management in Cloud Computing Systems by Hadi Goudarzi ______________________________________________________________ A Dissertation Presented to the FACULTY OF THE USC GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) December 2013 Copyright 2013 Hadi Goudarzi DEDICATION To my family for their everlasting love and support ii ACKNOWLEDGEMENTS The completion of this doctoral dissertation has been a long journey made possible through the inspiration and support of a handful of people. First and foremost, I especially would like to thank my Ph.D. advisor and dissertation committee chairman, Professor Massoud Pedram, for his enthusiasm, mentorship, and encouragement throughout my graduate studies and academic research. He has been a continuous source of motivation and support for me and I want to sincerely thank him for all I have achieved. His passion for scientific discoveries and his dedication in making technical contributions to the computer engineering community have been invaluable in shaping my academic and professional career. Special thanks go to my dissertation and qualification committees, including Professor Sandeep K. Gupta, Professor Murali Annavaram, Professor Viktor K. Prasanna, Professor Aiichiro Nakano, and Professor Mansour Rahimi for their time, guidance, and feedback. Special thanks to Dr. Shahin Nazarian with whom I have collaborated on some projects. I truly appreciate his mentorship, priceless advices, feedback, and help. I would like to thank those who have in many ways contributed to the success of my academic endeavors. They are the Electrical Engineering staff at the University of Southern California, particularly Annie Yu, Diane Demetras, and Tim Boston; the iii members of the System Power Optimization and Regulation Technology (SPORT) Laboratory; and my best and dearest friends.
    [Show full text]
  • Placement and Beyond in Honor of Ernest S. Kuh
    Placement and Beyond in Honor of Ernest S. Kuh C. K. Cheng UC San Diego March 28, 2011 Placement and Beyond • Ernest S. Kuh is a pioneer and giant in physical layout. • Board of Directors, Cadence Design Syy,stems, San Jose, Ca. (1984‐1991). • Chair, Scientific Advisory Committee, Cadence Design StSystems (1988‐1991). • C&C Prize, Japan Society for Promotion of Communication and Computers, 1996. • Phil Kaufman Award of the Electronic Design Automation Consortium, 1998. • EDAA Lifetime Achievement Award, 2008 • Robert Gustav Kirchhoff Award, 2009 Outlines • Placement • Applications • Team • Second Waves • Scaling and Trends 3 Placement • 1‐D Gate Assignment: Interval Graph • Building Block Layout: BBL, BEAR • Gate Array Layout: BAGEL • Standard Cell Placement: RAMP, PROUD • Performance Driven Placement: Congestion, Timing, Low Power 4 4 Placement • Productivity: Theory, Software Package, Application • Core of Physical Synthesis: > $500 Millions Market ESL Synthesis Logic Synthesis Placement DFT, DFM, ECO Timing Analysis Routing 5 5 Building Block Layout • Issues: Representation, Routability • Nonslicing Architecture –Repr esenta tio n: Tile Plaeane –Routability: Routing Order for 100% routing compltiletion • Applications –Digital Equipment Corporation –ECAD, Cadence 6 Standard Cell Placement • Issues: Complexity, Timing Convergence due to Interconnect Dominance • RAMP, PROUD – Analogy of a resistive network – Quadratic wire length minimization • Analytical vs. Iterative Approaches – Quadratic Programming – Simuldlated Annealing (‘83 Kirkk)kpatrick) • Applications – Qplacer 7 Analytical Placement • Quinn and Breuer, 1979: Force Model – Hook’s law for attraction – Repulsive force for pairs without connection • Antreich, Johannes, and Kirsh, 1982: Systematic Formulation • RAMP, 1983: Delete repulsive force – Sparse matrix operations • GALA, 1984: Gate Array Layout, Hughes Aircraft Comp. • PROUD, 1988: Successive Over Relaxation • Qplacer, 1992: Louis Chao, Cadence • R.S.
    [Show full text]
  • Coupling of Synthesis and Layout: Challenges and Solutions
    Coupling of Synthesis and Layout: Challenges and Solutions Jason Cong Computer Science Department University of California at Los Angels 4711 Boelter Hall, Los Angeles, CA 90095-1596 ABSTRACT As the IC technologies move into deep submicron designs, many physical design effects, such as the delay and noise associated with interconnects, are becoming signi®cant, often dominating, factors in determining the overall circuit performance and relia- bility. Therefore, it is critical to consider layout design during high-level and logic-level synthesis in order to meet tight design constraints and achieve the best possible performance in deep submicron designs. This session starts with an embedded tutorial on "Logical-Physical Co-design for Deep Submicron Circuits: Solutions and Challenges" by Prof. Massoud Pedram, followed by discussions by a panel of experts from industry and academia on the following issues: 1. Reality and Needs: Why the conventional design ¯ow with separated synthesis and physical design fail to work well for today's designs? How bad is the convergence problem using the conventional design ¯ow for today's high-performance designs? Can the conventional design ¯ow be ®xed with incremental enhancements, or a revolutionary change in the design ¯ow and design methodology is needed? 2. Challenges: How synthesis tools can consider detailed physical effects, such as interconnect delay, coupling noise, ground bounce, electro-migration failure, etc. early in the design cycle? If merging logic synthesis and physical design is inevitable, how can we to handle over 100 million transistor designs, while each design step itself is already facing serious challenges to meet the design complexity? 3.
    [Show full text]
  • Payam Heydari Address : 830 Childs Way, SUITE #254 Los Angeles, CA 90089 Tel : (213) 740-4437 Home: (323) 730-0883 Fax : (213) 740-7290 E-Mail : [email protected]
    Payam Heydari Address : 830 Childs Way, SUITE #254 Los Angeles, CA 90089 Tel : (213) 740-4437 Home: (323) 730-0883 Fax : (213) 740-7290 E-mail : [email protected] EDUCATION: 1996-present: Ph.D. - Electrical Engineering - University of Southern California - GPA : 3.95/4.0 Ph.D. Advisor : Professor Massoud Pedram Thesis Title: Noise Analysis and Optimization in High-Frequency Mixed-Signal VLSI Circuits 1993-1995: M.Sc. - Electrical Engineering - Sharif University of Technology - GPA : 3.85/4.0 M.Sc. Advisor : Professor Kambiz Nayebi Thesis Title: A High Quality Mixed Excitation LPC Vocoder for Low Bit-rate Speech Coding 1987-1992: B.Sc. - Electrical Engineering - Sharif University of Technology - GPA : 3.5/4.0* * The average undergraduate GPA at the Sharif University of Tech. is 2.9/4.0. INTERNSHIP: Summer 1997: Bell laboratories, Lucent Technologies, Murray Hill, NJ. Summer 1998: IBM T. J. Watson Research Center, Yorktown Heights, NY. HONORS & AWARDS: • Best Iranian Graduate Student in the area of Electrical Engineering in Southern California, 2001 • Technical Excellence Award from Association of Professors and Scolars of Iranian Heritage, 2001 • Best Paper Award, IEEE International Conference on Computer Design, Austin, Texas, 2000. • Recipient of Travel grant, ASP-DAC conference, Yokohama, Japan, Feb. 2001. • Recipient of Young Student Award, Design Automation Conference, Los Angeles, 2000. • Honorable Mention Award, Department of EE-Systems, University of Southern California, 2000. • Ranked 2nd amongst M.Sc. graduate students, Sharif University of Technology, 1995. • Ranked 10th in the nationwide examination for postgraduate studies, Iran, 1993. • Ranked 5th among more than 200,000 applicants in the nationwide entrance examination, Iran, 1987.
    [Show full text]
  • Global Warming – Impacts and Future Perspective
    GLOBAL WARMING – IMPACTS AND FUTURE PERSPECTIVE Edited by Bharat Raj Singh Global Warming – Impacts and Future Perspective http://dx.doi.org/10.5772/2599 Edited by Bharat Raj Singh Contributors Juan Cagiao Villar, Sebastián Labella Hidalgo, Adolfo Carballo Penela, Breixo Gómez Meijide, C. Aprea, A. Greco, A. Maiorino, Bharat Raj Singh, Onkar Singh, Amjad Anvari Moghaddam, Gabrielle Decamous, Oluwatosin Olofintoye, Josiah Adeyemo, Fred Otieno, Silvia Duhau, Sotoodehnia Poopak, Amiri Roodan Reza, Hiroshi Ujita, Fengjun Duan, D. Vatansever, E. Siores, T. Shah, Robson Ryu Yamamoto, Paulo Celso de Mello-Farias, Fabiano Simões, Flavio Gilberto Herter, Zsuzsa A. Mayer, Andreas Apfelbacher, Andreas Hornung, Karl Cheng, Bharat Raj Singh, Alan Cheng Published by InTech Janeza Trdine 9, 51000 Rijeka, Croatia Copyright © 2012 InTech All chapters are Open Access distributed under the Creative Commons Attribution 3.0 license, which allows users to download, copy and build upon published articles even for commercial purposes, as long as the author and publisher are properly credited, which ensures maximum dissemination and a wider impact of our publications. After this work has been published by InTech, authors have the right to republish it, in whole or part, in any publication of which they are the author, and to make other personal use of the work. Any republication, referencing or personal use of the work must explicitly identify the original source. Notice Statements and opinions expressed in the chapters are these of the individual contributors and not necessarily those of the editors or publisher. No responsibility is accepted for the accuracy of information contained in the published chapters. The publisher assumes no responsibility for any damage or injury to persons or property arising out of the use of any materials, instructions, methods or ideas contained in the book.
    [Show full text]
  • Dr. Massoud Pedram
    Colorado State University’s Information Science and Technology Center (ISTeC) presents two lectures by Dr. Massoud Pedram Stephen and Etta Varra Professor Department of Electrical Engineering University of Southern California ISTeC Distinguished Lecture In conjunction with the Electrical and Computer Engineering Department and Computer Science Department Seminar Series “Digital Infrastructure: Reducing Energy Cost and Environmental Impacts of Information Processing and Communications Systems” Monday October 21, 2013 Reception with refreshments: 10:30 am Lecture: 11:00 am – 12:00 noon Location: Morgan Library, Event Hall Electrical and Computer Engineering Department Special Seminar Sponsored by ISTeC “Designing Energy-Efficient Information Processing Systems” Monday October 21, 2013 Lecture: 2:00 – 3:00 pm Location: Lory Student Center Rm. 224-226 ISTeC (Information Science and Technology Center) is a university-wide organization for promoting, facilitating, and enhancing CSU's research, education, and outreach activities pertaining to the design and innovative application of computer, communication, and information systems. For more information please see ISTeC.ColoState.edu. Abstracts: Digital Infrastructure: Reducing Energy Cost and Environmental Impacts of Information Processing and Communications Systems Modern society’s dependence on information and communication infrastructure (ICI) is so deeply entrenched that it should be treated on par with other critical lifelines of our existence, such as water and electricity. As is the case with any true lifeline, ICI must be reliable, affordable, and sustainable. Meeting these requirements (especially sustainability) is a continued critical challenge, which will be the focus of my talk. More precisely, I will provide an overview of information and communication technology trends in light of various societal and environmental mandates followed by a review of technologies, systems, and hardware/software solutions required to create a sustainable ICI.
    [Show full text]
  • An Efficient Training and Inference Engine for Intelligent Mobile
    1 JointDNN: An Efficient Training and Inference Engine for Intelligent Mobile Cloud Computing Services Amir Erfan Eshratifar, Mohammad Saeed Abrishami, and Massoud Pedram, Fellow, IEEE Abstract—Deep learning models are being deployed in many mobile intelligent applications. End-side services, such as intelligent personal assistants, autonomous cars, and smart home services often employ either simple local models on the mobile or complex remote models on the cloud. However, recent studies have shown that partitioning the DNN computations between the mobile and cloud can increase the latency and energy efficiencies. In this paper, we propose an efficient, adaptive, and practical engine, JointDNN, for collaborative computation between a mobile device and cloud for DNNs in both inference and training phase. JointDNN not only provides an energy and performance efficient method of querying DNNs for the mobile side but also benefits the cloud server by reducing the amount of its workload and communications compared to the cloud-only approach. Given the DNN architecture, we investigate the efficiency of processing some layers on the mobile device and some layers on the cloud server. We provide optimization formulations at layer granularity for forward- and backward-propagations in DNNs, which can adapt to mobile battery limitations and cloud server load constraints and quality of service. JointDNN achieves up to 18 and 32 times reductions on the latency and mobile energy consumption of querying DNNs compared to the status-quo approaches, respectively. Index Terms—deep neural networks, intelligent services, mobile computing, cloud computing F 1 INTRODUCTION In the status-quo approaches, there are two methods DNN architectures are promising solutions in achieving for DNN inference: mobile-only and cloud-only.
    [Show full text]