Efficient Interpreter Optimizations for The
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Towards Performance Measurements for the Java Virtual Machine's
Towards Performance Measurements for the Java Virtual Machine’s invokedynamic Chanwit Kaewkasi School of Computer Engineering Suranaree University of Technology Nakhon Ratchasima, Thailand 30000 [email protected] ABSTRACT JVML are strongly typed. Every symbol is linked before This paper presents a study of a Java Virtual Machine prototype executing a referencing instruction [15]. In the JVM, there are from the Da Vinci Machine project, defined by JSR 292. It four instructions for invoking different kinds of Java method describes binary translation techniques to prepare benchmarks to calls. These instructions serve Java programs perfectly, but not run on the invokedynamic mode of the prototype, resulting that well for other languages that use the JVM as their runtime in the invokedynamic version of the SciMark 2.0 suite. systems [4], [5], [8], [11], [12]. Benchmark preparation techniques presented in this paper are The Da Vinci Machine project [3], also known as the Multi- proven to be useful as the invokedynamic version of Language Virtual Machine (MLVM), is an effort to investigate benchmark programs successfully identified strange slowness and develop prototypes that support a new bytecode instruction, behavior of the invokedynamic mode of the server virtual invokedynamic [15], to extend the Java Virtual Machine machine. (JVM) to other languages, beside the Java language itself. Surprisingly, benchmarking results show that the invoke- Recently, several language implementers have adapted the JVM dynamic mode with direct method handles on the server as a runtime system for their languages, which include virtual machine is just 2-5 times slower than native Java JavaScript [11], JRuby [12], Scala [13], Groovy [8], Clojure [4] invocations, except the Monte Carlo benchmark. -
An Architectural Trail to Threaded-Code Systems
Some programmers question certain claims made for threaded-code systems. The author defends these claims by tracing such a system from its origin in simple concepts. An Architectural Trail to Threaded-Code Systems Peter M. Kogge, IBM Federal Systems Division Interest in software systems based on threaded-code * the concepts and syntax of a high-order language, or concepts has grown remarkably in recent years. Ad- HOL; and vocates of such systems regularly make claims for them * a set of commands for a conversational monitor. that many classical programmers regard as bordering on The ISA (such as it is) is for an abstract machine that is the impossible. Typically, proponents claim that it is very efficiently implemented by short code segments in possible to construct, in 5K to 10K bytes of code, a soft- almost any current machine architecture. The HOL con- ware package that cepts include hierarchical construction of programs, * is conversational like APL, Lisp, or Basic; block structures, GOTOless programming, and user- * includes a compile facility with many high-order definable data structures. The commands for the conver- language, structured-programming constructs; sational monitor permit direct interaction with objects * exhibits performance very close to that of machine- defined by the programmer in terms he defines, not sim- coded program equivalents; ply in the terms of the underlying machine (i.e., core * is written largely in itself and consequently is largely dumps). Further, the command set is directly executable portable; in a conversational mode and includes virtually all com- * places no barriers among combinations of system, mands available in the system; when so executed, they compiler, or application code; function just as they would if found in an executed pro- * can include an integrated, user-controlled virtual gram. -
Basic Threads Programming: Standards and Strategy
Basic Threads Programming: Standards and Strategy Mike Dahlin [email protected] February 13, 2007 1 Motivation Some people rebel against coding standards. I don’t understand the logic. For concurrent programming in particular, there are a few good solutions that have stood the test of time (and many unhappy people who have departed from these solutions.) For concurrent programming, debugging won’t work. You must rely on (a) writing correct code and (b) writing code that you and others can read and understand. Following the rules below will help you write correct, readable code. Rules 2 through 6 below are required coding standards for CS372. Answers to homework and exam problems and project code that do not follow these standards are by definition incorrect. Section 5 discusses additional restrictions for project code (or exam pseudo-code) in Java. Again, answers that deviate from these required coding standars are, by definition, incorrect for this class. If you believe you have a better way to write concurrent programs, that’s great! Bring it to us (before you use it on an assignment!) We will examine your approach the same way we hope that a civil engineering manager would examine a proposal by a bright young civil engineer who has a proposal for a better config- uration of rebar for reinforcing a new bridge: we will hope you have found a better way, but the burden of proof for explaining the superiority of your approach and proving that there are no hidden pitfalls is on you. 2 Coding standards for concurrent programs: 1. -
Effective Inline-Threaded Interpretation of Java Bytecode
Effective Inline-Threaded Interpretation of Java Bytecode Using Preparation Sequences Etienne Gagnon1 and Laurie Hendren2 1 Sable Research Group Universit´eduQu´ebec `a Montr´eal, [email protected] 2 McGill University Montreal, Canada, [email protected] Abstract. Inline-threaded interpretation is a recent technique that im- proves performance by eliminating dispatch overhead within basic blocks for interpreters written in C [11]. The dynamic class loading, lazy class initialization, and multi-threading features of Java reduce the effective- ness of a straight-forward implementation of this technique within Java interpreters. In this paper, we introduce preparation sequences, a new technique that solves the particular challenge of effectively inline-threa- ding Java. We have implemented our technique in the SableVM Java virtual machine, and our experimental results show that using our tech- nique, inline-threaded interpretation of Java, on a set of benchmarks, achieves a speedup ranging from 1.20 to 2.41 over switch-based inter- pretation, and a speedup ranging from 1.15 to 2.14 over direct-threaded interpretation. 1 Introduction One of the main advantages of interpreters written in high-level languages is their simplicity and portability, when compared to static and dynamic compiler-based systems. One of their main drawbacks is poor performance, due to a high cost for dispatching interpreted instructions. In [11], Piumarta and Riccardi introduced a technique called inlined-threading which reduces this overhead by dynamically inlining instruction sequences within basic blocks, leaving a single instruction dispatch at the end of each sequence. To our knowledge, inlined-threading has not been applied to Java interpreters before. -
Java Virtual Machine Guide
Java Platform, Standard Edition Java Virtual Machine Guide Release 14 F23572-02 May 2021 Java Platform, Standard Edition Java Virtual Machine Guide, Release 14 F23572-02 Copyright © 1993, 2021, Oracle and/or its affiliates. This software and related documentation are provided under a license agreement containing restrictions on use and disclosure and are protected by intellectual property laws. Except as expressly permitted in your license agreement or allowed by law, you may not use, copy, reproduce, translate, broadcast, modify, license, transmit, distribute, exhibit, perform, publish, or display any part, in any form, or by any means. Reverse engineering, disassembly, or decompilation of this software, unless required by law for interoperability, is prohibited. The information contained herein is subject to change without notice and is not warranted to be error-free. If you find any errors, please report them to us in writing. If this is software or related documentation that is delivered to the U.S. Government or anyone licensing it on behalf of the U.S. Government, then the following notice is applicable: U.S. GOVERNMENT END USERS: Oracle programs (including any operating system, integrated software, any programs embedded, installed or activated on delivered hardware, and modifications of such programs) and Oracle computer documentation or other Oracle data delivered to or accessed by U.S. Government end users are "commercial computer software" or "commercial computer software documentation" pursuant to the applicable Federal Acquisition -
This Is the Author's Version of a Work Accepted for Publication by Elsevier
NOTICE: This is the author’s version of a work accepted for publication by Elsevier. Changes resulting from the publishing process, including peer review, editing, corrections, structural formatting and other quality control mechanisms, may not be reflected in this document. A definitive version was subsequently published in the Journal of Systems and Software, Volume 86, Issue 2, pp. 278-301, February 2013. Efficient Support of Dynamic Inheritance for Class- and Prototype-based Languages Jose Manuel Redondo, Francisco Ortin University of Oviedo, Computer Science Department, Calvo Sotelo s/n, 33007, Oviedo, Spain Abstract Dynamically typed languages are becoming increasingly popular for different software devel- opment scenarios where runtime adaptability is important. Therefore, existing class-based plat- forms such as Java and .NET have been gradually incorporating dynamic features to support the execution of these languages. The implementations of dynamic languages on these platforms com- monly generate an extra layer of software over the virtual machine, which reproduces the reflective prototype-based object model provided by most dynamic languages. Simulating this model fre- quently involves a runtime performance penalty, and makes the interoperation between class- and prototype-based languages difficult. Instead of simulating the reflective model of dynamic languages, our approach has been to extend the object-model of an efficient class-based virtual machine with prototype-based seman- tics, so that it can directly support both kinds of languages. Consequently, we obtain the runtime performance improvement of using the virtual machine JIT compiler, while a direct interoperation between languages compiled to our platform is also possible. In this paper, we formalize dynamic inheritance for both class- and prototype-based languages, and implement it as an extension of an efficient virtual machine that performs JIT compilation. -
Dynamic Code Evolution for Java
JOHANNES KEPLER UNIVERSITAT¨ LINZ JKU Technisch-Naturwissenschaftliche Fakult¨at Dynamic Code Evolution for Java DISSERTATION zur Erlangung des akademischen Grades Doktor im Doktoratsstudium der Technischen Wissenschaften Eingereicht von: Dipl.-Ing. Thomas W¨urthinger Angefertigt am: Institut f¨ur Systemsoftware Beurteilung: Univ.-Prof. Dipl.-Ing. Dr. Dr.h.c. Hanspeter M¨ossenb¨ock (Betreuung) Univ.-Prof. Dipl.-Ing. Dr. Michael Franz Linz, M¨arz 2011 Oracle, Java, HotSpot, and all Java-based trademarks are trademarks or registered trademarks of Oracle in the United States and other countries. All other product names mentioned herein are trademarks or registered trademarks of their respective owners. Abstract Dynamic code evolution allows changes to the behavior of a running program. The pro- gram is temporarily suspended, the programmer changes its code, and then the execution continues with the new version of the program. The code of a Java program consists of the definitions of Java classes. This thesis describes a novel algorithm for performing unlimited dynamic class redefi- nitions in a Java virtual machine. The supported changes include adding and removing fields and methods as well as changes to the class hierarchy. Updates can be performed at any point in time and old versions of currently active methods will continue running. Type safety violations of a change are detected and cause the redefinition to fail grace- fully. Additionally, an algorithm for calling deleted methods and accessing deleted static fields improves the behavior in case of inconsistencies between running code and new class definitions. The thesis also presents a programming model for safe dynamic updates and discusses useful update limitations that allow a programmer to reason about the semantic correctness of an update. -
Funktionaalisten Kielten Ydinpiirteiden Toteutus Oliokielten Virtuaalikonealustoilla
Funktionaalisten kielten ydinpiirteiden toteutus oliokielten virtuaalikonealustoilla Laura Leppänen Pro gradu -tutkielma HELSINGIN YLIOPISTO Tietojenkäsittelytieteen laitos Helsinki, 30. lokakuuta 2016 HELSINGIN YLIOPISTO — HELSINGFORS UNIVERSITET — UNIVERSITY OF HELSINKI Tiedekunta — Fakultet — Faculty Laitos — Institution — Department Matemaattis-luonnontieteellinen Tietojenkäsittelytieteen laitos Tekijä — Författare — Author Laura Leppänen Työn nimi — Arbetets titel — Title Funktionaalisten kielten ydinpiirteiden toteutus oliokielten virtuaalikonealustoilla Oppiaine — Läroämne — Subject Tietojenkäsittelytiede Työn laji — Arbetets art — Level Aika — Datum — Month and year Sivumäärä — Sidoantal — Number of pages Pro gradu -tutkielma 30. lokakuuta 2016 106 sivua + 25 sivua liitteissä Tiivistelmä — Referat — Abstract Tutkielma käsittelee funktionaalisille kielille tyypillisten piirteiden, ensimmäisen luo- kan funktioarvojen ja häntäkutsujen toteutusta oliokielille suunnatuilla JVM- ja .NET- virtuaalikonealustoilla. Oliokielille suunnattujen virtuaalikonealustojen tarjoamien tavukoodi- rajapintojen rajoitteet verrattuna matalamman tason assembly-kieliin ovat pitkään aiheut- taneet valtavirran oliokielistä poikkeavien kielten toteuttajille päänvaivaa. Tarkasteltavista alustoista .NET-alustan tavoitteena on alusta asti ollut monenlaisten kielten tukeminen. JVM- alustalla erilaisten kielten toteuttajien tarpeisiin on havahduttu vasta viimeisten vuosien aikana. Tutkielma tarkastelee, millaisia mahdollisuuksia alustat nykyisellään tarjoavat ensim- -
Threaded Code Is Not in Fact Implemented in the Computer's Hardware
desired generality in others. In summary, when writing hard code the user needs relatively many instructions, each of which executes relatively rapidly. An interpreter, by contrast, is a vehicle by which the user can choose his own instruction set to correspond Programming R. Morris to his specific problem. Obviously such freedom allows Techniques Editor a much shorter program for that: problem to be written. The penalty is that the instruction set of the interpreter Threaded Code is not in fact implemented in the computer's hardware. Instead the interpreter must itself be a computer pro- James R. Bell gram which simulates the action of the interpretive in- Digital Equipment Corporation struction set in terms of the actual instruction set. This can be a time-consuming proposition. Thus interpretive code tends to be shorter but slower than hard code. The concept of "threaded code" is presented as an It is instructive to look at the relation between the alternative to machine language code. Hardware and host hardware and the alternatives discussed. In the software realizations of it are given. In software it is case of hard code an instruction directs the flow of realized as interpretive code not needing an interpreter. processing by its actual execution from the IR, or in- Extensions and optimizations are mentioned. struction register, of the machine. In the case of an in- Key Words and Phrases: interpreter, machine code, terpreter, an "instruction" is in fact merely a datum time tradeoff, space tradeoff, compiled code, subroutine from the interpreting program. Thus it directs the flow calls, threaded code of processing from an accumulator or the equivalent. -
Csc 453 Interpreters & Interpretation
CSc 453 Interpreters & Interpretation Saumya Debray The University of Arizona Tucson Interpreters An interpreter is a program that executes another program. An interpreter implements a virtual machine , which may be different from the underlying hardware platform. Examples: Java Virtual Machine; VMs for high-level languages such as Scheme, Prolog, Icon, Smalltalk, Perl, Tcl. The virtual machine is often at a higher level of semantic abstraction than the native hardware. This can help portability, but affects performance. CSc 453: Interpreters & Interpretation 2 1 Interpretation vs. Compilation CSc 453: Interpreters & Interpretation 3 Interpreter Operation ip = start of program; while ( ¬ done ) { op = current operation at ip ; execute code for op on current operands; advance ip to next operation; } CSc 453: Interpreters & Interpretation 4 2 Interpreter Design Issues Encoding the operation I.e., getting from the opcode to the code for that operation (“dispatch”): byte code (e.g., JVM) indirect threaded code direct threaded code. Representing operands register machines: operations are performed on a fixed finite set of global locations (“registers”) (e.g.: SPIM); stack machines: operations are performed on the top of a stack of operands (e.g.: JVM). CSc 453: Interpreters & Interpretation 5 Byte Code Operations encoded as small integers (~1 byte). The interpreter uses the opcode to index into a table of code addresses: while ( TRUE ) { byte op = ∗∗∗ip; switch ( op ) { case ADD: … perform addition ; break; case SUB: … perform subtraction ; break; … } } Advantages: simple, portable. Disadvantages: inefficient. CSc 453: Interpreters & Interpretation 6 3 Direct Threaded Code Indexing through a jump table (as with byte code) is expensive. Idea : Use the address of the code for an operation as the opcode for that operation. -
Static Analysis of Lockless Microcontroller C Programs
Static Analysis of Lockless Microcontroller C Programs Eva Beckschulze Sebastian Biallas Stefan Kowalewski Embedded Software Laboratory RWTH Aachen University, Germany {lastname}@embedded.rwth-aachen.de Concurrently accessing shared data without locking is usually a subject to race conditions resulting in inconsistent or corrupted data. However, there are programs operating correctly without locking by exploiting the atomicity of certain operations on a specific hardware. In this paper, we describe how to precisely analyze lockless microcontroller C programs with interrupts by taking the hardware architecture into account. We evaluate this technique in an octagon-based value range analysis using access-based localization to increase efficiency. 1 Introduction Static analysis based on abstract interpretation [7] is a formal method that found its way into practice by several commercial code analysis tools. Proving the absence of run-time errors in microcontroller programs is of particular importance as microcontrollers are often deployed in safety-critical systems. However, C code analyzers usually do not cope with C extensions and hardware-specific control prevalent in microcontroller programs. This control is not only necessary for data input/output but also needed to implement interrupt service routines (ISRs), which allows some form of concurrency and can be used for asynchronous hardware communication and periodic tasks. Since the control functions of the hardware are often exposed through normal memory accesses, a sound analysis of microcontroller programs has to reflect these registers in its memory model. On the Atmega16 [2], for example, it is possible to enable/disable interrupts by a write to the SREG register which is located at the memory address 0x5F. -
A Case Study of Multi-Threading in the Embedded Space
A Case Study of Multi-Threading in the Embedded Space Greg Hoover Forrest Brewer Timothy Sherwood University of California, Santa University of California, Santa University of California, Santa Barbara Barbara Barbara Engineering I Engineering I Engineering I Santa Barbara, California Santa Barbara, California Santa Barbara, California 93106 93106 93106 [email protected] [email protected] [email protected] ABSTRACT vironment. Such systems open the possibility of early de- The continuing miniaturization of technology coupled with tection of structural failure, tracking microclimates in for- wireless networks has made it feasible to physically embed est canopies, and observing migratory patterns of any num- sensor network systems into the environment. Sensor net ber of species [16, 11, 29]. In an ideal world, these tiny processors are tasked with the job of handling a disparate digital systems would be operating a wireless network, han- set of interrupt driven activity, from networks to timers to dling sensor readings, controlling electro-statically-activated the sensors themselves. In this paper, we demonstrate the devices, processing software updates, and performing dis- advantages of a tiny multi-threaded microcontroller design tributed computations. To handle all of these functions at which targets embedded applications that need to respond the required throughput, we argue for the use of dynamic to events at high speed. While multi-threading is typically multi-threading at all levels of the microcontroller design. used to improve resource utilization, in the embedded space At first this concept may seem counterintuitive as most it can provide zero-cycle context switching and interrupt ser- multi-threaded architectures were developed to better-exploit vice threads (IST), enabling complex programmable control an abundance of resources [25], something that these sys- in latency constrained environments.