Under the Hood of a DC/DC Boost Converter Brian T. Lynch

Ab s t r a c t Despite having the same number of significant power components as the well-understood , the boost converter has the reputation of being low-performance and complicated to design. This topic discusses continuous-conduction-mode (CCM) and discontinuous-conduction-mode (DCM) operation of the boost converter in practical terms and presents a mathematical model for analysis of voltage-mode and current-mode feedback control.

I. In t r o d u c t i o n II. Tr a n s f e r o f En e r g y Necessitated by the proliferation of devices To help facilitate this discussion of the boost requiring unique voltage rails, the single-voltage, power stage, we begin with three underlying intermediate-bus architecture has gained in assumptions. popularity over using a centralized, multivoltage 1. In steady-state operation, the volt seconds (V•s) 3 Topic source. Localized point-of-load converters across the , L1, during the ON time of the optimized for specific loads remove from the , Q1, must be equal to the V•s across the system the overhead of multiple-voltage inductor during the switch OFF time. In other distribution. While stepping the intermediate-bus words, the average V•s over a single switching voltage down to a lower voltage with buck period is zero. This assumption ensures steady- converters is the most common requirement, there state operation from one switching cycle to the is the occasional need for a boost converter to step next. the bus voltage up. 2. Charge balance in output . In steady- This topic discusses a few basics of the boost state operation, the ampere-seconds (A•s) charging topology, going into some detailed discussion the output capacitor during the ON time of the regarding modes of operation, and then discusses switch must be equal to the A•s discharging of the design trade-offs in the control options and their capacitor during the switch OFF time. This means effect on overall converter per­ V formance. Mathematical models IN aid in the analysis. Examples presented in this R1 TPS40210 text discuss a number of fixed- C7 L1 1 10 V RC VDD OUT frequency boost converters C6 2 9 designed with a TPS40210 con­ SS BP D1 R6 C3 3 8 Q1 troller operating at a nominal DIS/EN GDRV C2 R2 R4 C1 700 kHz (Fig. 1). For all of the 4 7 R3 COMP ISNS converters, the input voltage is C8 C4 5 6 R7 R8 12 V and the output voltage is FB GND 24 V, with a sourcing-current C5 capability of 1 A. The individual R5 implementations of each converter will highlight differences in various modes of operation. Fig. 1. Generalized circuit schematic of a TPS40210-based boost converter.

3-1 that the average A•s over a single switch period is cycle, plus an amount for converter losses. The zero. This assumption ensures steady-state energy in the inductor depletes to zero before the operation from one switching cycle to the next. end of each switching cycle, resulting in a period 3. The ripple voltage across the output capacitor is of no energy flow, or discontinuous operation. small compared to the DC voltage generated by These two operating modes have significant the converter. This assumption simplifies the influence on the performance of the converter. analysis somewhat when we look at the V•s One of the first decisions to make in designing a balance across the inductor. boost converter is to select in which of these two The nonsynchronous boost topology is one of modes the converter is to operate. the few topologies where, even if the converter is Unlike a buck-derived topology, energy flows off, there is an output voltage. Unfortunately, the to the load during the OFF time of the control voltage is unregulated and is subject to every switch. The effect of any control action during the change of the input. Under this steady-state ON time of the switch is delayed until the switch condition, load current—if there is any—flows is turned OFF. For example, during a load-step continuously through the inductor and and increase, the output voltage drops due to into the load. With the exception of the drop insufficient stored energy in the inductor. The across the inductor due to the DC resistance, there lower output voltage in turn creates a demand for is no voltage across the inductor. a longer pulse width in order to store additional

Topic 3 Topic To generate a regulated output voltage, the energy in the inductor. In a fixed-frequency switch must begin switching. When switch Q1 converter, a longer ON-time pulse means a shorter turns ON, the voltage across the inductor increases OFF-time pulse, which means the output will to approximately the input voltage, and energy is droop even further. It is not until the release of the stored in the inductor. The amount of energy energy in the inductor from the longer ON-time stored is a function of the input voltage, the pulse that the output voltage will reverse towards inductance, and the duration of the ON pulse. The regulation. From the standpoint of small-signal diode , D1, is reverse-biased during this feedback control, the phenomenon of the output time interval. When the switch turns OFF, the response initially going in the opposite direction stored energy releases to the output through of the desired correction creates a right-half-plane the rectifier. The output capacitor filters the (RHP) zero, so named because of the placement of pulsating current, allowing DC current to flow the zeros in the right-half plane of a complex into the load. s-plane. The frequency-response curve in Fig. 2 There are two fundamentally different shows that with a left-half-plane (LHP) zero (as operating modes for the converter. The first, from the ESR of a capacitor), the phase increases continuous-conduction mode (CCM), is where with increasing gain; and with an RHP zero, the energy in the inductor flows continuously during phase decreases with increasing gain. This the operation of the converter. The increase of condition makes compensating the control loop a stored energy in the inductor during the ON time difficult task if a feedback loop is to have adequate of the switch is equal to the energy discharged into phase margin. This discussion later shows that the output during the OFF time of the switch, design decisions regarding mode of operation and ensuring steady-state operation. At the end of the the choice of control method largely alleviate the discharge interval, residual energy remains in the RHP-zero effect. inductor. During the next ON interval of the switch, energy builds from that residual level to A. Continuous-Conduction Mode (CCM) that required by the load for the next switching In CCM, power transfer is a two-step process. cycle. When the switch is ON, stored energy builds in In the other mode, discontinuous-conduction the inductor. When the switch is OFF, energy mode (DCM), the energy stored in the inductor transfers to the output through the diode. The during the ON interval of the switch is equal only switch current is a stepped sawtooth with a fixed to the energy required by the load for one switching steady-state ON time with some amount of ripple

3-2 40 Important to any model is the understanding of the current in each Phase LHP Zero 100 ) 30 of the relevant components in the ) power path. The mathematical

dB

(

Degrees construction of these currents helps

(

in 20 0 to determine the magnitude and

Ga Phase RHP Zero shapes of these currents. 10 –100 Phase Gain With zero losses assumed, the inductor current’s ON-time slope 0 is 10 100 1k 10 k 100 k V Frequency(Hz) m = IN . ILO()N (1) Fig. 2. Examples of frequency response RHP and LHP zeros. L During the OFF time, the current superimposed. During the ON time of the current will have a slope of switch, if we assume zero losses for the moment, VV− m = IN OUT . (2) the voltage across the inductor is approximately ILO()FF L the input voltage; and the voltage across the rectifier is the capacitor, or output voltage. When If the V•s during the ON time of the switch is Topic 3 Topic the switch turns OFF, the energy stored in the equated with the V•s during the OFF time of the inductor releases into the output through the switch, rectifier. The voltage across the inductor is VIN VVIN − OUT ××DTs = ××()1− DTs. (3) approximately the input-to-output voltage L L difference, and the voltage across the switch becomes approximately the output voltage (see Fig. 3).

Switch- Node VOUT Voltage

I Switch L(ON) Current

I Rectifier L(OFF) I Current OUT_AVG

mIL(ON) mIL(OFF) Inductor Current

Switch On Switch Off

Fig. 3. Representative CCM waveforms.

*See Appendix C for a glossary of variables.

3-3 Solving for the switch duty cycle, D, results in the switch turns on. During this third interval (the V idle period in Fig. 5), the voltage across the D =−1 IN . CCM()ideal V (4) inductor decays to zero, the voltage across the OUT switch decays to the input voltage, and the input- Power-stage input and output losses that impact to-output voltage differential is across the rectifier. the duty cycle are shown in Fig. 4. The input losses There is essentially no current flowing in the include the inductor winding resistance (RL), the power stage during this interval. switch MOSFET RDS(ON), and (in the case of a current-mode-controlled converter) a current- sense (RISENSE). The output losses are ON Losses OFF Losses L RL D1 represented by the output diode rectifier, D1. Input Output If the loss elements of the power-stage Voltage Voltage components are included, the equation for the duty

cycle in CCM is shown by Equation (5) below. RDS(ON) Equation (5) holds true for CCM when the ripple COUT Load current in the inductor is small relative to the RISENSE average DC current. The equation is “close” when there is a high percentage of ripple current.

Topic 3 Topic Reassuringly, if the losses in Equation (5) reduce to zero, the equation simplifies to the ideal case. Fig. 4. Boost model with loss elements. B. Discontinuous-Conduction Mode (DCM) In DCM, a switching cycle is composed of three intervals.

The first two are the same as Switch- in CCM, where energy is Node VOUT stored in the inductor during Voltage VIN the ON time of the switch, and Switch transferred to the load during I Current L(ON) the OFF time of the switch. In Idle DCM, however, all of the period Rectifier IL(OFF) energy in the inductor transfers Current IOUT_AVG to the load during this second mIL(ON) mIL(OFF) interval. The third interval Inductor begins when the energy in the Current inductor is depleted, and Switch On terminates at the end of the tfall Switch switching period the next time Off Fig. 5. Representative DCM waveforms.

VI++×()RR   IN DS()ON ISENSE   2  ++VI×()RR+  −+4IR××()RV()+ V  (5)   IN OUTDSO()NISENSE  OUT DS()ON ISENSE OUT d  DCCM =−1 2(VVOUT + d )

3-4 Observe that since all of the energy in the Solving for the DCM duty cycle results in inductor discharges in each switching cycle during 1 2LV×()OUTI− V N an interval shorter than the (1 – D) conduction DDCM = × IOUT . (9) V T time, the peak current in the diode must be higher IN s in DCM than in CCM. If the peak current is higher If losses are included, the following is a in the diode in DCM, then the peak current will be slightly better approximation†: higher in the inductor and in the switch as well. 1 With higher peaks and the same or a shorter DDCM = (10) ()VVOUTd+ × IOUT conduction time, as a rule of thumb, we can VIN − × R tot assume that for the same components, the RMS VIN losses will be greater in a DCM converter than in 2LV×()OUTd+−VVIN an equivalent CCM converter. × × IOUT T The operating duty cycle of the converter in s DCM is dependent not only on the input and output voltages but on the inductor value and load III. De s i g n i n g f o r CCM o r current as well. In addition, in DCM operation, the DCM Op e r at i o n current fall time (to zero) is usually different than The two design parameters whose selection a (1 – D) x T . To find the duty cycle in DCM, we s designer can control when determining the

can first find the fall time that is required to 3 Topic operating mode of the converter at a given load discharge the inductor by taking the peak current current are the switching frequency and the value during the ON time and dividing it by the current’s of the inductance. If the converter size and overall rate of decay during the OFF time: switching loss determine the switching frequency, m ILO()N the inductor value remains as the only design tfall = ××DTs (6) −mI parameter available to determine whether the LO()FF converter will operate in CCM or DCM. To find The negative sign in the denominator of tfall is the value of inductance required to guarantee due to the OFF-time slope being a negative value. operation in the selected mode, we can set the If tfall is less than (1 – D) x Ts, the converter is CCM and DCM duty cycles to be equal, and solve operating in DCM. That is, if the time to discharge for L: the energy in the inductor to zero is less than the VT× OFF time of the switch, the converter is operating L =−IN s ××DD()1 (11) 2I CCMCCM in DCM. Under this condition, the fall-time duty OUTD_ CM cycle, Ddisch, is Note that the requirement for inductance is at t V D ==fall IN × D . (7) a maximum at the 50% duty cycle and decreases disch T VV− DCM at the duty-cycle extremes. This highlights the s OUT IN need to check all aspects of operation when In steady-state operation, the average output component values are being determined. current is equal to the average diode current. This average output current is equal to the peak current, averaged over the switching period: VT× I = IN s ××DD OUT 2L DCMdisch (8) VT× V = IN sI××N D2 2L VV− DCM OUT IN

†This approximation assumes that voltage drops are due to the average current, whereas the actual drops are due to the peak current. The approximation loses accuracy if the voltage drops due to the loss elements are a significant percentage of the input voltage.

3-5 For simplicity, further equations will omit the loop in four configurations: CCM and DCM loss terms. Fig. 6 compares waveforms obtained operation with voltage-mode control (VMC), and from a CCM and a DCM boost converter (both CCM and DCM operation with peak-current-mode designed from the schematic in Fig. 1 and simulated control (peak-CMC). in SIMPLIS™). Arbitrarily selecting CCM operation at down to a 100-mA load results in A. VMC in CCM Small-Signal Analysis L = 22 µH. From Equation (11), L = 1.0 µH is Fig. 7 depicts how the error- output, selected to allow DCM operation of the other VC, controls the converter’s output voltage, VOUT. converter over a wide duty-cycle range. Understanding this VMC transfer is necessary to The RMS and average values of the currents ensure that the network is capable of controlling may be calculated and compared with the technique the output voltage over the entire range of outlined in Appendix A. A waveform operation. has inserted values from the simulation in the figure. VIN In all three paths, the peak and RMS currents are larger in the DCM converter. This + VC D V implies that for equivalent resistive VREF KEA Fm Gvd(s) OUT components, power losses will be higher and – Tv(s)

Topic 3 Topic turn-off switching and recovery losses will be higher. For the diode, the average current is KFB the same in both modes; therefore the conduction losses will be the same. Fig. 7. Simplified transfer-function diagram of VMC. In Sections III.A through III.C, we develop a small-signal model to analyze the feedback

(A) 6 DCM CCM DCM CCM IInductor I RMS = RMS = Inductor 3A 2.1 A 4

Current

2

Inductor 0

DCM (A) 6 CCM DCM CCM IDiode I AVG= AVG= Diode 1A 1A 4

Current 2

0

Diode

(A) 6 DCM CCM DCM CCM ISwitch ISwitch RMS = RMS = 2.2 A 1.5 A 4

Current 2

Switch 0 0 2 46 Time (µs) Fig. 6. Comparison of waveforms from CCM and DCM converters.

SIMPLIS is a trademark of Simplis Technologies, Inc.

3-6 The modulator gain, Fm, is the transfer function that generates the duty cycle based Control Voltage + PWM on the VC control voltage. That is, for a Oscillator Sawtooth – given change in VC, the duty cycle will change by an amount proportional to the modulator gain. For VMC, Fm is simply Oscillator 1 Sawtooth Fm = , (12) mT× Vramp ma as where ma is the slope of a sawtooth ramp Control waveform (Fig. 8). The controller’s internal VC Voltage clock oscillator usually generates this 0 sawtooth waveform. As a side note, the Resulting PWM TPS40210 is configurable so that ma is fixed or is a function of the input voltage. This Fig. 8. Pulse-width modulation (PWM). provides an option for including voltage feedforward to the transfer function. The impact of increasing the slope, m , is a decreasing Note that if the output are of mixed a types (i.e., aluminum electrolytic and ceramic),

Fm, the result of which is described later in this 3 Topic section. their impedances may be included in this parallel The small-signal duty-cycle-to-output-voltage combination, allowing characterization of transfer function, G (s), is determined from converters with a variety of mixed component vd_CCM types. the boost circuit’s impedances (Fig. 9). ZON is the impedance of the inductor as a function of The derivation of Gvd_CCM(s) is developed in detail in Reference [1]. Without re-creating that frequency, plus the RDS(ON) of the MOSFET switch and any other series impedances: work here, it is sufficient to give that function for CCM in terms of circuit impedances as ZZON =+LDRRSO()NI+ SENSE (13) ZM× 2 1− ON CCM ZOFF is the parallel combination of the output 2 Rload Gsvd _ CCM ()= VMIN ×× (15) capacitors and the load resistance: CCM ZM× 2 1+ ON CCM ZRCl× oad Z = (14) ZOFF OFF ZR+ Cload

ZON ZOFF

L R Input L Output Voltage Voltage

RDS(ON) COUT COUT Load

RESR RESR

RISENSE

Fig. 9. Circuit highlighting ON- and OFF-time impedances.

3-7 where MCCM is the conversion 50 180 Gain L-C Double Pole ratio in CCM, 40 135

) V 1 30 18 V OUT IN 12 VIN 90 MCCM ==. (16) ) VD1− 20 45

IN dB ( 9VIN

Degrees

( in 10 Two Zeros in 0 It is in Gvd(s) that the RHP zero Close Proximity Ga 0 –45 comes into play. As the numerator Phase

of Equation (15) indicates, the zero –10 18 VIN –90 Phase 12 VIN –20 is a function of the converter’s ON 9VIN –135 impedance (determined from the –30 –180 inductor value, the frequency, and 10 100 1k 10 k 100 k1M parasitic imped­ances) load, and Frequency(Hz) duty cycle. In Fig. 10, the span of Fig. 10. Control-to-output Bode plot for VMC CCM movement of the RHP zero is from operation at 1-A load. about 23 kHz to 96 kHz over the 50 180 input-voltage range. At lighter load Gain (Fig. 11), the RHP zero moves to a 40 135

) 30 much higher frequency, likely 18 VIN 12 VIN 90

)

Topic 3 Topic beyond any frequency of interest. 20 45

dB

( 9VIN

Degrees

Note again that the ESR-zero ( in 10 0

frequency of the output capacitor Ga 0 –45 is just over 11 kHz. The interaction Phase –10 18 VIN –90 Phase of the two zeros (the RHP zero 12 VIN –20 –135 from the converter and the LHP 9VIN –30 –180 zero from the capacitor's ESR) 10 100 1k 10 k 100 k1M tends to flatten the phase response Frequency(Hz) while providing a double-zero Fig. 11. Control-to-output Bode plot for VMC CCM correction to the L-C filter double operation at 150-mA load. pole. Notice also that the lower gain occurs at higher input voltages (smaller MCCM, the load resistance), scaled by the CCM duty Equation (16)). This is in contrast to a buck- cycle. derived converter where the gain increases with With VMC used in CCM, the three dominant increasing input voltage. In this example, adding characteristics of the curves are observable (see input-voltage feedforward increases the gain Fig. 10): spread for the 9- to 18-V input-voltage change • A relatively low-frequency double pole due to from –5.5 dB (see Figs. 10 and 11) to –11.5 dB. the inductor and output capacitor This further decrease in gain with increasing input • An RHP zero due to the inductor, the load, and voltage is due to the decrease in Fm with input the duty cycle voltage (see Equation (12)). • An LHP zero due to the output capacitor and Putting the blocks together yields the control- ESR to-output transfer function of the converter: The complexities in compen­sating this path Gs()=×FG()s (17) vc mvd are numerous (Figs. 10 and 11): The RHP zero The dominant pole in CCM is generated from shifts in frequency with varying duty cycle and the ratio of the network impedance when the load, and the gain changes inversely with input switch is on (basically, the inductor impedance) to voltage. The zero occurs with a control-to-output the output-network impedance when the switch is gain above 0 dB, and the phase shifts dramatically off (when the output capacitance is in parallel with

3-8 in the 1- to 5-kHz range. The output capacitor’s The control-to-output transfer characteristic in ESR provides an additional phase boost (at 11 kHz DCM is in these plots), lessening the available margin. To 21V M − compensate this control loop, a feedback network Gs()= OUT × DCM vd _ DCM D 21M − must be designed so that the closed-loop response DCM sD× has a crossover frequency in the low 100s of hertz, 1− (19) perhaps an octive below the minimum worst-case 2F × s . L-C pole frequency and the dramatic phase shift. ()MR−1 × 1+ DCMload (2MMZ−1) × B. VMC in DCM Small-Signal Analysis DCMC In DCM, the energy stored in the inductor in In DCM, and because of the relatively smaller each switching cycle is equal to the output energy inductor, the RHP-zero frequency extends to and is a function of the input voltage, the beyond the switching frequency with negligible inductance, and the output power. Equating the inpact at typical loop crossover frequencies [2]. energy over a switching cycle gives us the See Figs. 12 and 13. conversion ratio: The low-frequency pole is a function of the 2 output capacitance and load resistance, and is ()VVOUTd+ ××DTs 11++2× lower in frequency than in the CCM example. ILOUT × MDCM = (18) The gain change over an input voltage range is 3 Topic 2 +4.7 dB. This is because Gvd(s) now increases

50 180 Gain Rload-C Single Pole 40 135

) 30 18 VIN 90

) 20 12 VIN 45

dB

(

9VIN Degrees

in 10 0 (

Ga 0 –45 Phase

–10 18 VIN ESR Zero –90 Phase 12 VIN –20 9VIN –135 –30 –180 10 100 1k 10 k 100 k1M Frequency(Hz) Fig. 12. Control-to-output Bode plot for VMC DCM operation at 1-A load.

50 180 18 V 40 IN 135

Gain ) 30 Phase 18 V 90 ) IN 20 12 VIN 12 VIN 45

dB ( 9V

IN Degrees

(

in 10 0 9VIN Ga 0 –45

–10 –90 Phase –20 –135 –30 –180 10 100 1k 10 k 100 k1M Frequency(Hz) Fig. 13. Control-to-output Bode plot for VMC DCM operation at 150-mA load.

3-9 with increasing VIN. Adding voltage feedforward there is no output information in the current signal reduces Fm with increasing input voltage and in DCM. reduces the gain variation to –1.3 dB. R 1+ load To compensate this converter, a network with 2 2ZC Gsid _ CCM ()= 2IMOUTC××CM , (22) a zero at a few hundred hertz and a pole at about ZM× 2 10 kHz will yield a stable system with a crossover 1+ ON CCM ZOFF frequency in the low 10s of kilohertz. where MCCM is defined by Equation (16). C. Peak-Current-Mode Control As shown in Fig. 15, the inner current loop is Incorporating peak-CMC is a matter of Ts()=×FA××RG(×s) Hs(), (23) monitoring the switch current during the ON time ImCS ISENSE id e of the switch and summing a current signal into ‡ where He(s) is the sampling gain [3]. The sense the modulator (see Fig. 14). The modulator gain resistor, RISENSE, used in this example is 50 mΩ, then becomes and the current-sense gain (ACS) of the TPS40210 1 is about 6. Fm = , (20) mT× ns Error Control Voltage Switch + where mn is a slope proportional to the inductor’s Current Amplifier current slope during the ON time of the switch, + Topic 3 Topic – PWM ACS mR= m,××A (21) – nILO()NISENSECS RISENSE and ACS is the gain of the current-sense amplifier. Notice that the current slope is a function of the Control input voltage (Equation (1)), and that a shift in Voltage gain will occur from that changing slope. The effect is similar to that of voltage feedforward in Switch the VMC converter. Current mn The current feedback path has a transfer function in CCM, but not in DCM. This is because Resulting PWM

Ts Fig. 14 Current Mode PWM.

VIN VIN

+ VC + D VREF KEA Fm Gvd(s) VOUT – –

TI(s) ARCS  ISENSE He(s)

Gid(s)

Tv(s)

KFB

Fig. 15. Simplified block diagram of CMC converter.

‡The sampling gain is a modeling tool that allows the zero-order sample-and-hold effects of peak-CMC to be included in this simple frequency-domain model.

3-10 50 180 40 135 Gain 18 VIN ) 30 90

) 20 45

dB ( 12 VIN 9V Degrees

IN (

in 10 0

Ga 0 –45 Phase

–10 18 VIN –90 Phase 12 VIN –20 9VIN –135 –30 –180 10 100 1k 10 k 100 k1M Frequency(Hz) Fig. 16. Control-to-output Bode plot for CMC CCM operation at 1-A load. The control-to-output transfer function, Switch Error Control Voltage including the inner current loop, is Current Amplifier + FG× ()s + mvd −×std – PWM Gsvc ()= ×e , (24) ACS

1+ Ts() – 3 Topic I + Composite –s×t + where e d is the delay time from the RISENSE Ramp PWM comparator input to the transition of Oscillator the converter switch node. This delay Sawtooth Composite introduces a phase lag at higher Control Ramp frequencies. Voltage m+m The inner current loop tends to reduce a n the overall gain of the system, in this example by about 13 dB. The voltage Oscillator ma feedforward of the current feedback reduces Sawtooth the gain variation over the input-voltage range to 4.2 dB. The slope above resonance Switch mn is reduced to –20 dB/decade, allowing a Current simple type II compensation to yield a Resulting closed-loop crossover frequency in the PWM middle kilohertz range. A crossover frequency any higher could cause gain- Ts margin instability because of the higher- Fig. 17 Current-mode PWM with slope compensation. frequency zero. Notice in Fig. 16 that the 12-V response curve Slope Compensation has high peaking at high frequencies. This peaking The addition of an external ramp to the current- occurs at near 50% duty cycle at half the switching feedback signal reduces the effect of subharmonic frequency. This peaking is due to the sample-and- oscillation (see Fig. 17). An artificial ramp, ma, is hold effect of the peak-CMC and the inherent summed with the signal proportional to the current- tendency towards subharmonic oscillation. feedback signal, mn, creating a composite signal that is used to determine the modulator gain: 1 F = (25) m ()mm+ ×T ans

3-11 Adding slope compensation helps control the Current-Mode DCM Operation high-frequency peak at the expense of lower In DCM, changes in control-to-output gain overall control-to-output gain. In Fig. 18, a slight depends on changes in the modulator gain, Fm. amount of slope compensation is included, There is no AC contribution (Gid(s)) in DCM resulting in reduced peaking at the duty cycle because the energy builds from zero in each extremes; however, there is insufficient slope switching cycle; i.e., there is no contribution from compensation to remove the peaking at wide (low the output to the feedback signal within the current input voltage) duty cycle. signal. In Figs. 20 and 21, the current-sense resistor In Fig. 19, the load is reduced to 150 mA, is reduced from 50 mΩ to 17 mΩ to limit the peak resulting in a minor shift in the low-frequency voltage at the sense pin and to keep power pole and a dramatic shift in the RHP zero to higher dissipation low. frequency. A pole at about 11 kHz is necessary to With essentially only a gain shift, the curves compensate the ESR zero. The crossover frequency follow the poles and zeros of the VMC converters should be limited to less than 10 kHz to prevent operating in DCM. The inclusion of slope the peaking at high frequency from affecting compensation, with or without voltage feed­ overall stability. forward, has only a minor effect on this signal path

Topic 3 Topic 50 180 40 135

) 30 Gain 18 VIN 90

) 20 45

dB ( 9VIN 12 VIN

Degrees

(

in 10 0

Ga 0 –45 Phase

–10 18 VIN –90 Phase 12 VIN –20 9VIN –135 –30 –180 10 100 1k 10 k 100 k1M Frequency(Hz) Fig. 18. Control-to-output Bode plot for CMC CCM operation at 1-A load, including slope compensation.

50 180

40 Gain 135

) 30 90 ) Phase 20 18 VIN 45 dB 18 VIN

(

9VIN 12 V 12 V Degrees IN IN ( in 10 0 9VIN Ga 0 –45

–10 –90 Phase –20 –135 –30 –180 10 100 1k 10 k 100 k1M Frequency(Hz) Fig. 19. Control-to-output Bode plot for CMC CCM operation at 150-mA load, including slope compensation.

3-12 50 180 40 135

Gain ) 30 90

) 18 V 20 IN 45

dB

(

12 VIN Degrees

(

in 10 0 9VIN

Ga 0 –45 Phase

–10 18 VIN –90 Phase 12 VIN –20 9VIN –135 –30 –180 10 100 1k 10 k 100 k1M Frequency(Hz) Fig. 20. Control-to-output Bode plot for CMC DCM operation at 1-A load.

50 180 Gain 40 135 18 VIN Phase ) 30 90 18 VIN

) 20 12 VIN 45 Topic 3 Topic

dB ( 12 VIN 9VIN 9V Degrees IN ( in 10 0

Ga 0 –45

–10 –90 Phase –20 –135 –30 –180 10 100 1k 10 k 100 k1M Frequency(Hz) Fig. 21. Control Control-to-output Bode plot for CMC DCM operation at 150-mA load. because of the relatively large current signal. The the converter, including transients. The winding ESR zero dominates the curves in the areas of resistance should be low enough to limit power interest for loop crossover. dissipation and avoid overheating. The structure of the inductor should yield low interwinding D. Component Selection and Design capacitance to limit ringing and EMI. A closed- Considerations field magnetic structure also reduces radiated Inductor Selection EMI. The inductance required by a converter In a DCM design, high ripple current can operating in DCM at heavy load will be much create high core losses. High losses increase lower than the inductance of a converter operating temperature, which in turn can lead to a loss of in CCM under the same load condition. This inductance. Therefore a core material with low means the inductor in a DCM converter will likely permeability and low core losses at the switching have lower winding resistance than the inductor in frequency, such as gapped ferrite, powdered iron, a CCM converter. Although the RMS current is or MPP should be chosen. The vendor can help higher in a DCM converter, the winding losses in calculate the core losses for a particular­ design. the inductor may be equivalent to or less than The conduction losses in the inductor are 2 those of the CCM counterpart. PdLc__ond = IRLRMS × L. (26) The peak-current rating of the inductor selected should be well above the expected peak current of

3-13 MOSFET Selection voltage is high, a fast-recovery diode is an alternate MOSFET selection focuses primarily on possibility. For converters operating in CCM, a breakdown voltage and power dissipation. A diode with a “soft” recovery characteristic will MOSFET with a breakdown voltage of about 1.5 minimize EMI and the need for a snubber. This times the output voltage is preferable. Once the characteristic is not necessary in a DCM application converter is running, the designer should ensure because there is no current flowing in the diode that all drain voltage spikes are well below this when the switch is turned on. value. A simple approximation of conduction losses Power dissipation in the switch is composed of in the diode is three elements—conduction loss, switching loss, PdRECT _ cond =×IVOUT d. (30) and gate loss. The conduction losses in the MOSFET are approximated as Switching losses associated with a Schottky 2 rectifier are dissipated by the switch. In this case, PdSW__cond = IRSW RMSD× SO()N . (27) the results of Equation (31) are added to those of The switching losses are approximated as shown Equation (28). 2 by Equation (28) below are comprised of the losses 1 ()VVOUT + d incurred in driving the node capacitance (MOSFET PdSW _SCHR= ××C ECT , (31) 22Ts Coss and the rectifier capacitance or Qrr) and the

Topic 3 Topic device itself. The gate losses are approximated as and for a fast-recovery device, as shown by

PdSW_ gate =×QVGATE GATE × Fs. (29) VtOUT ××rr IOFFSET PdRECT _ Qrr = . (32) 2Ts An RDS(ON) should be selected for the MOSFET so that the conduction power dissipation is limited Synchronous Rectification to 1% or so of the total output power. With this If the R is low and the output current is selection, the maximum allowable drain current of DS(ON) high, a MOSFET may replace the diode. The the MOSFET will be much greater than what will benefits of the increased efficiency must be occur in the application. A MOSFET with low weighed against the additional complexity of capacitance will minimize switching losses. A driving the MOSFET. Using a MOSFET allows a good rule of thumb is to select a MOSFET with “discontinuous” design to be run in CCM. If the switching losses equal to conduction losses with gate-driver timing allows the synchronous the converter operating at maximum load. rectifier’s MOSFET to be on for the full (1 – D) Obviously, selecting a MOSFET to meet these interval, then when the inductor current decays to criteria is a somewhat iterative endeavor. zero during the OFF period, it then reverses and Diode Rectifier Selection conducts energy back into the input. However, The rectifier must be capable of handling the during such CCM operation, power dissipation capacitor’s peak input current and of dissipating increases significantly due to the recirculation of the rectifier’s average power—the rectifier voltage energy. drop times the load current. The voltage breakdown Selection of an Output Capacitor of the device must be greater than the output To provide relatively smooth DC voltage to voltage plus some margin. The typical choice for a the load, the output capacitor in a boost converter rectifier in applications with low output voltage is must absorb pulsating ripple current. For this to a low-capacitance . If the output occur, the impedance of the capacitor at the

1  2 IOUT QRGD × GATTE  PdSW_ switch =+××CVOSSO()UT VVd ++()OUT Vd ××  (28) 21Ts  − D VVGATE − th 

3-14 switching frequency and the ESR of the capacitor DC L Switching must be low enough to keep the ripple voltage D Current Current Input Output across the capacitor very small as compared to the average output voltage (see Fig. 22). SW COUT Load The output capacitor should be chosen for its holdup (if necessary) and filtering performance and, more important, its RMS ripple-current rating. The power dissipation in the capacitor can be Fig. 22. Capacitor current flow. significant if the ESR is high in a high-ripple- current DCM converter. To find the power Current Limiting and Inrush Current dissipated in the capacitor, first find the ripple An inspection of the schematic for a simple current into the capacitor and the capacitor’s ESR. boost converter makes it clear that upon Asumming a steady-state load current, the voltage instantaneous start-up there will be a large surge drop created by the capacitance is current charging the output capacitor. The peak of ID××T the current is dependent on the rate of rise of the V = OUT s . (33) input voltage, the inductance, the capacitance, and RIPPLEC_ AP C OUT the circuit resistance. In practice, inductor The pead-to-peak voltage drop created by the ESR saturation is not generally a problem when the sourcing converter has a soft start of some sort, is 3 Topic limiting the rate of rise of the voltage. For those VR=+×∆()II. (34) RIPPLEE_(SR PP) ESROFFSET L applications where a switch is in series with the The capacitor ripple current is shown by input of the boost converter, an inrush-limiting Equation (35) below and the power dissipation in circuit such as an NTC or a resistor the capacitor is then shunted by a switch is in series with the inductor. 2 Alternatively, a rugged diode placed in parallel PdCAPC= IRAP _ RMSE× SR . (36) with the series connection of the inductor and diode shunts most of the inrush current from the inductor. Winding Controlling Switch-Node Capacitance Rectifier Capacitance Ringing Parasitic components, L R Input L Output such as inductor shunt Voltage Voltage capacitance and lead- inductance in the MOSFET and diode (see COUT COUT Package Snubber Fig. 23), can cause ringing and Lead RDS(ON) Resistor at the switch node in Inductance Load RESR RESR excess of 100 MHz. Snubber Damage to the MOSFET Capacitor may occur if the voltage

RISENSE spikes created by this ringing exceed the MOSFET’s voltage rating. Fig. 23. Boost power stage with parasitic elements.

2 22tfall ()∆ItLO()FF × fall IICAPR_ MS =+OUT ××D ()IIOFFSET −+OUT ()IIOFFSETO− UT ×∆IItLO()FF × fall + (35) Ts 3

3-15 In addition to more power loss, conducted and parasitic energy. The snubber capacitor controls radiated EMI are by-products of this ringing. the maximum peak voltage at the switch node: Good PCB layout practices minimize some of ItCP()Kr× this ringing. The physical trace loop areas of the C = (37) V switch node must be as small as possible to max minimize stray inductance. Tying the source of the The snubber resistor ensures that the capacitor MOSFET at the return path of the output capacitor is discharged when the switch is turned on. can help, or a high-frequency capacitor can be tON _min connected from the cathode of the diode directly R = (38) to the source of the MOSFET. 3C An additional technique is to place a small The power dissipation in the resistor will be (2- to 10-Ω) resistor in series with the gate of the MOSFET. This will serve to slow the turn-on and approximately turn-off of the MOSFET and will further reduce 1 2 Pd = CV××Fs. (39) the ringing. However, a resistor that is too large 2 will increase switching times and power dissipation. Reference [4] contains a technique for finding Another technique is to add a series R-C the R and C values based on bench measurements snubber across the MOSFET to dampen the of the ringing. Topic 3 Topic

3-16 IV. De s i g n Ex am p l e s With a 12-V input, 24-V output, and 1-A load, Two CMC application circuits utilizing the the power dissipation of the significant components TPS40210 demonstrate a few of the principles highlights the difference in power loss between outlined in this topic. One converter operates in CCM and DCM. The losses in the MOSFET and CCM with a 22-µH inductor (see Fig. 24). The inductor comprise most of the additional loss in other operates in DCM and has a 1.0-µH inductor. the DCM converter, with a small amount of Components other than those in the feedback loop increased switching loss in the rectifier. The are the same and were selected by using the increased losses bring the full load efficiency guidelines in the previous section. See Table 1 for down from 93% for the CCM converter to 88% for a comparison of the test results for both converters. the DCM converter. A detailed design example for the CCM converter can be found in Appendix B.

VIN

R1 TPS40210 C7 L1 1 10 V 3 Topic RC VDD OUT C6 2 9 SS BP D1 R6 C3 3 8 Q1 DIS/EN GDRV C2 R2 R4 C1 4 7 R3 COMP ISNS C8 C4 5 6 R7 R8 FB GND C5 R5

Fig. 24. Schematic of example CCM boost converter.

Ta b l e 1. Co m pa r i s o n o f CCM a n d DCM Po w e r Lo s s e s

IPK IRMS IAVG Conduction AC Loss Total Device Type (A) (A) (A) Loss (W) (W) Loss (W) CCM MOSFET Switch 0.07 Ω 2.3 1.5 0.16 0.60 Sense Resistor 0.05 Ω 1.5 0.11 Inductor 22 µH, 79 mΩ 2.1 0.35 0.02

Rectifier Vf = 0.5 V, C = 100 pF 2.3 1 0.50 0.01 Output Capacitor ESR = 140 mΩ 1 0.15 1.90 DCM MOSFET Switch 0.07 Ω 6 2.2 0.34 0.96 Sense Resistor 0.017 Ω 2.2 0.08 Inductor 1 µH, 6 mΩ 3 0.06 0.80

Rectifier Vf = 0.5 V, C = 100 pF 6 1 0.50 0.01 Output Capacitor ESR = 140 mΩ 1.7 0.40 3.15

3-17 Fig. 25 shows the control- 180 to-output gain and phase plot 90 for the CCM converter to Phase 0 Measured Phase

compensate the feedback loop, (s)

vc (Degrees) –90 a pole was selected at about G Calculated Phase 200 Hz, and a zero at about –180 11 kHz. The error-amplifier 40 Measured Gain compensation network has a 20 Gain 0

(dB) zero at about 200 Hz and a (s) –20 vc Calculated Gain pole at about 10 kHz, resulting G –40 in a response of a straight line. –60

The crossover frequency is 180 Measured Phase about 6 kHz, with a phase 90

margin of 75°. Phase 0 Calculated Phase

Compensation of the DCM (Degrees)

Loop –90 version of this converter is achieved in a similar fashion –180 (see Fig. 26). The poles and 60 40 Measured Gain

Topic 3 Topic zeros are selected at the same 20

Gain

location as for the CCM (dB) 0 Calculated Gain

Loop –20 converter, but this time the –40 gain is increased by about –60 100 1k 10 k 100 k 10 dB to compensate for the Frequency (Hz) lower control-to-output gain. Fig. 25. CCM loop plots. The result is a closed-loop plot similar to that of the CCM converter but without the 0 phase lag at higher frequency. Measured Phase

Phase Clearly, this loop may be –100 (s) Calculated Phase

vc

(Degrees)

optimized further. G

Step 11 in Appendix B –200 details how to find the values 30 Measured Gain of R5, C4 and C5. With 20 Ω Gain 10

(dB)

R5 = 150 k , ­C4 = 5600 pF, (s) 0

vc

G Calculated Gain and C5 = 180 pF, the closed- –10 loop crossover frequency is –20 again about 6 kHz, with a 180 Measured Phase phase margin of 75°. In this 90

Phase Calculated Phase case, the gain may be pushed 0

out further since there is little (Degrees)

Loop –90 risk of running out of phase –180 margin at higher frequency. 60 40 Measured Gain 20

Gain 0 (dB) Calculated Gain –20

Loop –40 –60 100 1k 10 k 100 k Frequency (Hz) Fig. 26. DCM loop plots.

3-18 V. Co n c l u s i o n VI. Re f e r e n c e s

There are a variety of ways to design a boost [1] R.W. Erickson and D. Maksimovic, converter and a variety of control techniques to Fundamentals of Power Electronics, 2nd ed. stabilize it. The choice of operating in CCM or New York: Springer Science + Business Media, DCM has a direct impact on power-stage efficiency Inc., 2001. ISBN 0-7923-7270-0 and loop crossover frequency. Operating in DCM generally will result in a higher loop bandwidth at [2] J. Sun, D.M. Mitchell, M. Greuel, P.T. Krein, the expense of lower efficiency. The DCM R.M. Bass, “Average Models for PWM converter will likely be smaller due to the smaller Converters in Discontinuous Conduction inductor, but the demands on the output capacitor’s Mode,” HFPC Proceedings, pp. 61-72, ability to handle ripple current are higher. November, 1998. Employing peak-CMC allows some correction [3] A.R. Brown and R.D. Middlebrook, “Sampled- of the double-pole rolloff found in VMC. Further, data modeling of switching regulators,” IEEE including slope compensation minimizes the Power Electrons Specialists Conf., June/July, possibility for subharmonic oscillation during 1981. CCM operation. Operating a DCM converter with CMC has the same effect as operating it with [4] J. Falin, “Minimizing Ringing at the Switch VMC—increased loop bandwidth with better Node of a Boost Converter,” Application phase margin at the expense of higher Report, TI Literature No. SLVA255. 3 Topic power dissipation. [5] “4.5-V to 52-V Input Current Mode Boost Controller,” TPS40210 Datasheet, TI Literature No. SLUS772. [6] B.T. Lynch, “Feedback in the Fast Lane— Modeling Current-Mode Control in High- Frequency Converters,” , Power Supply Design Seminar, SEM1700, 2006-2007.

3-19 Ap p e n d i x A. Ca l c u l at i o n o f RMS a n d Av e r a g e Va l u e s f o r Co mm o n Sw i t c h i n g Wav e f o r m s

and IL tT1 II=×s . IPK AVGPK 2 IOFFSET In the rectifier, similar calculations hold true (see Fig. 28). t1

Ts In CCM, Fig. 27. Switch current in boost converter.  ∆I2  t2 II=+2 II××∆ + L RMSO FFSET OFFSET L   3  Ts

IL and I  ∆I  t2 PK II=+L × . I AVGO FFSET  OFFSET  2  Ts

Topic 3 Topic In DCM, t2 tT2 s Ts II=× RMSPK 3 Fig. 28. Rectifier switch current. and

One of the most common waveforms in a tT2 s IIAVGP=×K . switching power supply is the stepped sawtooth. 2 Fig. 27 shows the switch current in the boost converter. Pedestal IOFFSET is the level from which the IL(ON) IL(OFF) current begins to rise at the start of a switching cycle. The level corresponds to the average input current, less one-half the peak current value: Fig. 29. Inductor current. I ||∆I I = out − L OFFSET 12− D The average and RMS values of the inductor The RMS switch current is current are calculated from the switch and rectifier  ∆I2  t1 currents. II=+2 II××∆ + L . RMSO FFSET OFFSET L   ∆I  3 Ts LO()N   ILA_ VG =+ IIOFFSET  + RECT _ AVG  2  The average value is  ∆I  t1 22 L × IILR__MS =+SW RMSRI ECTR_ MS IIAVGO=+ FFSET  .  2  Ts For CCM cases, an alternative is In the case of DCM operation, IOFFSET goes to I zero, and the calculations simplify to I = OUT . LA_ VG 1− D tT1 II=× s RMSPK 3

3-20 Ap p e n d i x B. De tai l e d De s i g n Ex am p l e o f CCM Co n v e r t e r

For this example, the boost converter has a 9- The peak-to-peak ripple current (∆IL in to 18-V input and 24-V output and is operating in Appendix A) is found from Equation (1) times the CCM with CMC (see Fig. 30). The output current ON time of the switch: is 1 A, and the controller is a TPS40210 operating V ∆I = IN ××DT at about 700 kHz. With the operating mode and LO()N L s control technique established, the remaining 12 design tasks are straightforward. = ××05..1430 µsA� ..39 22 µH 1. The value of L is calculated to achieve CCM The pedestal of the current is approximated by operation over the operating range of the input and I ∆I load. The ideal duty cycle from Equation (4), is I = out − L OFFSET 12− D V 12 D =−11IN =− = 05.. 1 03. 9 CCM()ideal V 24 = − � 18. A. OUT 10− .5 2 Desiring CCM operation with at least a 10% load, The peak-to-peak current is we can calculate the value of L using ∆ILO()N Equation (11): II=+ � 22. A, SW()PK OFFSET 2 3 Topic VTIN × s L =−××DDCCMC()1 CM 2IOUTD_ CM and the RMS current is 12×14. 3 µs  ∆I2  t1 II=+2 II××∆ + L =−××05.(10.5) � 22 µH RMSO FFSET OFFSET L  20× .1  3  Ts 2. Next we select components for the switch,  0.152  rectifier, inductor, sense resistor and the output =+36..1193×0. 9 + ×05..� 15 A.  3  capacitor. Given the input and output parameters, we can then determine approximate current in For conduction losses to be (arbitrarily) 1% of each component. the total losses, a P ×00. 1 24×00. 1 ==out Ω RDS()ON 2 � 100 m . IRMS 22. 5

VIN

R1 TPS40210 C7 L1 1 10 V RC VDD OUT C6 2 9 SS BP D1 R6 C3 3 8 Q1 DIS/EN GDRV C2 R2 R4 C1 4 7 R3 COMP ISNS C8 C4 5 6 R7 R8 FB GND C5 R5

Fig. 30. Schematic for CCM converter.

3-21 The MOSFET should have a maximum voltage For a 2% peak-to-peak ripple voltage, a capacitor rating of at least 24 V. For this converter, an with an ESR of less than 218 mΩ should be used. Si4446DY has a maximum RDS(ON) of 72 mΩ In this example, a Panasonic 100-µF FK series with a typical value of 43 mΩ, and a breakdown capacitor is used. The ESR for this capacitor is voltage rating of 40 V. measured to be about 140 mΩ. For the rectifier, the average rectifier current Using Equation (35), the RMS ripple current will be the same as the load current: 1 A. An in the capacitor is about 1 A. The rating of the MBRS340 has 3-A capability and a breakdown capacitor is just under 400 mA at 105°C. Although voltage of 40 V. dissipation is low, about 140 mW, a more robust The inductor is a Pulse P1169.273NL. This solution should be found for a production device has a 20-µH inductance at 2.4 A and 27-µH converter. inductance at 0 A. To suppress the tendency towards subharmonic 3. With the major components selected, calculate oscillation, the current-sense resistor is selected so the CCM duty cycle, DCCM, from Equation (5) as that the slope of the current signal (at the input of shown at bottom of this page, this time including the PWM) is half that of the compensating ramp. losses. Refer to the TSP40210 datasheet [4] for further Note: If the converter was operating in DCM, this detail. is where the DCM duty cycle would be calculated

Topic 3 Topic The slope of the compensating ramp is the using Equation (10) for use in subsequent peak-to-peak value of the sawtooth waveform calculations. divided by the period of oscillation: 06. m = � 420 V/ms 4. For CCM, peak CMC operation, we calculate a 14.3 µs the slope of the current in the switch during the The sense-resistor value is ON interval. Equation (1) is modified to include the voltage drop across the loss elements of the ma RISENSE = MOSFET and the current-sense resistor: ∆IALO()FF ××CS 2 IOUT 420×1 k VIN − ×()RRISENSE + DS()ON =≈64 mΩ. 1− D mI = 545××16 k × 2 LO()N L 1 A 50-mΩ resistor is used. 12 − ×(.0050+ .007) The remaining component in the power stage = 10− .52 � 529 Ams is the output capacitor. From earlier, the peak-to- 22 µH

peak ripple current was determined to be 2.2 A.

VI++×()RR   IN DS()ON ISENSE   2  ++VI×()RR+  −+4IR××()RV()+ V    IN OUTDSO()NISENSE  OUT DS()ON ISENSE OUT d  DCCM =−1 2(VVOUT + d )

12 ++10×(.07 00.)5   2  ++[(12 10××..07 +−0054)] 10×(.07 + 00. 5))(× 24 + 05.) D =−1 � 52% CCM 22×(.40+ 5)

3-22 5. From Equation (25), calculate the modulator 7. To find Gvd(s), the duty-cycle to output-voltage gain, Fm: transfer function, the frequency dependent § 1 parameters, ZON and ZOFF must first be calculated. F = m ()mm+ ×T Solving Equation (15): ans 2 1 ZMON × CCM = =12. 1− 2 Rload (.417000 + 529000××6005).×143 µs Gsvd _ CCM ()= VMIN ×× CCM ZM× 2 1+ ON CCM Notice that mn from Equation (21) is the Z inductor-current ON slope times the sense resistor OFF Z × 43. 4 amplified by the current-sense amplifier gain, 1− ON ACS, of 6. =12× 4.334× 24 Z × 43. 4 1+ ON 6. The conversion ratio from Equation (16) is ZOFF 1 1 MCCM = = � 21.. 8. The inner current-loop transfer function, TI(s), 1− D 10− .52 is determined from Equation (23) as shown at the bottom of this page: 180

135 3 Topic 90 9. We can use Equation (24)

Phase 45 to plot the control-to-output

(s)

vc (Degrees) 0 Measured Phase Phase Rolloff G transfer function, Gvc(s) (see –45 Fig. 31): –90 –135 Calculated Phase FGmv× d ()s −st× d –180 Gsvc ()= ×e 1+ TsI () 40 Measured Gain The plots in Fig. 31 indicate 20 Desired Crossover Frequency the calculated and measured

Gain 0 control-to-output gain and Calculated Gain

(dB)

(s)

vc –20 phase of the control-to-output G transfer function of the –40 evaluation circuit as a function

–60 of frequency. 100 1k 10 k 100 k Frequency (Hz) Fig. 31 Control-to-output frequency-response curves of CCM converter.

R 1+ load 2 2ZC TsIm()= FI××2 OUT MCCM × ××RAISENSE CS × Hse () ZM× 2 1+ ON CCM ZOFF 24 1+ 2Z 21πf × .43 µ =12..××21××434 C ××00. 56× Z × 43. 4 21πµf× .43 1+ ON e −1 ZOFF

§ It is left to the reader to calculate the impedances ZON and ZOFF as a function of frequency. Refer to Fig. 9 and Equations (13) and (14).

3-23 VOUT are R6, R5, C4, and C5 (see Fig. 32).

C5 V 24 R68==OUT ××Rk1500 � 49.,9 Ω VREF 07. R6 R5 C4 AVC_ A 9

20 20 – RR56==××10 49.,91 kkΩΩ0 � 138

Error-Amplifier + Output FB Pin (COMP Pin) where AV_CA is the desired gain (9 dB) of the compensated amplifier at the crossover frequency. R8 To set the zero at about 200 Hz, 1 1 C4 == � 58., nF 25ππfR××2 200×138 kΩ Fig. 32. Error amplifier with type II compensation. zE_ A and to set the pole at about 11 kHz, 10. Find the poles and zeros of the circuit. There is 1 C5 = a pole at about 200 Hz, and a zero at about 11 kHz.  1  25πfR× + The error-amplifier compensation network should pC_ A   24πfCpC_ A × then have a zero at about 200 Hz and a pole at  

Topic 3 Topic 1 about 11 kHz. The resulting desired response will = � 100 pF.  1  be a straight line with a –20-dB/decade slope. 2π××11000 138 kΩ +   21π× 10000×58. nF 

11. Referring to the Bode plot, the phase begins to The calculation for R5 assumes that the C4 roll off at about 20 kHz. The loop crossover impedance at the desired crossover frequency is frequency should then be below 10 kHz to give small compared to R5. If not, then the overall gain some margin of safety. The error-amplifier gain is greater than originally desired. Also, if the therefore needs to be about +9 dB to bring the gain impedance of C5 at the crossover frequency is curve to 0 dB in the region of 10 kHz at the near the value of R5, the compensated amplifier nominal 12-V input. gain will be lower than calculated. After some The voltage divider, R6 and R8 in this example, iteration of values, Fig. 33 shows a gain/phase plot determines the output voltage. Arbitrarily setting with R5 = 138 kW, C4 = 5800 pF, and C5 = 100 pF. R8 to 1.5 kW, the remaining components to find The crossover frequency, which is about 6 kHz with a phase margin of 75°, is lower than originally desired. As mentioned, the gain is also lower than originally desired due to the process of selecting R5, C4, and C5. 30 180 The measured and predicted results compare fairly well (see 20 Phase 135

) Fig. 25). The low-frequency differ­ 10 90

) Gain ences are accounted for by the 0 45

dB

( omission of losses in the MCCM

–10 Degrees

( in 0 conversion-ratio calculation on

Ga –20 –45 page 3-23. The high-frequency

–30 –90 Phase differences likely result from the –40 –135 parasitic elements of the output –50 –180 capacitor being different than those 10 100 1k 10 k 100 k1M assumed. Frequency(Hz) Fig. 33. Error-amplifier gain/phase plot.

3-24 Ap p e n d i x C. Gl o s s a ry o f Te r m s

ACS Gain of the current sense Gvd_DCM(s) Voltage-loop duty-cycle to signal path output-voltage transfer function in DCM AV_CA Voltage gain of a compensated error amplifier at the desired Gid(s) Current-loop duty-cycle to crossover frequency current transfer function

Gid_CCM(s) Current-loop duty-cycle to C MOSFET capacitance output-voltage transfer OSS function in CCM COUT Output capacitance CRECT Capacitance of Schottly rectifier He(s) Sampling gain

D Converter duty cycle (generic). IAVG Average current Equal to the ON time of the ICAP_RMS RMS capacitor ripple current switch divided by the total I Capacitor peak current period. C(PK) IL(AVG) Inductor average current DCCM Duty cycle of the converter in 3 Topic CCM IL(RMS) RMS inductor current I The pedestal level from which DDCM Duty cycle of the converter in OFFSET DCM the current begins to rise at the start of a switching cycle. Ddisch Percentage of switching period required to discharge inductor IOUT Output load current energy in DCM IOUT(AVG) Average output current DCCM(ideal) Ideal duty cycle IOUT_DCM Level of average output current at boundary between CCM and DCM operation e–s×td Time delay in the switching path of the converter IPK Peak current IRECT(RMS) Rectifier RMS current I RMS current fz_CA Desired zero frequency of the RMS compensation error amplifier ISW(RMS) RMS switch current fp_CA Desired pole frequency of the compensation error amplifier L Inductor value Fm Modulator gain Fs Converter switching frequency ma Slope of artificial ramp mn Slope of the current-feedback Gvc(s) Control-to-output transfer signal during the ON time of function the switch

Gvd(s) Voltage-loop duty-cycle to MCCM Converter conversion ratio in output-voltage transfer CCM function MDCM Converter conversion ratio in Gvd_CCM(s) Voltage-loop duty-cycle to DCM output-voltage transfer function in CCM

3-25 Ap p e n d i x C. Gl o s s a ry o f Te r m s (Co n t i n u e d )

mIL(ON) Slope of the inductor current tDISCHG Discharge time of sawtooth during ON time of the switch tOFF Turn-OFF time m Slope of the inductor current IL(OFF) tON_min Switch ON time under during OFF time of the switch minimum duty-cycle conditions

Pd Power dissipated TI(s) Inner current-loop transfer function PdCAP Power dissipated by output capacitor tr Desired SW-node rise time PdL_cond Inductor winding power loss Ts Converter switching period PdRECT_cond Rectifier conduction power tfall Time for the inductor current loss to decay to zero in DCM operation PdRECT_FR Rectifier switching power loss PdRECT_Qrr Schottky rectifier switching loss Vd Rectifier diode forward voltage PdSW_cond MOSFET conduction power Vf Rectifier forward voltage loss 3 Topic VGATE MOSFET gate-drive voltage PdSW_switch MOSFET switching power V Converter input voltage loss IN Vmax Maximum voltage across the PdSW_gate MOSFET gate power loss snubber capacitor P Converter output power out VOUT Converter output voltage Vramp Sawtooth waveform peak-to- QGD MOSFET gate-drain charge peak voltage QGATE MOSFET total gate charge VRIPPLE_CAP Voltage ripple across the output capacitor R Switch ON resistance VRIPPLE_ESR(PP) Peak-to-peak voltage ripple DS(ON) across the output capacitor’s RESR Capacitor ESR ESR R MOSFET gate resistance GATE Vth MOSFET gate-threshold RL Inductor winding resistance voltage Rload Converter load resistance RISENSE Current-sense resistor ZC Parallel impedances of output capacitors Rtot Sum of DC loss elements when the switch is on ZON Total impedance of the network when the switch is on s Frequency in radians/s ZOFF Total impedance of the network when the switch is off

3-26