C.I Data Acquisition 33 uses and implementations of previously user defined pins and connectors, release, SCIzzl association information on SCI via WWW http://sunrise.scu.edu/ standardization of the 9U form factor VME cards etc. In addition, based on the Experiments at CERN 1994 ( grey book ) page 370,371 ) overall positive feedback to the definition of CAMAC and FASTBUS software In a complementary way, the hierarchical PCI local bus is the de facto interface interface standards, definitions of standard software access mechanisms for use of all major computer platforms for local subsystems, local memory and video with VME modules are being defined. data. The VMEbus industry like other established bus manufacturers adopt the This paper reports on the current status and directions of this standards PMC mezzanine card environment with PCI protocol. This allows building simple effort - with emphasis on the overlap of European and American High Energy crate interconnects via PCI, multiport access to data and provides a standard way Physics needs and on the overlap of the requirements and directions of the Physics to interface to embedded processors. community with the needs and directions of the wider VME commercial sector. (References: PMC IEEE P1386 Draft, PCI-PCI bridge architecture, PCI Local Bus Spec 2.1 available via the SIG distributors, PCI'95 Proceedings St.Clara March 27-31, Available via 1995 Annabooks San Diego ISBN 0-929392-27-1, Fax: 619-673-1432 ) BR9737160 The architecture of large DAQ systems of the year 2000 and beyond can ABS-136 therefore be seen as a link-switch layer between PCI based DAQ front end units on one side and a CPU farm with PCI and/or SCI interface on the other side. A millenium approach to Data Acquisition: SCI and PCI This DAQ layer contains a large superswitch, being investigated by competing HANS MULLER (CERN) technologies and standards. A. Bogaerts (CERN) ( References: Talks on SCI on DAQ conference at FNAL see http://wwwl.cern.ch/RD24/ slides of talk to ALICE Collaboration pages 12-16 The international SCI standard is on its way to become the computer of 8.6.95 http://sunshine.cern.ch:8080/DAQ PCLALICE.ps ) interconnect of the year 2000 for cost effective implementations of cluster The SCI standard can naturally implement this switch in a uniform and cost computing and to provide very low latency to MPP systems. The PCI bus effective way using a network of SCI ringlets and switches. The RD24 project is is a local bus extension, implemented in all major computer platforms as well constructing a first DAQ demonstrator with PCI-SCI interface to VME, a first in VMEbus as a self configuring system with hierarchical architecture. The 4-ring by 4-ring SCI switch with up to 80 interconnected nodes by integration eventbuilder layer for a millesium DAQ system can therefore be seen as a of SCI components from SCI industry callaborators in particular from Apple, large data routing switch in between numerous local PCI segments on the front Dolphin, IBM, and more. end units side and PCI or SCI interfaces on the CPU farm side. This paper The first eventbuilder skeleton tests yield very good figures beyond 25 kHz describes our proposal for a scalable SCI DAQ system, based on PCI-SCI bridges, event rate for SUN stations, interconnected via SCI ringlets. Increasing speed of optical SCI links and multistage SCI switches. Advantages of using SCI and SCI components, today's availabilty of SCI switches and SCI's built-in scalabilty PCI are amongst others, transparent data access allowing to scale up to data allow us predictions towards 100 kHz for 1 Mbyte events. rates and event sizes of LHC experiments with embedded flow control and event (Reference will be the RD24 Status report 1995, due 16 August 1995 and oral synchronisiation. First RD24 eventbuilding results are reported. presentation to LCRB September 5, 1995) Detailed Description The Scalable Coherent Interface IEEE/ANSI standard has not only proven existence and applicability to Data Acquistion ( RD24 project), it is emerging today like a 'tip of the iceberg' as scalable computer interconnect of the year BR9737161 ABS.132 2000. Industry projects and products range from cost effective cluster computing to low latency MPP interconnect. BaBar On-line Prototype Development (Some Public References: IEEE/ANSI 1596 Standard, Convex Exemplar MPP system, Byte April 1995: article on P6 page 56, Nixdorf PCI-SCI Press G. ARAMS(LBL)